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[AArch64] Refactor the scheduling predicates (2/3) (NFC)
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Authored by evandro on Nov 21 2018, 4:39 PM.

Details

Summary

Refactor the scheduling predicates based on MCInstPredicate. In this case, AArch64InstrInfo::hasShiftedReg().

Diff Detail

Event Timeline

evandro created this revision.Nov 21 2018, 4:39 PM
andreadb added inline comments.Nov 22 2018, 3:31 AM
llvm/lib/Target/AArch64/AArch64SchedPredicates.td
74–79

Same as D54833 and D54777.

def RegShiftedPred : MCSchedPredicate<RegShiftedBody>;

You are inlining the entire body of hasShiftedReg here. You should replace it with this:

def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;

A TIIPredicate is a special kind of MCInstPredicate. See my other comment in D54777.

You should also rewrite RegShiftedFn so that it uses a more readable MCOpcodeSwitchStatement.

evandro marked 2 inline comments as done.Nov 23 2018, 2:45 PM
evandro added inline comments.
llvm/lib/Target/AArch64/AArch64SchedPredicates.td
74–79

Again, I intend to reuse IsArithLogicShiftPred in another patch.

evandro updated this revision to Diff 175146.Nov 23 2018, 4:24 PM
evandro marked an inline comment as done.
andreadb accepted this revision.Nov 23 2018, 4:47 PM

Only a minor nit. Otherwise, it LGTM. Thanks!

llvm/lib/Target/AArch64/AArch64SchedPredicates.td
43–44

Do you still need this? If not, then you can remove it.

This revision is now accepted and ready to land.Nov 23 2018, 4:47 PM
This revision was automatically updated to reflect the committed changes.
evandro marked 2 inline comments as done.Nov 26 2018, 1:51 PM
evandro added inline comments.
llvm/lib/Target/AArch64/AArch64SchedPredicates.td
43–44

Will be using it shortly for Exynos.