[PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instruction

[ZhangKang]

Summary

There are 4 instruction which has Inconsistent ImmMustBeMultipleOf in the function PPCInstrInfo::instrHasImmForm, they are LFS, LFD, STFS, STFD.

For example LFS:

2651  bool PPCInstrInfo::instrHasImmForm(const MachineInstr &MI,
                                   ImmInstrInfo &III, bool PostRA) const {
2653  unsigned Opc = MI.getOpcode();
      ...
2661  III.ImmMustBeMultipleOf = 1;
      ...
  
2664    switch (Opc) {
      ...
2880      case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
      ...
      
2961      case PPC::STXSSPX:
2976        III.ImmMustBeMultipleOf = 4;
      ...
2977        switch(Opc) {
      ...
2983          case PPC::LXSSPX:
2984            if (PostRA) {
2985              if (isVFReg(MI.getOperand(0).getReg()))
2986                III.ImmOpcode = PPC::LXSSP;
2987              else
2988                III.ImmOpcode = PPC::LFS;
2989              break;
2990            }
      ...
            }
      ...        
        }
      ...    
      }

For the ImmInstrInfo::ImmMustBeMultipleOf is used to describe the immediate multiple information of the instruction LFS. So for the same instruction LFS, it should have same immediate multiple information.

But from above code, we can see in the line 2880, the instruction LFS has the immediate multiple 1 byte, but in the line 2988, its value is 4 byte. They are inconsistent.

This bug will result in below pattern can not be optimized.

addi   r2, 99
lxsspx f1, 0, r2

In fact, this pattern should be optimized to:

lfs f1, 99(r2)

[nemanjai]

LGTM.

[ZhangKang]

The test case does not use -mtriple=powerpc64-unknown-linux-gnu option, so on the platform except PowerPC, we will get error. I should modify the test case command line to use the option -mtriple. I have reverted this commit.

[ZhangKang]

Add the optiion -mtriple=powerpc64le-unknown-linux-gnu.

[steven.zhang]

LGTM.

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

case PPC::XFSTOREf64:
     case PPC::LXVX:
       III.ImmOpcode = PPC::LXV;
       III.ImmMustBeMultipleOf = 16;
       break;
     case PPC::LXSSPX:
       if (PostRA) {
         if (isVFReg(MI.getOperand(0).getReg()))
           III.ImmOpcode = PPC::LXSSP;
-        else
+        else {
           III.ImmOpcode = PPC::LFS;
+          III.ImmMustBeMultipleOf = 1;
+        }
         break;
       }
       LLVM_FALLTHROUGH;
     case PPC::XFLOADf32:
       III.ImmOpcode = PPC::DFLOADf32;
       break;
     case PPC::LXSDX:
       if (PostRA) {
         if (isVFReg(MI.getOperand(0).getReg()))
           III.ImmOpcode = PPC::LXSD;
-        else
+        else {
           III.ImmOpcode = PPC::LFD;
+          III.ImmMustBeMultipleOf = 1;
+        }
         break;
       }
       LLVM_FALLTHROUGH;
     case PPC::XFLOADf64:
       III.ImmOpcode = PPC::DFLOADf64;
       break;
     case PPC::STXVX:
       III.ImmOpcode = PPC::STXV;
       III.ImmMustBeMultipleOf = 16;
       break;
     case PPC::STXSSPX:
       if (PostRA) {
         if (isVFReg(MI.getOperand(0).getReg()))
           III.ImmOpcode = PPC::STXSSP;
-        else
+        else {
           III.ImmOpcode = PPC::STFS;
+          III.ImmMustBeMultipleOf = 1;
+        }
         break;
       }
       LLVM_FALLTHROUGH;
     case PPC::XFSTOREf32:
       III.ImmOpcode = PPC::DFSTOREf32;
       break;
     case PPC::STXSDX:
       if (PostRA) {
         if (isVFReg(MI.getOperand(0).getReg()))
           III.ImmOpcode = PPC::STXSD;
-        else
+        else {
           III.ImmOpcode = PPC::STFD;
+          III.ImmMustBeMultipleOf = 1;
+        }
         break;
       }
       LLVM_FALLTHROUGH;
     case PPC::XFSTOREf64:
       III.ImmOpcode = PPC::DFSTOREf64;
       break;
     }
     break;

llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir

+# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole -mcpu=pwr9 %s -o - | FileCheck %s 
+
+---
+name:            testLXSSPX
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
+  - { id: 1, class: g8rc, preferred-register: '' }
+  - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
+  - { id: 3, class: gprc, preferred-register: '' }
+  - { id: 4, class: g8rc, preferred-register: '' }
+  - { id: 5, class: g8rc, preferred-register: '' }
+  - { id: 6, class: g8rc, preferred-register: '' }
+  - { id: 7, class: vssrc, preferred-register: '' }
+  - { id: 8, class: gprc, preferred-register: '' }
+  - { id: 9, class: g8rc, preferred-register: '' }
+  - { id: 10, class: g8rc, preferred-register: '' }
+  - { id: 11, class: g8rc, preferred-register: '' }
+  - { id: 12, class: vssrc, preferred-register: '' }
+  - { id: 13, class: vssrc, preferred-register: '' }
+liveins:
+  - { reg: '$x3', virtual-reg: '%0' }
+  - { reg: '$x4', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x3, $x4
+
+    %1 = COPY $x4
+    %0 = COPY $x3
+    %2 = COPY %1.sub_32
+    %3 = ADDI %2, 1
+    %5 = IMPLICIT_DEF
+    %4 = INSERT_SUBREG %5, killed %3, 1
+    %6 = LI8 97
+    %7 = LXSSPX %0, killed %6, implicit $rm
+    ; CHECK:  lfs [[REG1:[0-9]+]], 97(3)
+    %8 = ADDI %2, 2
+    %10 = IMPLICIT_DEF
+    %9 = INSERT_SUBREG %10, killed %8, 1
+    %11 = LI8 -92
+    %12 = LXSSPX %0, killed %11, implicit $rm
+    ; CHECK-NEXT:  lfs [[REG2:[0-9]+]], -92(3)
+    %13 = XSADDSP killed %7, killed %12
+    ; CHECK-NEXT:  xsaddsp {{[0-9]+}}, [[REG1]], [[REG2]]
+    $f1 = COPY %13
+    BLR8 implicit $lr8, implicit $rm, implicit $f1
+...
+
+
+---
+name:            testLXSDX
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
+  - { id: 1, class: g8rc, preferred-register: '' }
+  - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
+  - { id: 3, class: gprc, preferred-register: '' }
+  - { id: 4, class: g8rc, preferred-register: '' }
+  - { id: 5, class: g8rc, preferred-register: '' }
+  - { id: 6, class: g8rc, preferred-register: '' }
+  - { id: 7, class: vsfrc, preferred-register: '' }
+  - { id: 8, class: gprc, preferred-register: '' }
+  - { id: 9, class: g8rc, preferred-register: '' }
+  - { id: 10, class: g8rc, preferred-register: '' }
+  - { id: 11, class: g8rc, preferred-register: '' }
+  - { id: 12, class: vsfrc, preferred-register: '' }
+  - { id: 13, class: vsfrc, preferred-register: '' }
+liveins:         
+  - { reg: '$x3', virtual-reg: '%0' }
+  - { reg: '$x4', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $x3, $x4
+  
+    %1 = COPY $x4
+    %0 = COPY $x3
+    %2 = COPY %1.sub_32
+    %3 = ADDI %2, 1
+    %5 = IMPLICIT_DEF
+    %4 = INSERT_SUBREG %5, killed %3, 1
+    %6 = LI8 99
+    %7 = LXSDX %0, killed %6, implicit $rm
+    ; CHECK:  lfd [[REG1:[0-9]+]], 99(3)
+    %8 = ADDI %2, 2
+    %10 = IMPLICIT_DEF
+    %9 = INSERT_SUBREG %10, killed %8, 1
+    %11 = LI8 -120
+    %12 = LXSDX %0, killed %11, implicit $rm
+    ; CHECK-NEXT:  lfd [[REG2:[0-9]+]], -120(3)
+    %13 = XSADDDP killed %7, killed %12, implicit $rm
+    ; CHECK-NEXT:  xsadddp {{[0-9]+}}, [[REG1]], [[REG2]]
+    $f1 = COPY %13
+    BLR8 implicit $lr8, implicit $rm, implicit $f1
+...
+
+
+---
+name:            testSTXSSPX
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
+  - { id: 1, class: vssrc, preferred-register: '' }
+  - { id: 2, class: g8rc, preferred-register: '' }
+  - { id: 3, class: g8rc, preferred-register: '' }
+liveins:
+  - { reg: '$x3', virtual-reg: '%0' }
+  - { reg: '$f1', virtual-reg: '%1' }
+  - { reg: '$x5', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x3, $f1, $x5
+
+    %2 = COPY $x5
+    %1 = COPY $f1
+    %0 = COPY $x3
+    %3 = LI8 443
+    STXSSPX %1, %0, killed %3, implicit $rm
+    ; CHECK: stfs {{[0-9]+}}, 443(3)
+    BLR8 implicit $lr8, implicit $rm
+...
+
+
+---
+name:            testSTXSDX
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
+  - { id: 1, class: vsfrc, preferred-register: '' }
+  - { id: 2, class: g8rc, preferred-register: '' }
+  - { id: 3, class: g8rc, preferred-register: '' }
+liveins:
+  - { reg: '$x3', virtual-reg: '%0' }
+  - { reg: '$f1', virtual-reg: '%1' }
+  - { reg: '$x5', virtual-reg: '%2' }
+body:             |
+  bb.0.entry:
+    liveins: $x3, $f1, $x5
+
+    %2 = COPY $x5
+    %1 = COPY $f1
+    %0 = COPY $x3
+    %3 = LI8  7
+    STXSDX %1, %0, killed %3, implicit $rm
+    ; CHECK: stfd {{[0-9]+}}, 7(3)
+    BLR8 implicit $lr8, implicit $rm
+...