[MachineScheduler] Bias physical register immediate assignments

[niravd]

Summary

The machine scheduler currently biases register copies to/from
physical registers to be closer to their point of use / def to
minimize their live ranges. This change extends this to also physical
register assignments from immediate values.

This causes a reduction in reduction in overall register pressure and
minor reduction in spills and indirectly fixes an out of register assertion (PR39391).

Most test changes are from minor instruction reorderings and register
name selection changes and direct consequences of that.

[qcolombet]

Looks reasonable to me.
Could of comments/nitpicks inlined.

llvm/lib/CodeGen/MachineScheduler.cpp

2878 ↗

(On Diff #172997)

In case this instruction has more than one definition, should we check all of them?

3210 ↗

(On Diff #172997)

Dead comment.

[niravd]

Modify move immediate check to check all register definitions are physical. Also fix typo (s/isReg/getReg) that caused all register immediate assignments to be reordered.
This appears to have resolved the isntance of PR26810 in CodeGen/X86/hoist-spill.ll, but otherwise doesn't seem to have an notable effect on code generation.

[qcolombet]

I see a few checks that weaken the check (e.g., -next replaced by regular checks).
Is this expected and why?

llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll

20 ↗

(On Diff #173403)

Given those are check-DAG, why do we have to update them?

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll

15 ↗

(On Diff #173403)

Why do we need to weaken those checks?

llvm/test/CodeGen/X86/pr39391.ll

2 ↗

(On Diff #173403)

Could you give a more meaningful name to the file?
Put the PR number in the comments here.

36 ↗

(On Diff #173403)

Could you get rid of the implicit variables ([0-9]+)?
Use opt -instnamer for that.

[niravd]

Resolve Quentin's comments. Revert some tests which don't need changes after previous bugfix.

[niravd]

llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll

20 ↗

(On Diff #173403)

It's from a limitation of FileCheck. As I understand it, FileCheck will greedily match the first of a DAG line if more than one DAG pattern will match. Putting the specialized makes sure we always associate the LOW_REG assignment with it's corresponding pattern.

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll

15 ↗

(On Diff #173403)

We don't for this one; I've reverted any file that no longer needs changes.

[qcolombet]

LGTM

llvm/trunk/include/llvm/CodeGen/MachineScheduler.h

 /// Base class for GenericScheduler. This class maintains information about
 /// scheduling candidates based on TargetSchedModel making it easy to implement
 /// heuristics for either preRA or postRA scheduling.
 class GenericSchedulerBase : public MachineSchedStrategy {
 public:
   /// Represent the type of SchedCandidate found within a single queue.
   /// pickNodeBidirectional depends on these listed by decreasing priority.
   enum CandReason : uint8_t {
-    NoCand, Only1, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak,
+    NoCand, Only1, PhysReg, RegExcess, RegCritical, Stall, Cluster, Weak,
     RegMax, ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
     TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
 
 #ifndef NDEBUG
   static const char *getReasonStr(GenericSchedulerBase::CandReason Reason);
 #endif
 
   /// Policy for scheduling the next instruction in the candidate's zone.

 bool tryPressure(const PressureChange &TryP,
                  const PressureChange &CandP,
                  GenericSchedulerBase::SchedCandidate &TryCand,
                  GenericSchedulerBase::SchedCandidate &Cand,
                  GenericSchedulerBase::CandReason Reason,
                  const TargetRegisterInfo *TRI,
                  const MachineFunction &MF);
 unsigned getWeakLeft(const SUnit *SU, bool isTop);
-int biasPhysRegCopy(const SUnit *SU, bool isTop);
+int biasPhysReg(const SUnit *SU, bool isTop);
 
 /// GenericScheduler shrinks the unscheduled zone using heuristics to balance
 /// the schedule.
 class GenericScheduler : public GenericSchedulerBase {
 public:
   GenericScheduler(const MachineSchedContext *C):
     GenericSchedulerBase(C), Top(SchedBoundary::TopQID, "TopQ"),
     Bot(SchedBoundary::BotQID, "BotQ") {}
protected:
 
   SUnit *pickNodeBidirectional(bool &IsTopNode);
 
   void pickNodeFromQueue(SchedBoundary &Zone,
                          const CandPolicy &ZonePolicy,
                          const RegPressureTracker &RPTracker,
                          SchedCandidate &Candidate);
 
-  void reschedulePhysRegCopies(SUnit *SU, bool isTop);
+  void reschedulePhysReg(SUnit *SU, bool isTop);
 };
 
 /// PostGenericScheduler - Interface to the scheduling algorithm used by
 /// ScheduleDAGMI.
 ///
 /// Callbacks from ScheduleDAGMI:
 ///   initPolicy -> initialize(DAG) -> registerRoots -> pickNode ...
 class PostGenericScheduler : public GenericSchedulerBase {

llvm/trunk/lib/CodeGen/MachineScheduler.cpp

 }
 
 #ifndef NDEBUG
 const char *GenericSchedulerBase::getReasonStr(
   GenericSchedulerBase::CandReason Reason) {
   switch (Reason) {
   case NoCand:         return "NOCAND    ";
   case Only1:          return "ONLY1     ";
-  case PhysRegCopy:    return "PREG-COPY ";
+  case PhysReg:        return "PHYS-REG  ";
   case RegExcess:      return "REG-EXCESS";
   case RegCritical:    return "REG-CRIT  ";
   case Stall:          return "STALL     ";
   case Cluster:        return "CLUSTER   ";
   case Weak:           return "WEAK      ";
   case RegMax:         return "REG-MAX   ";
   case ResourceReduce: return "RES-REDUCE";
   case ResourceDemand: return "RES-DEMAND";

 
 /// Minimize physical register live ranges. Regalloc wants them adjacent to
 /// their physreg def/use.
 ///
 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
 /// with the operation that produces or consumes the physreg. We'll do this when
 /// regalloc has support for parallel copies.
-int biasPhysRegCopy(const SUnit *SU, bool isTop) {
+int biasPhysReg(const SUnit *SU, bool isTop) {
   const MachineInstr *MI = SU->getInstr();
-  if (!MI->isCopy())
-    return 0;
 
+  if (MI->isCopy()) {
     unsigned ScheduledOper = isTop ? 1 : 0;
     unsigned UnscheduledOper = isTop ? 0 : 1;
     // If we have already scheduled the physreg produce/consumer, immediately
     // schedule the copy.
     if (TargetRegisterInfo::isPhysicalRegister(
             MI->getOperand(ScheduledOper).getReg()))
       return 1;
     // If the physreg is at the boundary, defer it. Otherwise schedule it
     // immediately to free the dependent. We can hoist the copy later.
     bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
     if (TargetRegisterInfo::isPhysicalRegister(
             MI->getOperand(UnscheduledOper).getReg()))
       return AtBoundary ? -1 : 1;
+  }
+
+  if (MI->isMoveImmediate()) {
+    // If we have a move immediate and all successors have been assigned, bias
+    // towards scheduling this later. Make sure all register defs are to
+    // physical registers.
+    bool DoBias = true;
+    for (const MachineOperand &Op : MI->defs()) {
+      if (Op.isReg() && !TargetRegisterInfo::isPhysicalRegister(Op.getReg())) {
+        DoBias = false;
+        break;
+      }
+    }
+
+    if (DoBias)
+      return isTop ? -1 : 1;
+  }
+
   return 0;
 }
 } // end namespace llvm
 
 void GenericScheduler::initCandidate(SchedCandidate &Cand, SUnit *SU,
                                      bool AtTop,
                                      const RegPressureTracker &RPTracker,
                                      RegPressureTracker &TempTracker) {
void GenericScheduler::tryCandidate(SchedCandidate &Cand,
                                     SchedCandidate &TryCand,
                                     SchedBoundary *Zone) const {
   // Initialize the candidate if needed.
   if (!Cand.isValid()) {
     TryCand.Reason = NodeOrder;
     return;
   }
 
-  if (tryGreater(biasPhysRegCopy(TryCand.SU, TryCand.AtTop),
-                 biasPhysRegCopy(Cand.SU, Cand.AtTop),
-                 TryCand, Cand, PhysRegCopy))
+  // Bias PhysReg Defs and copies to their uses and defined respectively.
+  if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop),
+                 biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg))
     return;
 
   // Avoid exceeding the target's limit.
   if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
                                                Cand.RPDelta.Excess,
                                                TryCand, Cand, RegExcess, TRI,
                                                DAG->MF))
     return;
SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
   if (SU->isBottomReady())
     Bot.removeReady(SU);
 
   LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
                     << *SU->getInstr());
   return SU;
 }
 
-void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
+void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
   MachineBasicBlock::iterator InsertPos = SU->getInstr();
   if (!isTop)
     ++InsertPos;
   SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
 
   // Find already scheduled copies with a single physreg dependence and move
   // them just above the scheduled instruction.
   for (SDep &Dep : Deps) {
     if (Dep.getKind() != SDep::Data || !TRI->isPhysicalRegister(Dep.getReg()))
       continue;
     SUnit *DepSU = Dep.getSUnit();
     if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
       continue;
     MachineInstr *Copy = DepSU->getInstr();
-    if (!Copy->isCopy())
+    if (!Copy->isCopy() && !Copy->isMoveImmediate())
       continue;
     LLVM_DEBUG(dbgs() << "  Rescheduling physreg copy ";
                DAG->dumpNode(*Dep.getSUnit()));
     DAG->moveInstruction(Copy, InsertPos);
   }
 }
 
 /// Update the scheduler's state after scheduling a node. This is the same node
 /// that was just returned by pickNode(). However, ScheduleDAGMILive needs to
 /// update it's state based on the current cycle before MachineSchedStrategy
 /// does.
 ///
 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
-/// them here. See comments in biasPhysRegCopy.
+/// them here. See comments in biasPhysReg.
 void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
   if (IsTopNode) {
     SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
     Top.bumpNode(SU);
     if (SU->hasPhysRegUses)
-      reschedulePhysRegCopies(SU, true);
+      reschedulePhysReg(SU, true);
   } else {
     SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.getCurrCycle());
     Bot.bumpNode(SU);
     if (SU->hasPhysRegDefs)
-      reschedulePhysRegCopies(SU, false);
+      reschedulePhysReg(SU, false);
   }
 }
 
 /// Create the standard converging machine scheduler. This will be used as the
 /// default scheduler if the target does not set a default.
 ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) {
   ScheduleDAGMILive *DAG =
       new ScheduleDAGMILive(C, llvm::make_unique<GenericScheduler>(C));

llvm/trunk/lib/Target/X86/X86InstrCompiler.td

def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size),
                      "# dynamic stack allocation",
                      [(X86WinAlloca GR64:$size)]>,
                      Requires<[In64BitMode]>;
 } // SchedRW
 
 // These instructions XOR the frame pointer into a GPR. They are used in some
 // stack protection schemes. These are post-RA pseudos because we only know the
 // frame register after register allocation.
-let Constraints = "$src = $dst", isPseudo = 1, Defs = [EFLAGS] in {
+let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in {
   def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
                   "xorl\t$$FP, $src", []>,
                   Requires<[NotLP64]>, Sched<[WriteALU]>;
   def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src),
                   "xorq\t$$FP $src", []>,
                   Requires<[In64BitMode]>, Sched<[WriteALU]>;
 }
 

 
 //===----------------------------------------------------------------------===//
 // Alias Instructions
 //===----------------------------------------------------------------------===//
 
 // Alias instruction mapping movr0 to xor.
 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
-    isPseudo = 1, AddedComplexity = 10 in
+    isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in
 def MOV32r0  : I<0, Pseudo, (outs GR32:$dst), (ins), "",
                  [(set GR32:$dst, 0)]>, Sched<[WriteZero]>;
 
 // Other widths can also make use of the 32-bit xor, which may have a smaller
 // encoding and avoid partial register updates.
 let AddedComplexity = 10 in {
 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;

llvm/trunk/lib/Target/X86/X86InstrInfo.td

 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
                 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
                 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
                  "mov{q}\t{$src, $dst|$dst, $src}", []>;
 }
 
-let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
 def MOV8ri  : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
                    "mov{b}\t{$src, $dst|$dst, $src}",
                    [(set GR8:$dst, imm:$src)]>;
 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
                    "mov{w}\t{$src, $dst|$dst, $src}",
                    [(set GR16:$dst, imm:$src)]>, OpSize16;
 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
                    "mov{l}\t{$src, $dst|$dst, $src}",
                    [(set GR32:$dst, relocImm:$src)]>, OpSize32;
 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
                        "mov{q}\t{$src, $dst|$dst, $src}",
                        [(set GR64:$dst, i64immSExt32:$src)]>;
 }
-let isReMaterializable = 1 in {
+let isReMaterializable = 1, isMoveImm = 1 in {
 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
                     "movabs{q}\t{$src, $dst|$dst, $src}",
                     [(set GR64:$dst, relocImm:$src)]>;
 }
 
 // Longer forms that use a ModR/M byte. Needed for disassembler
 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
 def MOV8ri_alt  : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),

llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.ll

 
 
 ; FIXME: Should be passing -1
 ; GCN-LABEL: {{^}}test_call_external_void_func_i1_imm:
 ; MESA: s_mov_b32 s36, SCRATCH_RSRC_DWORD
 
 ; MESA-DAG: s_mov_b64 s[0:1], s[36:37]
 
-; GCN: v_mov_b32_e32 v0, 1{{$}}
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1@rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1@rel32@hi+4
+; GCN-DAG: v_mov_b32_e32 v0, 1{{$}}
 ; MESA-DAG: s_mov_b64 s[2:3], s[38:39]
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1@rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1@rel32@hi+4
 
 ; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
 ; GCN-NEXT: s_endpgm
 define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
   call void @external_void_func_i1(i1 true)
   ret void
 }
 
define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
   %var = load volatile i1, i1 addrspace(1)* undef
   call void @external_void_func_i1_zeroext(i1 %var)
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_void_func_i8_imm:
 ; MESA-DAG: s_mov_b32 s33, s3{{$}}
 
-; GCN: v_mov_b32_e32 v0, 0x7b
-; HSA-DAG: s_mov_b32 s4, s33{{$}}
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8@rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8@rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8@rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8@rel32@hi+4
+; GCN-DAG: v_mov_b32_e32 v0, 0x7b
 
+; HSA-DAG: s_mov_b32 s4, s33{{$}}
 ; GCN-DAG: s_mov_b32 s32, s33{{$}}
 
 ; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
 ; GCN-NEXT: s_endpgm
 define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
   call void @external_void_func_i8(i8 123)
   ret void
 }
 
 ; FIXME: don't wait before call
 ; GCN-LABEL: {{^}}test_call_external_void_func_i8_signext:
 ; HSA-DAG: s_mov_b32 s33, s9{{$}}
 ; MESA-DAG: s_mov_b32 s33, s3{{$}}
 
 ; GCN-DAG: buffer_load_sbyte v0
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext@rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_signext@rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext@rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_signext@rel32@hi+4
 
+; GCN-DAG: s_mov_b32 s4, s33
 ; GCN-DAG: s_mov_b32 s32, s3
 
 ; GCN: s_waitcnt vmcnt(0)
 ; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
 ; GCN-NEXT: s_endpgm
 define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
   %var = load volatile i8, i8 addrspace(1)* undef
   call void @external_void_func_i8_signext(i8 %var)
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_void_func_i8_zeroext:
 ; MESA-DAG: s_mov_b32 s33, s3{{$}}
 ; HSA-DAG: s_mov_b32 s33, s9{{$}}
 
 ; GCN-DAG: buffer_load_ubyte v0
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext@rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_zeroext@rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext@rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_zeroext@rel32@hi+4
 
 ; GCN-DAG: s_mov_b32 s32, s33
 
 ; GCN: s_waitcnt vmcnt(0)
 ; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
 ; GCN-NEXT: s_endpgm
 define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
   %var = load volatile i8, i8 addrspace(1)* undef
define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
   call void @external_void_func_i16(i16 123)
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_void_func_i16_signext:
 ; MESA-DAG: s_mov_b32 s33, s3{{$}}
 
 ; GCN-DAG: buffer_load_sshort v0
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_signext@rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_signext@rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_signext@rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_signext@rel32@hi+4
 
 ; GCN-DAG: s_mov_b32 s32, s33
 
 ; GCN: s_waitcnt vmcnt(0)
 ; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
 ; GCN-NEXT: s_endpgm
 define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
   %var = load volatile i16, i16 addrspace(1)* undef
   call void @external_void_func_i16_signext(i16 %var)
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_void_func_i16_zeroext:
 ; MESA-DAG: s_mov_b32 s33, s3{{$}}
 
 
-; GCN-DAG: buffer_load_ushort v0
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_zeroext@rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_zeroext@rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_zeroext@rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_zeroext@rel32@hi+4
 
 ; GCN-DAG: s_mov_b32 s32, s33
 
 ; GCN: s_waitcnt vmcnt(0)
 ; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
 ; GCN-NEXT: s_endpgm
 define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
   %var = load volatile i16, i16 addrspace(1)* undef
   call void @external_void_func_i16_zeroext(i16 %var)
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_void_func_i32_imm:
 ; MESA-DAG: s_mov_b32 s33, s3{{$}}
 
-; GCN: v_mov_b32_e32 v0, 42
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i32@rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i32@rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i32@rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i32@rel32@hi+4
+; GCN-DAG: v_mov_b32_e32 v0, 42
+; GCN-DAG: s_mov_b32 s4, s33
 ; GCN-DAG: s_mov_b32 s32, s33
 
 ; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
 ; GCN-NEXT: s_endpgm
 define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {
   call void @external_void_func_i32(i32 42)
   ret void
 }

 ; GCN-DAG: buffer_store_dword [[VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:12
 
 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:8
 ; GCN-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:12
 
 ; GCN-NOT: s_add_u32 [[SP]]
 ; GCN-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]] offset:4
 ; GCN-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]] offset:8
-; GCN-NEXT: s_swappc_b64
+; GCN: s_swappc_b64
 ; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:16
 ; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:20
 ; GCN-NOT: s_sub_u32 [[SP]]
 
 ; GCN: buffer_store_byte [[LOAD_OUT_VAL0]], off
 ; GCN: buffer_store_dword [[LOAD_OUT_VAL1]], off
 define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 {
   %in.val = alloca { i8, i32 }, align 4, addrspace(5)

llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll

define void @other_arg_use_workgroup_id_z(i32 %arg0) #1 {
   ret void
 }
 
 ; GCN-LABEL: {{^}}kern_indirect_other_arg_use_workgroup_id_x:
 ; GCN: enable_sgpr_workgroup_id_x = 1
 ; GCN: enable_sgpr_workgroup_id_y = 0
 ; GCN: enable_sgpr_workgroup_id_z = 0
 
+; GCN-NOT: s6
 ; GCN-DAG: s_mov_b32 s33, s7
 ; GCN-DAG: v_mov_b32_e32 v0, 0x22b
-
-; GCN-NOT: s6
-; GCN: s_mov_b32 s4, s33
-; GCN-NOT: s6
+; GCN-DAG: s_mov_b32 s4, s33
 ; GCN-DAG: s_mov_b32 s32, s33
+; GCN-NOT: s6
 ; GCN: s_swappc_b64
 define amdgpu_kernel void @kern_indirect_other_arg_use_workgroup_id_x() #1 {
   call void @other_arg_use_workgroup_id_x(i32 555)
   ret void
 }
 
 ; GCN-LABEL: {{^}}kern_indirect_other_arg_use_workgroup_id_y:
 ; GCN: enable_sgpr_workgroup_id_x = 1

 ; GCN-DAG: s_mov_b32 s8, s16
 
 ; GCN-DAG: s_mov_b64 s{{\[}}[[LO_X:[0-9]+]]{{\:}}[[HI_X:[0-9]+]]{{\]}}, s[6:7]
 ; GCN-DAG: s_mov_b64 s{{\[}}[[LO_Y:[0-9]+]]{{\:}}[[HI_Y:[0-9]+]]{{\]}}, s[8:9]
 ; GCN-DAG: s_mov_b64 s{{\[}}[[LO_Z:[0-9]+]]{{\:}}[[HI_Z:[0-9]+]]{{\]}}, s[10:11]
 
 ; GCN: s_swappc_b64
 
-; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:4
-; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], s[[LO_X]]
-; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], s[[HI_X]]
-; GCN: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
-; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], s[[LO_Y]]
-; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], s[[HI_Y]]
-; GCN: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
-; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], s[[LO_Z]]
-; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], s[[HI_Z]]
-; GCN: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
+; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:4
+; GCN-DAG: v_mov_b32_e32 v[[LO1:[0-9]+]], s[[LO_X]]
+; GCN-DAG: v_mov_b32_e32 v[[HI1:[0-9]+]], s[[HI_X]]
+; GCN-DAG: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO1]]:[[HI1]]{{\]}}
+; GCN-DAG: v_mov_b32_e32 v[[LO2:[0-9]+]], s[[LO_Y]]
+; GCN-DAG: v_mov_b32_e32 v[[HI2:[0-9]+]], s[[HI_Y]]
+; GCN-DAG: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO2]]:[[HI2]]{{\]}}
+; GCN-DAG: v_mov_b32_e32 v[[LO3:[0-9]+]], s[[LO_Z]]
+; GCN-DAG: v_mov_b32_e32 v[[HI3:[0-9]+]], s[[HI_Z]]
+; GCN-DAG: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO3]]:[[HI3]]{{\]}}
 ; GCN: ; use
 ; GCN: ; use [[SAVE_X]]
 ; GCN: ; use [[SAVE_Y]]
 ; GCN: ; use [[SAVE_Z]]
 define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz_spill() #1 {
   %alloca = alloca i32, align 4, addrspace(5)
   call void @use_workgroup_id_xyz()
 

llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll

 }
 
 ; Added offset can't be used with VOP3 add
 ; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32:
 ; GCN: s_sub_u32 s6, s5, s4
 ; GCN-DAG: s_movk_i32 s6, 0x204
 
 ; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6
-; CI: v_add_i32_e64 v0, s[6:7], s6, [[SCALED]]
+; CI: v_add_i32_e64 [[VZ:v[0-9]+]], s[6:7], s6, [[SCALED]]
 
 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
-; GFX9: v_add_u32_e32 v0, s6, [[SCALED]]
+; GFX9: v_add_u32_e32 [[VZ:v[0-9]+]], s6, [[SCALED]]
 
-; GCN: v_mul_lo_i32 v0, v0, 9
-; GCN: ds_write_b32 v0, v0
+; GCN: v_mul_lo_i32 [[VZ]], [[VZ]], 9
+; GCN: ds_write_b32 v0, [[VZ]]
 define void @func_other_fi_user_non_inline_imm_offset_i32() #0 {
   %alloca0 = alloca [128 x i32], align 4, addrspace(5)
   %alloca1 = alloca [8 x i32], align 4, addrspace(5)
   %gep0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca0, i32 0, i32 65
   %gep1 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %alloca1, i32 0, i32 0
   store volatile i32 7, i32 addrspace(5)* %gep0
   %ptrtoint = ptrtoint i32 addrspace(5)* %gep1 to i32
   %mul = mul i32 %ptrtoint, 9
   store volatile i32 %mul, i32 addrspace(3)* undef
   ret void
 }
 
 ; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32_vcc_live:
 ; GCN: s_sub_u32 [[DIFF:s[0-9]+]], s5, s4
 ; GCN-DAG: s_movk_i32 [[OFFSET:s[0-9]+]], 0x204
 
 ; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], [[DIFF]], 6
-; CI: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]]
+; CI: v_add_i32_e64 [[VZ:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]]
 
 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]]
-; GFX9: v_add_u32_e32 v0, [[OFFSET]], [[SCALED]]
+; GFX9: v_add_u32_e32 [[VZ:v[0-9]+]], [[OFFSET]], [[SCALED]]
 
-; GCN: v_mul_lo_i32 v0, v0, 9
-; GCN: ds_write_b32 v0, v0
+; GCN: v_mul_lo_i32 [[VZ]], [[VZ]], 9
+; GCN: ds_write_b32 v0, [[VZ]]
 define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 {
   %alloca0 = alloca [128 x i32], align 4, addrspace(5)
   %alloca1 = alloca [8 x i32], align 4, addrspace(5)
   %vcc = call i64 asm sideeffect "; def $0", "={VCC}"()
   %gep0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca0, i32 0, i32 65
   %gep1 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %alloca1, i32 0, i32 0
   store volatile i32 7, i32 addrspace(5)* %gep0
   call void asm sideeffect "; use $0", "{VCC}"(i64 %vcc)

llvm/trunk/test/CodeGen/AMDGPU/local-atomics64.ll

 ; GCN-LABEL: {{^}}lds_atomic_add_noret_i64_offset:
 ; SICIVI-DAG: s_mov_b32 m0
 ; GFX9-NOT: m0
 
 ; SI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
 ; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
 ; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9
 ; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0
-; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
+; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
 ; GCN: ds_add_u64 {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32
 ; GCN: s_endpgm
 define amdgpu_kernel void @lds_atomic_add_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
   %gep = getelementptr i64, i64 addrspace(3)* %ptr, i64 4
   %result = atomicrmw add i64 addrspace(3)* %gep, i64 9 seq_cst
   ret void
 }
 

llvm/trunk/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll

 
 ; IR: UnifiedReturnBlock:
 ; IR: call void @llvm.amdgcn.end.cf(i64 %14)
 ; IR: ret void
 
 
 ; GCN-LABEL: {{^}}multi_divergent_region_exit_ret_ret:
 
-; GCN:      s_mov_b64           [[EXIT1:s\[[0-9]+:[0-9]+\]]], 0
-; GCN:      v_cmp_lt_i32_e32    vcc, 1,
-; GCN:      s_mov_b64           [[EXIT0:s\[[0-9]+:[0-9]+\]]], 0
-; GCN:      s_and_saveexec_b64
-; GCN:      s_xor_b64
+; GCN-DAG:  s_mov_b64           [[EXIT1:s\[[0-9]+:[0-9]+\]]], 0
+; GCN-DAG:  v_cmp_lt_i32_e32    vcc, 1,
+; GCN-DAG:  s_mov_b64           [[EXIT0:s\[[0-9]+:[0-9]+\]]], 0
+; GCN-DAG:  s_and_saveexec_b64
+; GCN-DAG:  s_xor_b64
 
 ; GCN: ; %LeafBlock1
 ; GCN-NEXT: s_mov_b64           [[EXIT0]], exec
 ; GCN-NEXT: v_cmp_ne_u32_e32    vcc, 2,
 ; GCN-NEXT: s_and_b64           [[EXIT1]], vcc, exec
 
 ; GCN: ; %Flow
 ; GCN-NEXT: s_or_saveexec_b64

 ; GCN-DAG:  s_or_b64            [[EXIT1]], [[EXIT1]], [[TMP1]]
 
 ; GCN: ; %Flow4
 ; GCN-NEXT: s_or_b64            exec, exec,
 ; GCN-NEXT: s_and_saveexec_b64  {{s\[[0-9]+:[0-9]+\]}}, [[EXIT1]]
 ; GCN-NEXT: s_xor_b64
 
 ; GCN: ; %exit1
-; GCN:      ds_write_b32
-; GCN:      s_andn2_b64         [[EXIT0]], [[EXIT0]], exec
+; GCN-DAG:  ds_write_b32
+; GCN-DAG:  s_andn2_b64         [[EXIT0]], [[EXIT0]], exec
 
 ; GCN: ; %Flow5
 ; GCN-NEXT: s_or_b64            exec, exec,
 ; GCN-NEXT; s_and_saveexec_b64  {{s\[[0-9]+:[0-9]+\]}}, [[EXIT0]]
 
 ; GCN: ; %exit0
 ; GCN:      buffer_store_dword
 

llvm/trunk/test/CodeGen/AMDGPU/ret.ll

bb:
   call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
   %x = fadd float %arg3, 1.000000e+00
   %a = insertvalue { float, float } undef, float %x, 0
   %b = insertvalue { float, float } %a, float %arg3, 1
   ret { float, float } %b
 }
 
 ; GCN-LABEL: {{^}}vgpr_literal:
-; GCN: v_mov_b32_e32 v4, v0
-; GCN: exp mrt0 v4, v4, v4, v4 done vm
+; GCN: exp mrt0 v0, v0, v0, v0 done vm
 
 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
 ; GCN-DAG: v_mov_b32_e32 v2, 4.0
 ; GCN-DAG: v_mov_b32_e32 v3, -1.0
-; GCN: s_waitcnt expcnt(0)
+; GCN-DAG: s_waitcnt expcnt(0)
 ; GCN-NOT: s_endpgm
 define amdgpu_vs { float, float, float, float } @vgpr_literal([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
 bb:
   call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
   ret { float, float, float, float } { float 1.000000e+00, float 2.000000e+00, float 4.000000e+00, float -1.000000e+00 }
 }
 
 ; GCN: .long 165580
bb:
   %a1 = insertvalue { float, i32, float, i32, i32 } %a0, i32 %s, 1
   %a2 = insertvalue { float, i32, float, i32, i32 } %a1, float %arg3, 2
   %a3 = insertvalue { float, i32, float, i32, i32 } %a2, i32 %arg1, 3
   %a4 = insertvalue { float, i32, float, i32, i32 } %a3, i32 %arg2, 4
   ret { float, i32, float, i32, i32 } %a4
 }
 
 ; GCN-LABEL: {{^}}structure_literal:
-; GCN: v_mov_b32_e32 v3, v0
-; GCN: exp mrt0 v3, v3, v3, v3 done vm
+; GCN: exp mrt0 v0, v0, v0, v0 done vm
 
 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
 ; GCN-DAG: s_mov_b32 s0, 2
 ; GCN-DAG: s_mov_b32 s1, 3
 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
 ; GCN-DAG: v_mov_b32_e32 v2, 4.0
-; GCN: s_waitcnt expcnt(0)
+; GCN-DAG: s_waitcnt expcnt(0)
 define amdgpu_vs { { float, i32 }, { i32, <2 x float> } } @structure_literal([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
 bb:
   call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
   ret { { float, i32 }, { i32, <2 x float> } } { { float, i32 } { float 1.000000e+00, i32 2 }, { i32, <2 x float> } { i32 3, <2 x float> <float 2.000000e+00, float 4.000000e+00> } }
 }
 
 ; GCN-LABEL: {{^}}ret_return_to_epilog_pseudo_size:
 ; GCN: codeLenInByte = 0{{$}}

llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll

 ; CHECK-NEXT:    cvtsi2ssq %rax, %xmm2
 ; CHECK-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
 ; CHECK-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
 ; CHECK-NEXT:    movaps %xmm0, 0
 ; CHECK-NEXT:  LBB0_1: ## %bb4
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    callq _xxGetOffsetForCode
+; CHECK-NEXT:    movq %rbx, %rdi
 ; CHECK-NEXT:    xorl %esi, %esi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    movq %rbx, %rdi
 ; CHECK-NEXT:    callq _xxCalculateMidType
 ; CHECK-NEXT:    cmpl $1, %eax
 ; CHECK-NEXT:    jne LBB0_1
 ; CHECK-NEXT:  ## %bb.2: ## %bb26
 ; CHECK-NEXT:    ## in Loop: Header=BB0_1 Depth=1
 ; CHECK-NEXT:    cmpq $1048576, %r14 ## imm = 0x100000
 ; CHECK-NEXT:    jne LBB0_1
 ; CHECK-NEXT:    jmp LBB0_3

llvm/trunk/test/CodeGen/X86/anyext.ll

 ; X32-NEXT:    divw {{[0-9]+}}(%esp)
 ; X32-NEXT:    # kill: def $ax killed $ax def $eax
 ; X32-NEXT:    andl $1, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: bar:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    divw %si
 ; X64-NEXT:    # kill: def $ax killed $ax def $eax
 ; X64-NEXT:    andl $1, %eax
 ; X64-NEXT:    retq
   %q = trunc i32 %p to i16
   %r = udiv i16 %q, %x
   %s = zext i16 %r to i32
   %t = and i32 %s, 1
   ret i32 %t
 }

llvm/trunk/test/CodeGen/X86/atomic_mi.ll

 ; X32-NEXT:    pushl %edi
 ; X32-NEXT:    pushl %esi
 ; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $24, %esp
 ; X32-NEXT:    .cfi_offset %esi, -20
 ; X32-NEXT:    .cfi_offset %edi, -16
 ; X32-NEXT:    .cfi_offset %ebx, -12
 ; X32-NEXT:    movl 20(%ebp), %esi
+; X32-NEXT:    movl 8(%ebp), %edi
 ; X32-NEXT:    xorl %eax, %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    xorl %ecx, %ecx
 ; X32-NEXT:    xorl %ebx, %ebx
-; X32-NEXT:    movl 8(%ebp), %edi
 ; X32-NEXT:    lock cmpxchg8b (%edi,%esi,8)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; X32-NEXT:    fldl {{[0-9]+}}(%esp)
 ; X32-NEXT:    faddl 12(%ebp)
 ; X32-NEXT:    fstpl (%esp)
 ; X32-NEXT:    movl (%esp), %ebx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx

llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll

 ; X32-NEXT:    movb $7, %cl
 ; X32-NEXT:    movl $999, %edx # imm = 0x3E7
 ; X32-NEXT:    xorl %edi, %edi
 ; X32-NEXT:    retl
 ;
 ; WIN64-LABEL: test_argMultiRet:
 ; WIN64:       # %bb.0:
 ; WIN64-NEXT:    vaddsd __real@{{.*}}(%rip), %xmm1, %xmm1
+; WIN64-NEXT:    movl $999, %edx # imm = 0x3E7
 ; WIN64-NEXT:    movl $4, %eax
 ; WIN64-NEXT:    movb $7, %cl
-; WIN64-NEXT:    movl $999, %edx # imm = 0x3E7
 ; WIN64-NEXT:    retq
 ;
 ; LINUXOSX64-LABEL: test_argMultiRet:
 ; LINUXOSX64:       # %bb.0:
 ; LINUXOSX64-NEXT:    vaddsd {{.*}}(%rip), %xmm1, %xmm1
+; LINUXOSX64-NEXT:    movl $999, %edx # imm = 0x3E7
 ; LINUXOSX64-NEXT:    movl $4, %eax
 ; LINUXOSX64-NEXT:    movb $7, %cl
-; LINUXOSX64-NEXT:    movl $999, %edx # imm = 0x3E7
 ; LINUXOSX64-NEXT:    retq
   %6 = fadd double %1, 5.000000e+00
   %7 = insertvalue %struct.complex undef, float %0, 0
   %8 = insertvalue %struct.complex %7, double %6, 1
   %9 = insertvalue %struct.complex %8, i32 4, 2
   %10 = insertvalue %struct.complex %9, i8 7, 3
   %11 = insertvalue %struct.complex %10, i64 999, 4
   ret %struct.complex %11
 }

llvm/trunk/test/CodeGen/X86/bss_pagealigned.ll

 ; RUN: llc --code-model=kernel <%s -asm-verbose=0 | FileCheck %s
 ; PR4933
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
 %struct.kmem_cache_order_objects = type { i64 }
 declare i8* @memset(i8*, i32, i64)
 define void @unxlate_dev_mem_ptr(i64 %phis, i8* %addr) nounwind {
   %pte.addr.i = alloca %struct.kmem_cache_order_objects*
   %call8 = call i8* @memset(i8* bitcast ([512 x %struct.kmem_cache_order_objects]* @bm_pte to i8*), i32 0, i64 4096)
-; CHECK: movq    $bm_pte, %rdi
+; CHECK:      movl    $4096, %edx
+; CHECK-NEXT: movq    $bm_pte, %rdi
 ; CHECK-NEXT: xorl    %esi, %esi
-; CHECK-NEXT: movl    $4096, %edx
 ; CHECK-NEXT: callq   memset
   ret void
 }
 @bm_pte = internal global [512 x %struct.kmem_cache_order_objects] zeroinitializer, section ".bss.page_aligned", align 4096
 ; CHECK: .section        .bss.page_aligned,"aw",@nobits
 ; CHECK-NEXT: .p2align  12
 ; CHECK-NEXT: bm_pte:
 ; CHECK-NEXT: .zero   4096
 ; CHECK-NEXT: .size   bm_pte, 4096

llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll

 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    movl %ecx, %eax
 ; CHECK-NEXT:    cltd
 ; CHECK-NEXT:    idivl %ebx
 ; CHECK-NEXT:    movl %eax, %esi
 ; CHECK-NEXT:    testl $-256, %edi
 ; CHECK-NEXT:    je .LBB3_4
 ; CHECK-NEXT:  .LBB3_5:
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divl %ebx
 ; CHECK-NEXT:    jmp .LBB3_6
 ; CHECK-NEXT:  .LBB3_1:
 ; CHECK-NEXT:    movzbl %cl, %eax
 ; CHECK-NEXT:    # kill: def $eax killed $eax def $ax
 ; CHECK-NEXT:    divb %bl
 ; CHECK-NEXT:    movzbl %al, %esi
 ; CHECK-NEXT:    testl $-256, %edi

llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll

 ; CHECK-NEXT:    orq %rsi, %rcx
 ; CHECK-NEXT:    shrq $32, %rcx
 ; CHECK-NEXT:    je .LBB0_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    cqto
 ; CHECK-NEXT:    idivq %rsi
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB0_1:
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divl %esi
 ; CHECK-NEXT:    # kill: def $eax killed $eax def $rax
 ; CHECK-NEXT:    retq
   %result = sdiv i64 %a, %b
   ret i64 %result
 }
 
 define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: Test_get_remainder:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    movq %rdi, %rcx
 ; CHECK-NEXT:    orq %rsi, %rcx
 ; CHECK-NEXT:    shrq $32, %rcx
 ; CHECK-NEXT:    je .LBB1_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    cqto
 ; CHECK-NEXT:    idivq %rsi
 ; CHECK-NEXT:    movq %rdx, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB1_1:
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divl %esi
 ; CHECK-NEXT:    movl %edx, %eax
 ; CHECK-NEXT:    retq
   %result = srem i64 %a, %b
   ret i64 %result
 }
 
 define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: Test_get_quotient_and_remainder:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    movq %rdi, %rcx
 ; CHECK-NEXT:    orq %rsi, %rcx
 ; CHECK-NEXT:    shrq $32, %rcx
 ; CHECK-NEXT:    je .LBB2_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    cqto
 ; CHECK-NEXT:    idivq %rsi
 ; CHECK-NEXT:    addq %rdx, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB2_1:
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divl %esi
 ; CHECK-NEXT:    # kill: def $edx killed $edx def $rdx
 ; CHECK-NEXT:    # kill: def $eax killed $eax def $rax
 ; CHECK-NEXT:    addq %rdx, %rax
 ; CHECK-NEXT:    retq
   %resultdiv = sdiv i64 %a, %b
   %resultrem = srem i64 %a, %b
   %result = add i64 %resultdiv, %resultrem
   ret i64 %result
 }

llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll

 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset %rbx, -16
 ; CHECK-NEXT:    movq %rcx, %rbx
 ; CHECK-NEXT:    movq %rsi, %rax
 ; CHECK-NEXT:    xorl %esi, %esi
 ; CHECK-NEXT:    movq %r8, %rcx
 ; CHECK-NEXT:    lock cmpxchg16b (%rdi)
 ; CHECK-NEXT:    sete %sil
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
   %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
   %success = extractvalue { i128, i1 } %pair, 1
   %mask = zext i1 %success to i128
   ret i128 %mask
 }

llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK
 
 ; Basic 128-bit cmpxchg
 define void @t1(i128* nocapture %p) nounwind ssp {
 ; CHECK-LABEL: t1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    movl $1, %ebx
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    movl $1, %ebx
 ; CHECK-NEXT:    lock cmpxchg16b (%rdi)
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    retq
 entry:
   %r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst
   ret void
 }
 
 ; FIXME: Handle 128-bit atomicrmw/load atomic/store atomic

llvm/trunk/test/CodeGen/X86/code-model-elf-memset.ll

 
 define i32 @main() #0 {
 ; SMALL-PIC-LABEL: main:
 ; SMALL-PIC:       # %bb.0: # %entry
 ; SMALL-PIC-NEXT:    subq $424, %rsp # imm = 0x1A8
 ; SMALL-PIC-NEXT:    .cfi_def_cfa_offset 432
 ; SMALL-PIC-NEXT:    movl $0, {{[0-9]+}}(%rsp)
 ; SMALL-PIC-NEXT:    leaq {{[0-9]+}}(%rsp), %rdi
-; SMALL-PIC-NEXT:    xorl %esi, %esi
 ; SMALL-PIC-NEXT:    movl $400, %edx # imm = 0x190
+; SMALL-PIC-NEXT:    xorl %esi, %esi
 ; SMALL-PIC-NEXT:    callq memset@PLT
 ; SMALL-PIC-NEXT:    xorl %eax, %eax
 ; SMALL-PIC-NEXT:    addq $424, %rsp # imm = 0x1A8
 ; SMALL-PIC-NEXT:    .cfi_def_cfa_offset 8
 ; SMALL-PIC-NEXT:    retq
 ;
 ; MEDIUM-PIC-LABEL: main:
 ; MEDIUM-PIC:       # %bb.0: # %entry
 ; MEDIUM-PIC-NEXT:    subq $424, %rsp # imm = 0x1A8
 ; MEDIUM-PIC-NEXT:    .cfi_def_cfa_offset 432
 ; MEDIUM-PIC-NEXT:    movl $0, {{[0-9]+}}(%rsp)
 ; MEDIUM-PIC-NEXT:    leaq {{[0-9]+}}(%rsp), %rdi
-; MEDIUM-PIC-NEXT:    xorl %esi, %esi
 ; MEDIUM-PIC-NEXT:    movl $400, %edx # imm = 0x190
+; MEDIUM-PIC-NEXT:    xorl %esi, %esi
 ; MEDIUM-PIC-NEXT:    callq memset@PLT
 ; MEDIUM-PIC-NEXT:    xorl %eax, %eax
 ; MEDIUM-PIC-NEXT:    addq $424, %rsp # imm = 0x1A8
 ; MEDIUM-PIC-NEXT:    .cfi_def_cfa_offset 8
 ; MEDIUM-PIC-NEXT:    retq
 ;
 ; LARGE-PIC-LABEL: main:
 ; LARGE-PIC:       # %bb.0: # %entry
 ; LARGE-PIC-NEXT:    subq $424, %rsp # imm = 0x1A8
 ; LARGE-PIC-NEXT:    .cfi_def_cfa_offset 432
 ; LARGE-PIC-NEXT:  .L0$pb:
-; LARGE-PIC-NEXT:    leaq .L0$pb(%rip), %rax
+; LARGE-PIC-NEXT:    leaq .L0${{.*}}(%rip), %rax
 ; LARGE-PIC-NEXT:    movabsq $_GLOBAL_OFFSET_TABLE_-.L0$pb, %rcx
 ; LARGE-PIC-NEXT:    addq %rax, %rcx
 ; LARGE-PIC-NEXT:    movl $0, {{[0-9]+}}(%rsp)
 ; LARGE-PIC-NEXT:    leaq {{[0-9]+}}(%rsp), %rdi
 ; LARGE-PIC-NEXT:    movabsq $memset@GOT, %rax
-; LARGE-PIC-NEXT:    xorl %esi, %esi
 ; LARGE-PIC-NEXT:    movl $400, %edx # imm = 0x190
+; LARGE-PIC-NEXT:    xorl %esi, %esi
 ; LARGE-PIC-NEXT:    callq *(%rcx,%rax)
 ; LARGE-PIC-NEXT:    xorl %eax, %eax
 ; LARGE-PIC-NEXT:    addq $424, %rsp # imm = 0x1A8
 ; LARGE-PIC-NEXT:    .cfi_def_cfa_offset 8
 ; LARGE-PIC-NEXT:    retq
 entry:
   %retval = alloca i32, align 4
   %a = alloca [100 x i32], align 16

llvm/trunk/test/CodeGen/X86/combine-srem.ll

 ; CHECK-NEXT:    movl %esi, %eax
 ; CHECK-NEXT:    cltd
 ; CHECK-NEXT:    idivl %edi
 ; CHECK-NEXT:    movl %edx, %esi
 ; CHECK-NEXT:    movl %ecx, %eax
 ; CHECK-NEXT:    cltd
 ; CHECK-NEXT:    idivl %esi
 ; CHECK-NEXT:    movl %edx, %edi
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movl %ecx, %eax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divl %esi
 ; CHECK-NEXT:    andl %edi, %eax
 ; CHECK-NEXT:    retq
   %B17 = or i32 0, 2147483647
   %L6 = load i32, i32* undef
   %B11 = sdiv i32 %B17, %L6
   %B13 = udiv i32 %B17, %L6
   %B14 = srem i32 %B11, %B13

llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll

 ; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s
 ; RUN: opt -strip-debug < %s | llc -mtriple=x86_64-linux | FileCheck %s
 ; http://llvm.org/PR19051. Minor code-motion difference with -g.
 ; Presence of debug info shouldn't affect the codegen. Make sure that
 ; we generated the same code sequence with and without debug info. 
 ;
 ; CHECK:      callq   _Z3fooPcjPKc
 ; CHECK:      callq   _Z3fooPcjPKc
 ; CHECK:      movq    %rsp, %rdi
-; CHECK:      movl    $4, %esi
 ; CHECK:      testl   {{%[a-z]+}}, {{%[a-z]+}}
 ; CHECK:      je     .LBB0_4
+; CHECK:      movl    $4, %esi
 
 ; Regenerate test with this command: 
 ;   clang++ -emit-llvm -S -O2 -g
 ; from this source:
 ;
 ; extern void foo(char *dst,unsigned siz,const char *src);
 ; extern const char * i2str(int);
 ;

llvm/trunk/test/CodeGen/X86/divrem.ll

 ; X32-NEXT:    movw %dx, (%ecx)
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: ui16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdx, %r8
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
+; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    divw %si
 ; X64-NEXT:    movw %ax, (%r8)
 ; X64-NEXT:    movw %dx, (%rcx)
 ; X64-NEXT:    retq
   %r = udiv i16 %x, %y
   %t = urem i16 %x, %y
   store i16 %r, i16* %p
   store i16 %t, i16* %q

llvm/trunk/test/CodeGen/X86/known-bits.ll

 ; X32-NEXT:    vpextrd $2, %xmm1, %edi
 ; X32-NEXT:    vpextrd $2, %xmm0, %esi
 ; X32-NEXT:    vpextrd $3, %xmm1, %ebx
 ; X32-NEXT:    vpextrd $3, %xmm0, %ebp
 ; X32-NEXT:    .p2align 4, 0x90
 ; X32-NEXT:  .LBB0_1: # %CF
 ; X32-NEXT:    # =>This Loop Header: Depth=1
 ; X32-NEXT:    # Child Loop BB0_2 Depth 2
-; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X32-NEXT:    divl {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
 ; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    divl {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
 ; X32-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X32-NEXT:    divl (%esp) # 4-byte Folded Reload
 ; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    divl (%esp) # 4-byte Folded Reload
 ; X32-NEXT:    movl %edi, %eax
-; X32-NEXT:    divl %esi
 ; X32-NEXT:    xorl %edx, %edx
+; X32-NEXT:    divl %esi
 ; X32-NEXT:    movl %ebx, %eax
+; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    divl %ebp
 ; X32-NEXT:    .p2align 4, 0x90
 ; X32-NEXT:  .LBB0_2: # %CF237
 ; X32-NEXT:    # Parent Loop BB0_1 Depth=1
 ; X32-NEXT:    # => This Inner Loop Header: Depth=2
 ; X32-NEXT:    testb %cl, %cl
 ; X32-NEXT:    jne .LBB0_2
 ; X32-NEXT:    jmp .LBB0_1

 ; X64-NEXT:    vpextrd $2, %xmm1, %edi
 ; X64-NEXT:    vpextrd $2, %xmm0, %ebx
 ; X64-NEXT:    vpextrd $3, %xmm1, %ecx
 ; X64-NEXT:    vpextrd $3, %xmm0, %ebp
 ; X64-NEXT:    .p2align 4, 0x90
 ; X64-NEXT:  .LBB0_1: # %CF
 ; X64-NEXT:    # =>This Loop Header: Depth=1
 ; X64-NEXT:    # Child Loop BB0_2 Depth 2
-; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    movl %r8d, %eax
-; X64-NEXT:    divl %r9d
 ; X64-NEXT:    xorl %edx, %edx
+; X64-NEXT:    divl %r9d
 ; X64-NEXT:    movl %r10d, %eax
-; X64-NEXT:    divl %r11d
 ; X64-NEXT:    xorl %edx, %edx
+; X64-NEXT:    divl %r11d
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    divl %ebx
 ; X64-NEXT:    xorl %edx, %edx
+; X64-NEXT:    divl %ebx
 ; X64-NEXT:    movl %ecx, %eax
+; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    divl %ebp
 ; X64-NEXT:    .p2align 4, 0x90
 ; X64-NEXT:  .LBB0_2: # %CF237
 ; X64-NEXT:    # Parent Loop BB0_1 Depth=1
 ; X64-NEXT:    # => This Inner Loop Header: Depth=2
 ; X64-NEXT:    testb %sil, %sil
 ; X64-NEXT:    jne .LBB0_2
 ; X64-NEXT:    jmp .LBB0_1

llvm/trunk/test/CodeGen/X86/machine-cse.ll

 ; CHECK-NEXT:  # %bb.1: # %sw.bb
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    jne .LBB1_4
 ; CHECK-NEXT:  # %bb.2: # %if.end34
 ; CHECK-NEXT:    pushq %rax
 ; CHECK-NEXT:    imull %edi, %esi
 ; CHECK-NEXT:    leal (%rsi,%rsi,2), %esi
-; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    # kill: def $edi killed $edi killed $rdi
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    callq printf
 ; CHECK-NEXT:    addq $8, %rsp
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB1_3: # %for.body53.us
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    jmp .LBB1_3
 ; CHECK-NEXT:  .LBB1_4: # %sw.bb307
 ; CHECK-NEXT:    retq

llvm/trunk/test/CodeGen/X86/memset-nonzero.ll

; AVX-NEXT:    retq
   ret void
 }
 
 define void @memset_256_nonzero_bytes(i8* %x) {
 ; SSE-LABEL: memset_256_nonzero_bytes:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    pushq %rax
 ; SSE-NEXT:    .cfi_def_cfa_offset 16
-; SSE-NEXT:    movl $42, %esi
 ; SSE-NEXT:    movl $256, %edx # imm = 0x100
+; SSE-NEXT:    movl $42, %esi
 ; SSE-NEXT:    callq memset
 ; SSE-NEXT:    popq %rax
 ; SSE-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-NEXT:    retq
 ;
 ; SSE2FAST-LABEL: memset_256_nonzero_bytes:
 ; SSE2FAST:       # %bb.0:
 ; SSE2FAST-NEXT:    movaps {{.*#+}} xmm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]

llvm/trunk/test/CodeGen/X86/misched-code-difference-with-debug.ll

 
 %class.C = type { i8 }
 
 @argc = global i8 0, align 1, !dbg !0
 
 declare i32 @test_function(%class.C*, i8 signext, i8 signext, i8 signext, ...)
 ; CHECK-LABEL: test_without_debug
 ; CHECK: movl [[A:%[a-z]+]], [[B:%[a-z]+]]
-; CHECK-NEXT: movl [[A]], [[C:%[a-z]+]]
+; CHECK: movl [[A]], [[C:%[a-z]+]]
 
 define void @test_without_debug() {
 entry:
   %c = alloca %class.C, align 1
   %0 = load i8, i8* @argc, align 1
   %conv = sext i8 %0 to i32
   %call = call i32 (%class.C*, i8, i8, i8, ...) @test_function(%class.C* %c, i8 signext 0, i8 signext %0, i8 signext 0, i32 %conv)
   %1 = load i8, i8* @argc, align 1
   %call2 = call i32 (%class.C*, i8, i8, i8, ...) @test_function(%class.C* %c, i8 signext 0, i8 signext %1, i8 signext 0, i32 %conv)
   ret void
 }
 ; CHECK-LABEL: test_with_debug
 ; CHECK: movl [[A]], [[B]]
-; CHECK-NEXT: movl [[A]], [[C]]
+; CHECK: movl [[A]], [[C]]
 
 define void @test_with_debug() !dbg !17 {
 entry:
   %c = alloca %class.C, align 1
   %0 = load i8, i8* @argc, align 1
   tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !22, metadata !23), !dbg !24
   %conv = sext i8 %0 to i32
   tail call void @llvm.dbg.value(metadata %class.C* %c, i64 0, metadata !21, metadata !25), !dbg !24

llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc %s -O2 -mtriple=i686-unknown-linux-gnu -o - | FileCheck %s
+
+@f = global i8* zeroinitializer
+
+; PR39391 - The load of %v1 should be scheduled before the zeroing of the A-D registers.
+
+define void @g() #0 {
+; CHECK-LABEL: g:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %ebp
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    .cfi_offset %ebp, -8
+; CHECK-NEXT:    movl %esp, %ebp
+; CHECK-NEXT:    .cfi_def_cfa_register %ebp
+; CHECK-NEXT:    pushl %ebx
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    subl $16, %esp
+; CHECK-NEXT:    .cfi_offset %esi, -16
+; CHECK-NEXT:    .cfi_offset %ebx, -12
+; CHECK-NEXT:    movl f, %esi
+; CHECK-NEXT:    movb (%esi), %al
+; CHECK-NEXT:    movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    xorl %ebx, %ebx
+; CHECK-NEXT:    lock cmpxchg8b (%esi)
+; CHECK-NEXT:    cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
+; CHECK-NEXT:    jne .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %k.end
+; CHECK-NEXT:  .LBB0_1: # %.
+; CHECK-NEXT:    calll m
+entry:
+  %p = load i8*, i8** @f
+  %v1 = load atomic i8, i8* %p monotonic, align 1
+  %d.h.h.h.h.h = bitcast i8* %p to i64*
+  %v2 = load atomic i64, i64* %d.h.h.h.h.h monotonic, align 8
+  %j.h = icmp eq i8 %v1, 0
+  br i1 %j.h, label %k.end, label %.
+
+.:                                                ; preds = %entry
+  %v3 = call i32 @m()
+  unreachable
+
+k.end:                                            ; preds = %entry
+  unreachable
+}
+
+declare i32 @m()
+
+attributes #0 = { "no-frame-pointer-elim-non-leaf" }

llvm/trunk/test/CodeGen/X86/patchpoint.ll

; CHECK-NEXT: callq *%r11
   ret i64 %result
 }
 
 declare i64 @consume_attributes(i64, i8* nest, i64)
 define i64 @test_patchpoint_with_attributes() {
 entry:
 ; CHECK-LABEL: test_patchpoint_with_attributes:
 ; CHECK: movl $42, %edi
-; CHECK: xorl %r10d, %r10d
 ; CHECK: movl $17, %esi
+; CHECK: xorl %r10d, %r10d
 ; CHECK: movabsq $_consume_attributes, %r11
 ; CHECK-NEXT: callq *%r11
 ; CHECK-NEXT: xchgw %ax, %ax
 ; CHECK: retq
   %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 21, i32 15, i8* bitcast (i64 (i64, i8*, i64)* @consume_attributes to i8*), i32 3, i64 42, i8* nest null, i64 17)
   ret i64 %result
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)

llvm/trunk/test/CodeGen/X86/pr32282.ll

 ; X64-NEXT:    orq %rcx, %rdx
 ; X64-NEXT:    shrq $32, %rdx
 ; X64-NEXT:    je .LBB0_1
 ; X64-NEXT:  # %bb.2:
 ; X64-NEXT:    cqto
 ; X64-NEXT:    idivq %rcx
 ; X64-NEXT:    jmp .LBB0_3
 ; X64-NEXT:  .LBB0_1:
-; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    # kill: def $eax killed $eax killed $rax
+; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    divl %ecx
 ; X64-NEXT:    # kill: def $eax killed $eax def $rax
 ; X64-NEXT:  .LBB0_3:
 ; X64-NEXT:    testq %rax, %rax
 ; X64-NEXT:    setne -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    retq
   %1 = alloca i8, align 1
   %2 = load i64, i64* @d, align 8

llvm/trunk/test/CodeGen/X86/pr36865.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple x86_64-unknown-linux-gnu < %s | FileCheck %s
 
 define void @main() {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subq $424, %rsp # imm = 0x1A8
 ; CHECK-NEXT:    .cfi_def_cfa_offset 432
 ; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rdi
-; CHECK-NEXT:    xorl %esi, %esi
 ; CHECK-NEXT:    movl $400, %edx # imm = 0x190
+; CHECK-NEXT:    xorl %esi, %esi
 ; CHECK-NEXT:    callq memset
 ; CHECK-NEXT:    movl {{[0-9]+}}(%rsp), %eax
 ; CHECK-NEXT:    movl (%rax), %ecx
 ; CHECK-NEXT:    addl 0, %eax
 ; CHECK-NEXT:    addl %ecx, %eax
 ; CHECK-NEXT:    addl %ecx, %eax
 ; CHECK-NEXT:    addl {{[0-9]+}}(%rsp), %eax
 ; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%rsp)

llvm/trunk/test/CodeGen/X86/pr38865.ll

 
 define void @e() nounwind {
 ; CHECK-LABEL: e:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushq %rbx # encoding: [0x53]
 ; CHECK-NEXT:    subl $528, %esp # encoding: [0x81,0xec,0x10,0x02,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x210
 ; CHECK-NEXT:    leal {{[0-9]+}}(%rsp), %ebx # encoding: [0x8d,0x9c,0x24,0x08,0x01,0x00,0x00]
+; CHECK-NEXT:    movl %ebx, %edi # encoding: [0x89,0xdf]
 ; CHECK-NEXT:    movl $c, %esi # encoding: [0xbe,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: c, kind: FK_Data_4
 ; CHECK-NEXT:    movl $260, %edx # encoding: [0xba,0x04,0x01,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x104
-; CHECK-NEXT:    movl %ebx, %edi # encoding: [0x89,0xdf]
 ; CHECK-NEXT:    callq memcpy # encoding: [0xe8,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: memcpy-4, kind: FK_PCRel_4
 ; CHECK-NEXT:    movl $32, %ecx # encoding: [0xb9,0x20,0x00,0x00,0x00]
 ; CHECK-NEXT:    movl %esp, %edi # encoding: [0x89,0xe7]
 ; CHECK-NEXT:    movl %ebx, %esi # encoding: [0x89,0xde]
 ; CHECK-NEXT:    rep;movsq (%esi), %es:(%edi) # encoding: [0xf3,0x67,0x48,0xa5]
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x67,0x8b,0x84,0x24,0x08,0x02,0x00,0x00]
 ; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp) # encoding: [0x67,0x89,0x84,0x24,0x00,0x01,0x00,0x00]

llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll

 define <3 x i64> @test_ulong_div(<3 x i64> %num, <3 x i64> %div) {
 ; CHECK-LABEL: test_ulong_div:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq %rdx, %r10
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divq %rcx
 ; CHECK-NEXT:    movq %rax, %rcx
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divq %r8
 ; CHECK-NEXT:    movq %rax, %rsi
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movq %r10, %rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divq %r9
 ; CHECK-NEXT:    movq %rax, %rdi
 ; CHECK-NEXT:    movq %rcx, %rax
 ; CHECK-NEXT:    movq %rsi, %rdx
 ; CHECK-NEXT:    movq %rdi, %rcx
 ; CHECK-NEXT:    retq
   %div.r = udiv <3 x i64> %num, %div
   ret <3 x i64>  %div.r

 ; CHECK: test_ulong_rem
 define <5 x i64> @test_ulong_rem(<5 x i64> %num, <5 x i64> %rem) {
 ; CHECK-LABEL: test_ulong_rem:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq %rdx, %rax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divq {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq %rdx, %xmm0
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divq {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq %rdx, %xmm1
 ; CHECK-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movq %r8, %rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divq {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq %rdx, %xmm0
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movq %rcx, %rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divq {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq %rdx, %xmm2
 ; CHECK-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
-; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movq %r9, %rax
+; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    divq {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq %rdx, 32(%rdi)
 ; CHECK-NEXT:    movdqa %xmm2, 16(%rdi)
 ; CHECK-NEXT:    movdqa %xmm1, (%rdi)
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
   %rem.r = urem <5 x i64> %num, %rem
   ret <5 x i64>  %rem.r

llvm/trunk/test/CodeGen/X86/shrink_vmul-widen.ll

 ; X86-AVX1-NEXT:    divl %ecx
 ; X86-AVX1-NEXT:    movl %edx, (%esp) # 4-byte Spill
 ; X86-AVX1-NEXT:    vmovd %xmm2, %eax
 ; X86-AVX1-NEXT:    vmovd %xmm3, %ecx
 ; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %ecx
 ; X86-AVX1-NEXT:    movl %edx, %ebp
 ; X86-AVX1-NEXT:    vpextrd $3, %xmm0, %eax
-; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    vpextrd $3, %xmm1, %ecx
+; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %ecx
 ; X86-AVX1-NEXT:    movl %edx, %ebx
-; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    vpextrd $2, %xmm0, %eax
 ; X86-AVX1-NEXT:    vpextrd $2, %xmm1, %esi
+; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %esi
 ; X86-AVX1-NEXT:    movl %edx, %esi
-; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    vpextrd $1, %xmm0, %eax
 ; X86-AVX1-NEXT:    vpextrd $1, %xmm1, %edi
+; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %edi
 ; X86-AVX1-NEXT:    movl %edx, %edi
-; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    vmovd %xmm0, %eax
 ; X86-AVX1-NEXT:    vmovd %xmm1, %ecx
+; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %ecx
 ; X86-AVX1-NEXT:    vmovd %edx, %xmm0
 ; X86-AVX1-NEXT:    vpinsrd $1, %edi, %xmm0, %xmm0
 ; X86-AVX1-NEXT:    vpinsrd $2, %esi, %xmm0, %xmm0
 ; X86-AVX1-NEXT:    vpinsrd $3, %ebx, %xmm0, %xmm0
 ; X86-AVX1-NEXT:    vmovd %ebp, %xmm1
 ; X86-AVX1-NEXT:    vpinsrd $1, (%esp), %xmm1, %xmm1 # 4-byte Folded Reload
 ; X86-AVX1-NEXT:    vpinsrd $2, {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 4-byte Folded Reload

llvm/trunk/test/CodeGen/X86/shrink_vmul.ll

 ; X86-AVX1-NEXT:    divl %ecx
 ; X86-AVX1-NEXT:    movl %edx, (%esp) # 4-byte Spill
 ; X86-AVX1-NEXT:    vmovd %xmm2, %eax
 ; X86-AVX1-NEXT:    vmovd %xmm3, %ecx
 ; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %ecx
 ; X86-AVX1-NEXT:    movl %edx, %ebp
 ; X86-AVX1-NEXT:    vpextrd $3, %xmm0, %eax
-; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    vpextrd $3, %xmm1, %ecx
+; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %ecx
 ; X86-AVX1-NEXT:    movl %edx, %ebx
-; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    vpextrd $2, %xmm0, %eax
 ; X86-AVX1-NEXT:    vpextrd $2, %xmm1, %esi
+; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %esi
 ; X86-AVX1-NEXT:    movl %edx, %esi
-; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    vpextrd $1, %xmm0, %eax
 ; X86-AVX1-NEXT:    vpextrd $1, %xmm1, %edi
+; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %edi
 ; X86-AVX1-NEXT:    movl %edx, %edi
-; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    vmovd %xmm0, %eax
 ; X86-AVX1-NEXT:    vmovd %xmm1, %ecx
+; X86-AVX1-NEXT:    xorl %edx, %edx
 ; X86-AVX1-NEXT:    divl %ecx
 ; X86-AVX1-NEXT:    vmovd %edx, %xmm0
 ; X86-AVX1-NEXT:    vpinsrd $1, %edi, %xmm0, %xmm0
 ; X86-AVX1-NEXT:    vpinsrd $2, %esi, %xmm0, %xmm0
 ; X86-AVX1-NEXT:    vpinsrd $3, %ebx, %xmm0, %xmm0
 ; X86-AVX1-NEXT:    vmovd %ebp, %xmm1
 ; X86-AVX1-NEXT:    vpinsrd $1, (%esp), %xmm1, %xmm1 # 4-byte Folded Reload
 ; X86-AVX1-NEXT:    vpinsrd $2, {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 4-byte Folded Reload

llvm/trunk/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll

 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
 ; X64-NOPIC-MCM-NEXT:    callq f
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr0:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr0(%rip), %rdx
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rdx
 ; X64-NOPIC-MCM-NEXT:    cmpq %rdx, %rcx
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r14, %rax
 ; X64-NOPIC-MCM-NEXT:    movl (%rbx), %ebp
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
 ; X64-NOPIC-MCM-NEXT:    callq f
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr1:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rcx
 ; X64-NOPIC-MCM-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rcx
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr1(%rip), %rdx
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rdx
 ; X64-NOPIC-MCM-NEXT:    cmpq %rdx, %rax
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r14, %rcx
 ; X64-NOPIC-MCM-NEXT:    addl (%rbx), %ebp
 ; X64-NOPIC-MCM-NEXT:    orl %ecx, %ebp
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rcx
 ; X64-NOPIC-MCM-NEXT:    movl %ebp, %eax
 ; X64-NOPIC-MCM-NEXT:    orq %rcx, %rsp
 ; X64-NOPIC-MCM-NEXT:    popq %rbx

 ; X64-PIC-NEXT:    sarq $63, %rax
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    orq %rax, %rsp
 ; X64-PIC-NEXT:    callq f@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr0:
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr0(%rip), %rdx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rdx
 ; X64-PIC-NEXT:    cmpq %rdx, %rcx
 ; X64-PIC-NEXT:    cmovneq %r14, %rax
 ; X64-PIC-NEXT:    movl (%rbx), %ebp
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    orq %rax, %rsp
 ; X64-PIC-NEXT:    callq f@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr1:
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; X64-PIC-NEXT:    sarq $63, %rcx
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr1(%rip), %rdx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rdx
 ; X64-PIC-NEXT:    cmpq %rdx, %rax
 ; X64-PIC-NEXT:    cmovneq %r14, %rcx
 ; X64-PIC-NEXT:    addl (%rbx), %ebp
 ; X64-PIC-NEXT:    orl %ecx, %ebp
 ; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl %ebp, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    popq %rbx

 ; X64-NOPIC-MCM-NEXT:    pushq %rbx
 ; X64-NOPIC-MCM-NEXT:    pushq %rax
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %rdi, %rbx
 ; X64-NOPIC-MCM-NEXT:    movq $-1, %r14
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr2(%rip), %rbp
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rbp
 ; X64-NOPIC-MCM-NEXT:    callq f
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr2:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr2(%rip), %rcx
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-NOPIC-MCM-NEXT:    cmpq %rcx, %rbp
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r14, %rax
 ; X64-NOPIC-MCM-NEXT:    movl (%rbx), %ebp
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr3(%rip), %r15
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %r15
 ; X64-NOPIC-MCM-NEXT:    callq f
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr3:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rcx
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rcx
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr3(%rip), %rax
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rax
 ; X64-NOPIC-MCM-NEXT:    cmpq %rax, %r15
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r14, %rcx
 ; X64-NOPIC-MCM-NEXT:    addl (%rbx), %ebp
 ; X64-NOPIC-MCM-NEXT:    orl %ecx, %ebp
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rcx
 ; X64-NOPIC-MCM-NEXT:    movl %ebp, %eax
 ; X64-NOPIC-MCM-NEXT:    orq %rcx, %rsp
 ; X64-NOPIC-MCM-NEXT:    addq $8, %rsp

 ; X64-PIC-NEXT:    pushq %rbx
 ; X64-PIC-NEXT:    pushq %rax
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    movq %rdi, %rbx
 ; X64-PIC-NEXT:    movq $-1, %r14
 ; X64-PIC-NEXT:    sarq $63, %rax
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr2(%rip), %rbp
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rbp
 ; X64-PIC-NEXT:    callq f@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr2:
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr2(%rip), %rcx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-PIC-NEXT:    cmpq %rcx, %rbp
 ; X64-PIC-NEXT:    cmovneq %r14, %rax
 ; X64-PIC-NEXT:    movl (%rbx), %ebp
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr3(%rip), %r15
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %r15
 ; X64-PIC-NEXT:    callq f@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr3:
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    sarq $63, %rcx
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr3(%rip), %rax
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rax
 ; X64-PIC-NEXT:    cmpq %rax, %r15
 ; X64-PIC-NEXT:    cmovneq %r14, %rcx
 ; X64-PIC-NEXT:    addl (%rbx), %ebp
 ; X64-PIC-NEXT:    orl %ecx, %ebp
 ; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl %ebp, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    addq $8, %rsp

 ; X64-NOPIC-NEXT:    movq $.Lslh_ret_addr4, %rbp
 ; X64-NOPIC-NEXT:    callq setjmp
 ; X64-NOPIC-NEXT:  .Lslh_ret_addr4:
 ; X64-NOPIC-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-NEXT:    sarq $63, %rax
 ; X64-NOPIC-NEXT:    cmpq $.Lslh_ret_addr4, %rbp
 ; X64-NOPIC-NEXT:    cmovneq %r15, %rax
 ; X64-NOPIC-NEXT:    movl (%rbx), %ebp
-; X64-NOPIC-NEXT:    movl $42, %esi
 ; X64-NOPIC-NEXT:    shlq $47, %rax
 ; X64-NOPIC-NEXT:    movq %r14, %rdi
+; X64-NOPIC-NEXT:    movl $42, %esi
 ; X64-NOPIC-NEXT:    orq %rax, %rsp
 ; X64-NOPIC-NEXT:    movq $.Lslh_ret_addr5, %r12
 ; X64-NOPIC-NEXT:    callq sigsetjmp
 ; X64-NOPIC-NEXT:  .Lslh_ret_addr5:
 ; X64-NOPIC-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-NEXT:    sarq $63, %rax
 ; X64-NOPIC-NEXT:    cmpq $.Lslh_ret_addr5, %r12
 ; X64-NOPIC-NEXT:    cmovneq %r15, %rax
 ; X64-NOPIC-NEXT:    addl (%rbx), %ebp
-; X64-NOPIC-NEXT:    movl $42, %edx
 ; X64-NOPIC-NEXT:    shlq $47, %rax
 ; X64-NOPIC-NEXT:    movq %r14, %rdi
 ; X64-NOPIC-NEXT:    movq %r14, %rsi
+; X64-NOPIC-NEXT:    movl $42, %edx
 ; X64-NOPIC-NEXT:    orq %rax, %rsp
 ; X64-NOPIC-NEXT:    movq $.Lslh_ret_addr6, %r14
 ; X64-NOPIC-NEXT:    callq __sigsetjmp
 ; X64-NOPIC-NEXT:  .Lslh_ret_addr6:
 ; X64-NOPIC-NEXT:    movq %rsp, %rcx
 ; X64-NOPIC-NEXT:    sarq $63, %rcx
 ; X64-NOPIC-NEXT:    cmpq $.Lslh_ret_addr6, %r14
 ; X64-NOPIC-NEXT:    cmovneq %r15, %rcx

 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %rdi, %rbx
 ; X64-NOPIC-MCM-NEXT:    movq $-1, %r15
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %r14
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %r14, %rdi
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr4(%rip), %rbp
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rbp
 ; X64-NOPIC-MCM-NEXT:    callq setjmp
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr4:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr4(%rip), %rcx
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-NOPIC-MCM-NEXT:    cmpq %rcx, %rbp
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r15, %rax
 ; X64-NOPIC-MCM-NEXT:    movl (%rbx), %ebp
-; X64-NOPIC-MCM-NEXT:    movl $42, %esi
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %r14, %rdi
+; X64-NOPIC-MCM-NEXT:    movl $42, %esi
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr5(%rip), %r12
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %r12
 ; X64-NOPIC-MCM-NEXT:    callq sigsetjmp
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr5:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rax
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rax
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr5(%rip), %rcx
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-NOPIC-MCM-NEXT:    cmpq %rcx, %r12
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r15, %rax
 ; X64-NOPIC-MCM-NEXT:    addl (%rbx), %ebp
-; X64-NOPIC-MCM-NEXT:    movl $42, %edx
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rax
 ; X64-NOPIC-MCM-NEXT:    movq %r14, %rdi
 ; X64-NOPIC-MCM-NEXT:    movq %r14, %rsi
+; X64-NOPIC-MCM-NEXT:    movl $42, %edx
 ; X64-NOPIC-MCM-NEXT:    orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr6(%rip), %r14
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %r14
 ; X64-NOPIC-MCM-NEXT:    callq __sigsetjmp
 ; X64-NOPIC-MCM-NEXT:  .Lslh_ret_addr6:
 ; X64-NOPIC-MCM-NEXT:    movq %rsp, %rcx
 ; X64-NOPIC-MCM-NEXT:    sarq $63, %rcx
-; X64-NOPIC-MCM-NEXT:    leaq .Lslh_ret_addr6(%rip), %rax
+; X64-NOPIC-MCM-NEXT:    leaq {{.*}}(%rip), %rax
 ; X64-NOPIC-MCM-NEXT:    cmpq %rax, %r14
 ; X64-NOPIC-MCM-NEXT:    cmovneq %r15, %rcx
 ; X64-NOPIC-MCM-NEXT:    addl (%rbx), %ebp
 ; X64-NOPIC-MCM-NEXT:    orl %ecx, %ebp
 ; X64-NOPIC-MCM-NEXT:    shlq $47, %rcx
 ; X64-NOPIC-MCM-NEXT:    movl %ebp, %eax
 ; X64-NOPIC-MCM-NEXT:    orq %rcx, %rsp
 ; X64-NOPIC-MCM-NEXT:    addq $16, %rsp

 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    movq %rdi, %rbx
 ; X64-PIC-NEXT:    movq $-1, %r15
 ; X64-PIC-NEXT:    sarq $63, %rax
 ; X64-PIC-NEXT:    movq %rsp, %r14
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    movq %r14, %rdi
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr4(%rip), %rbp
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rbp
 ; X64-PIC-NEXT:    callq setjmp@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr4:
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr4(%rip), %rcx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-PIC-NEXT:    cmpq %rcx, %rbp
 ; X64-PIC-NEXT:    cmovneq %r15, %rax
 ; X64-PIC-NEXT:    movl (%rbx), %ebp
-; X64-PIC-NEXT:    movl $42, %esi
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    movq %r14, %rdi
+; X64-PIC-NEXT:    movl $42, %esi
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr5(%rip), %r12
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %r12
 ; X64-PIC-NEXT:    callq sigsetjmp@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr5:
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr5(%rip), %rcx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-PIC-NEXT:    cmpq %rcx, %r12
 ; X64-PIC-NEXT:    cmovneq %r15, %rax
 ; X64-PIC-NEXT:    addl (%rbx), %ebp
-; X64-PIC-NEXT:    movl $42, %edx
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    movq %r14, %rdi
 ; X64-PIC-NEXT:    movq %r14, %rsi
+; X64-PIC-NEXT:    movl $42, %edx
 ; X64-PIC-NEXT:    orq %rax, %rsp
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr6(%rip), %r14
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %r14
 ; X64-PIC-NEXT:    callq __sigsetjmp@PLT
 ; X64-PIC-NEXT:  .Lslh_ret_addr6:
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    sarq $63, %rcx
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr6(%rip), %rax
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rax
 ; X64-PIC-NEXT:    cmpq %rax, %r14
 ; X64-PIC-NEXT:    cmovneq %r15, %rcx
 ; X64-PIC-NEXT:    addl (%rbx), %ebp
 ; X64-PIC-NEXT:    orl %ecx, %ebp
 ; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl %ebp, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    addq $16, %rsp

llvm/trunk/test/CodeGen/X86/speculative-load-hardening-indirect.ll

 ; X64-PIC-NEXT:    orq %rax, %rcx
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    orq %rax, %rsp
 ; X64-PIC-NEXT:    callq *%rcx
 ; X64-PIC-NEXT:  .Lslh_ret_addr0:
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    movq -{{[0-9]+}}(%rsp), %rdx
 ; X64-PIC-NEXT:    sarq $63, %rcx
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr0(%rip), %rsi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rbx, %rcx
 ; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    popq %rbx
 ; X64-PIC-NEXT:    retq
 ;
 ; X64-RETPOLINE-LABEL: test_indirect_call:

 
 define i32 @test_indirect_call_global() nounwind {
 ; X64-LABEL: test_indirect_call_global:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    pushq %rbx
 ; X64-NEXT:    movq %rsp, %rax
 ; X64-NEXT:    movq $-1, %rbx
 ; X64-NEXT:    sarq $63, %rax
-; X64-NEXT:    movq global_fnptr(%rip), %rcx
+; X64-NEXT:    movq {{.*}}(%rip), %rcx
 ; X64-NEXT:    orq %rax, %rcx
 ; X64-NEXT:    shlq $47, %rax
 ; X64-NEXT:    orq %rax, %rsp
 ; X64-NEXT:    callq *%rcx
 ; X64-NEXT:  .Lslh_ret_addr1:
 ; X64-NEXT:    movq %rsp, %rcx
 ; X64-NEXT:    movq -{{[0-9]+}}(%rsp), %rdx
 ; X64-NEXT:    sarq $63, %rcx
 ; X64-NEXT:    cmpq $.Lslh_ret_addr1, %rdx
 ; X64-NEXT:    cmovneq %rbx, %rcx
 ; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    popq %rbx
 ; X64-NEXT:    retq
 ;
 ; X64-PIC-LABEL: test_indirect_call_global:
 ; X64-PIC:       # %bb.0: # %entry
 ; X64-PIC-NEXT:    pushq %rbx
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    movq $-1, %rbx
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    movq global_fnptr@GOTPCREL(%rip), %rcx
+; X64-PIC-NEXT:    movq global_fnptr@{{.*}}(%rip), %rcx
 ; X64-PIC-NEXT:    movq (%rcx), %rcx
 ; X64-PIC-NEXT:    orq %rax, %rcx
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    orq %rax, %rsp
 ; X64-PIC-NEXT:    callq *%rcx
 ; X64-PIC-NEXT:  .Lslh_ret_addr1:
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    movq -{{[0-9]+}}(%rsp), %rdx
 ; X64-PIC-NEXT:    sarq $63, %rcx
-; X64-PIC-NEXT:    leaq .Lslh_ret_addr1(%rip), %rsi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rbx, %rcx
 ; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    popq %rbx
 ; X64-PIC-NEXT:    retq
 ;
 ; X64-RETPOLINE-LABEL: test_indirect_call_global:
 ; X64-RETPOLINE:       # %bb.0: # %entry
 ; X64-RETPOLINE-NEXT:    pushq %rbx
 ; X64-RETPOLINE-NEXT:    movq %rsp, %rax
 ; X64-RETPOLINE-NEXT:    movq $-1, %rbx
 ; X64-RETPOLINE-NEXT:    sarq $63, %rax
-; X64-RETPOLINE-NEXT:    movq global_fnptr(%rip), %r11
+; X64-RETPOLINE-NEXT:    movq {{.*}}(%rip), %r11
 ; X64-RETPOLINE-NEXT:    shlq $47, %rax
 ; X64-RETPOLINE-NEXT:    orq %rax, %rsp
 ; X64-RETPOLINE-NEXT:    callq __llvm_retpoline_r11
 ; X64-RETPOLINE-NEXT:  .Lslh_ret_addr1:
 ; X64-RETPOLINE-NEXT:    movq %rsp, %rcx
 ; X64-RETPOLINE-NEXT:    movq -{{[0-9]+}}(%rsp), %rdx
 ; X64-RETPOLINE-NEXT:    sarq $63, %rcx
 ; X64-RETPOLINE-NEXT:    cmpq $.Lslh_ret_addr1, %rdx

 }
 
 define i32 @test_indirect_tail_call_global() nounwind {
 ; X64-LABEL: test_indirect_tail_call_global:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    movq %rsp, %rax
 ; X64-NEXT:    movq $-1, %rcx
 ; X64-NEXT:    sarq $63, %rax
-; X64-NEXT:    movq global_fnptr(%rip), %rcx
+; X64-NEXT:    movq {{.*}}(%rip), %rcx
 ; X64-NEXT:    orq %rax, %rcx
 ; X64-NEXT:    shlq $47, %rax
 ; X64-NEXT:    orq %rax, %rsp
 ; X64-NEXT:    jmpq *%rcx # TAILCALL
 ;
 ; X64-PIC-LABEL: test_indirect_tail_call_global:
 ; X64-PIC:       # %bb.0: # %entry
 ; X64-PIC-NEXT:    movq %rsp, %rax
 ; X64-PIC-NEXT:    movq $-1, %rcx
 ; X64-PIC-NEXT:    sarq $63, %rax
-; X64-PIC-NEXT:    movq global_fnptr@GOTPCREL(%rip), %rcx
+; X64-PIC-NEXT:    movq global_fnptr@{{.*}}(%rip), %rcx
 ; X64-PIC-NEXT:    movq (%rcx), %rcx
 ; X64-PIC-NEXT:    orq %rax, %rcx
 ; X64-PIC-NEXT:    shlq $47, %rax
 ; X64-PIC-NEXT:    orq %rax, %rsp
 ; X64-PIC-NEXT:    jmpq *%rcx # TAILCALL
 ;
 ; X64-RETPOLINE-LABEL: test_indirect_tail_call_global:
 ; X64-RETPOLINE:       # %bb.0: # %entry
 ; X64-RETPOLINE-NEXT:    movq %rsp, %rax
 ; X64-RETPOLINE-NEXT:    movq $-1, %rcx
 ; X64-RETPOLINE-NEXT:    sarq $63, %rax
-; X64-RETPOLINE-NEXT:    movq global_fnptr(%rip), %r11
+; X64-RETPOLINE-NEXT:    movq {{.*}}(%rip), %r11
 ; X64-RETPOLINE-NEXT:    shlq $47, %rax
 ; X64-RETPOLINE-NEXT:    orq %rax, %rsp
 ; X64-RETPOLINE-NEXT:    jmp __llvm_retpoline_r11 # TAILCALL
 entry:
   %fp = load i32 ()*, i32 ()** @global_fnptr
   %v = tail call i32 %fp()
   ret i32 %v
 }
 
 define i32 @test_indirectbr(i8** %ptr) nounwind {
 ; X64-LABEL: test_indirectbr:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    movq %rsp, %rcx
 ; X64-NEXT:    movq $-1, %rax
 ; X64-NEXT:    sarq $63, %rcx
 ; X64-NEXT:    movq (%rdi), %rdx
 ; X64-NEXT:    orq %rcx, %rdx
 ; X64-NEXT:    jmpq *%rdx
 ; X64-NEXT:  .LBB4_1: # %bb0
 ; X64-NEXT:    cmpq $.LBB4_1, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $2, %eax
-; X64-NEXT:    jmp .LBB4_2
-; X64-NEXT:  .LBB4_4: # %bb2
-; X64-NEXT:    cmpq $.LBB4_4, %rdx
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
+; X64-NEXT:  .LBB4_3: # %bb2
+; X64-NEXT:    cmpq $.LBB4_3, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $13, %eax
-; X64-NEXT:    jmp .LBB4_2
-; X64-NEXT:  .LBB4_5: # %bb3
-; X64-NEXT:    cmpq $.LBB4_5, %rdx
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
+; X64-NEXT:  .LBB4_4: # %bb3
+; X64-NEXT:    cmpq $.LBB4_4, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $42, %eax
-; X64-NEXT:    jmp .LBB4_2
-; X64-NEXT:  .LBB4_3: # %bb1
-; X64-NEXT:    cmpq $.LBB4_3, %rdx
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
+; X64-NEXT:  .LBB4_2: # %bb1
+; X64-NEXT:    cmpq $.LBB4_2, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
-; X64-NEXT:    movl $7, %eax
-; X64-NEXT:  .LBB4_2: # %bb0
 ; X64-NEXT:    shlq $47, %rcx
+; X64-NEXT:    movl $7, %eax
 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    retq
 ;
 ; X64-PIC-LABEL: test_indirectbr:
 ; X64-PIC:       # %bb.0: # %entry
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    movq $-1, %rax
 ; X64-PIC-NEXT:    sarq $63, %rcx
 ; X64-PIC-NEXT:    movq (%rdi), %rdx
 ; X64-PIC-NEXT:    orq %rcx, %rdx
 ; X64-PIC-NEXT:    jmpq *%rdx
 ; X64-PIC-NEXT:  .LBB4_1: # %bb0
-; X64-PIC-NEXT:    leaq .LBB4_1(%rip), %rsi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $2, %eax
-; X64-PIC-NEXT:    jmp .LBB4_2
-; X64-PIC-NEXT:  .LBB4_4: # %bb2
-; X64-PIC-NEXT:    leaq .LBB4_4(%rip), %rsi
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
+; X64-PIC-NEXT:  .LBB4_3: # %bb2
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $13, %eax
-; X64-PIC-NEXT:    jmp .LBB4_2
-; X64-PIC-NEXT:  .LBB4_5: # %bb3
-; X64-PIC-NEXT:    leaq .LBB4_5(%rip), %rsi
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
+; X64-PIC-NEXT:  .LBB4_4: # %bb3
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $42, %eax
-; X64-PIC-NEXT:    jmp .LBB4_2
-; X64-PIC-NEXT:  .LBB4_3: # %bb1
-; X64-PIC-NEXT:    leaq .LBB4_3(%rip), %rsi
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
+; X64-PIC-NEXT:  .LBB4_2: # %bb1
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
-; X64-PIC-NEXT:    movl $7, %eax
-; X64-PIC-NEXT:  .LBB4_2: # %bb0
 ; X64-PIC-NEXT:    shlq $47, %rcx
+; X64-PIC-NEXT:    movl $7, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    retq
 ;
 ; X64-RETPOLINE-LABEL: test_indirectbr:
 ; X64-RETPOLINE:       # %bb.0: # %entry
 entry:
   %a = load i8*, i8** %ptr
   indirectbr i8* %a, [ label %bb0, label %bb1, label %bb2, label %bb3 ]

 ; X64-NEXT:    movslq %edi, %rdx
 ; X64-NEXT:    movq global_blockaddrs(,%rdx,8), %rdx
 ; X64-NEXT:    orq %rcx, %rdx
 ; X64-NEXT:    jmpq *%rdx
 ; X64-NEXT:  .Ltmp0: # Block address taken
 ; X64-NEXT:  .LBB5_1: # %bb0
 ; X64-NEXT:    cmpq $.LBB5_1, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $2, %eax
-; X64-NEXT:    jmp .LBB5_2
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
 ; X64-NEXT:  .Ltmp1: # Block address taken
-; X64-NEXT:  .LBB5_4: # %bb2
-; X64-NEXT:    cmpq $.LBB5_4, %rdx
+; X64-NEXT:  .LBB5_3: # %bb2
+; X64-NEXT:    cmpq $.LBB5_3, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $13, %eax
-; X64-NEXT:    jmp .LBB5_2
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
 ; X64-NEXT:  .Ltmp2: # Block address taken
-; X64-NEXT:  .LBB5_5: # %bb3
-; X64-NEXT:    cmpq $.LBB5_5, %rdx
+; X64-NEXT:  .LBB5_4: # %bb3
+; X64-NEXT:    cmpq $.LBB5_4, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $42, %eax
-; X64-NEXT:    jmp .LBB5_2
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
 ; X64-NEXT:  .Ltmp3: # Block address taken
-; X64-NEXT:  .LBB5_3: # %bb1
-; X64-NEXT:    cmpq $.LBB5_3, %rdx
+; X64-NEXT:  .LBB5_2: # %bb1
+; X64-NEXT:    cmpq $.LBB5_2, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
-; X64-NEXT:    movl $7, %eax
-; X64-NEXT:  .LBB5_2: # %bb0
 ; X64-NEXT:    shlq $47, %rcx
+; X64-NEXT:    movl $7, %eax
 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    retq
 ;
 ; X64-PIC-LABEL: test_indirectbr_global:
 ; X64-PIC:       # %bb.0: # %entry
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    movq $-1, %rax
 ; X64-PIC-NEXT:    sarq $63, %rcx
 ; X64-PIC-NEXT:    movslq %edi, %rdx
-; X64-PIC-NEXT:    movq global_blockaddrs@GOTPCREL(%rip), %rsi
+; X64-PIC-NEXT:    movq global_blockaddrs@{{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    movq (%rsi,%rdx,8), %rdx
 ; X64-PIC-NEXT:    orq %rcx, %rdx
 ; X64-PIC-NEXT:    jmpq *%rdx
 ; X64-PIC-NEXT:  .Ltmp0: # Block address taken
 ; X64-PIC-NEXT:  .LBB5_1: # %bb0
-; X64-PIC-NEXT:    leaq .LBB5_1(%rip), %rsi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $2, %eax
-; X64-PIC-NEXT:    jmp .LBB5_2
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
 ; X64-PIC-NEXT:  .Ltmp1: # Block address taken
-; X64-PIC-NEXT:  .LBB5_4: # %bb2
-; X64-PIC-NEXT:    leaq .LBB5_4(%rip), %rsi
+; X64-PIC-NEXT:  .LBB5_3: # %bb2
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $13, %eax
-; X64-PIC-NEXT:    jmp .LBB5_2
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
 ; X64-PIC-NEXT:  .Ltmp2: # Block address taken
-; X64-PIC-NEXT:  .LBB5_5: # %bb3
-; X64-PIC-NEXT:    leaq .LBB5_5(%rip), %rsi
+; X64-PIC-NEXT:  .LBB5_4: # %bb3
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $42, %eax
-; X64-PIC-NEXT:    jmp .LBB5_2
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
 ; X64-PIC-NEXT:  .Ltmp3: # Block address taken
-; X64-PIC-NEXT:  .LBB5_3: # %bb1
-; X64-PIC-NEXT:    leaq .LBB5_3(%rip), %rsi
+; X64-PIC-NEXT:  .LBB5_2: # %bb1
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
-; X64-PIC-NEXT:    movl $7, %eax
-; X64-PIC-NEXT:  .LBB5_2: # %bb0
 ; X64-PIC-NEXT:    shlq $47, %rcx
+; X64-PIC-NEXT:    movl $7, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    retq
 ;
 ; X64-RETPOLINE-LABEL: test_indirectbr_global:
 ; X64-RETPOLINE:       # %bb.0: # %entry
 ; X64-RETPOLINE-NEXT:    movq %rsp, %rcx
 ; X64-RETPOLINE-NEXT:    movq $-1, %rax
 ; X64-RETPOLINE-NEXT:    sarq $63, %rcx
 ; X64-RETPOLINE-NEXT:    movslq %edi, %rdx
 ; X64-RETPOLINE-NEXT:    movq global_blockaddrs(,%rdx,8), %rdx
 ; X64-RETPOLINE-NEXT:    orq %rcx, %rdx
 ; X64-RETPOLINE-NEXT:    cmpq $2, %rdx
-; X64-RETPOLINE-NEXT:    je .LBB6_5
+; X64-RETPOLINE-NEXT:    je .LBB6_4
 ; X64-RETPOLINE-NEXT:  # %bb.1: # %entry
 ; X64-RETPOLINE-NEXT:    cmoveq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    cmpq $3, %rdx
-; X64-RETPOLINE-NEXT:    je .LBB6_6
+; X64-RETPOLINE-NEXT:    je .LBB6_5
 ; X64-RETPOLINE-NEXT:  # %bb.2: # %entry
 ; X64-RETPOLINE-NEXT:    cmoveq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    cmpq $4, %rdx
 ; X64-RETPOLINE-NEXT:    jne .LBB6_3
 ; X64-RETPOLINE-NEXT:  .Ltmp0: # Block address taken
-; X64-RETPOLINE-NEXT:  # %bb.7: # %bb3
+; X64-RETPOLINE-NEXT:  # %bb.6: # %bb3
 ; X64-RETPOLINE-NEXT:    cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT:    shlq $47, %rcx
 ; X64-RETPOLINE-NEXT:    movl $42, %eax
-; X64-RETPOLINE-NEXT:    jmp .LBB6_4
+; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
+; X64-RETPOLINE-NEXT:    retq
 ; X64-RETPOLINE-NEXT:  .Ltmp1: # Block address taken
-; X64-RETPOLINE-NEXT:  .LBB6_5: # %bb1
+; X64-RETPOLINE-NEXT:  .LBB6_4: # %bb1
 ; X64-RETPOLINE-NEXT:    cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT:    shlq $47, %rcx
 ; X64-RETPOLINE-NEXT:    movl $7, %eax
-; X64-RETPOLINE-NEXT:    jmp .LBB6_4
+; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
+; X64-RETPOLINE-NEXT:    retq
 ; X64-RETPOLINE-NEXT:  .Ltmp2: # Block address taken
-; X64-RETPOLINE-NEXT:  .LBB6_6: # %bb2
+; X64-RETPOLINE-NEXT:  .LBB6_5: # %bb2
 ; X64-RETPOLINE-NEXT:    cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT:    shlq $47, %rcx
 ; X64-RETPOLINE-NEXT:    movl $13, %eax
-; X64-RETPOLINE-NEXT:    jmp .LBB6_4
+; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
+; X64-RETPOLINE-NEXT:    retq
 ; X64-RETPOLINE-NEXT:  .Ltmp3: # Block address taken
 ; X64-RETPOLINE-NEXT:  .LBB6_3: # %bb0
 ; X64-RETPOLINE-NEXT:    cmoveq %rax, %rcx
-; X64-RETPOLINE-NEXT:    movl $2, %eax
-; X64-RETPOLINE-NEXT:  .LBB6_4: # %bb0
 ; X64-RETPOLINE-NEXT:    shlq $47, %rcx
+; X64-RETPOLINE-NEXT:    movl $2, %eax
 ; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
 ; X64-RETPOLINE-NEXT:    retq
 entry:
   %ptr = getelementptr [4 x i8*], [4 x i8*]* @global_blockaddrs, i32 0, i32 %idx
   %a = load i8*, i8** %ptr
   indirectbr i8* %a, [ label %bb0, label %bb1, label %bb2, label %bb3 ]
 
 bb0:

 ; X64-NEXT:    cmpl $3, %edi
 ; X64-NEXT:    ja .LBB6_2
 ; X64-NEXT:  # %bb.1: # %entry
 ; X64-NEXT:    cmovaq %rax, %rcx
 ; X64-NEXT:    movl %edi, %edx
 ; X64-NEXT:    movq .LJTI6_0(,%rdx,8), %rdx
 ; X64-NEXT:    orq %rcx, %rdx
 ; X64-NEXT:    jmpq *%rdx
-; X64-NEXT:  .LBB6_4: # %bb1
-; X64-NEXT:    cmpq $.LBB6_4, %rdx
+; X64-NEXT:  .LBB6_3: # %bb1
+; X64-NEXT:    cmpq $.LBB6_3, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $7, %eax
-; X64-NEXT:    jmp .LBB6_3
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
 ; X64-NEXT:  .LBB6_2: # %bb0
 ; X64-NEXT:    cmovbeq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $2, %eax
-; X64-NEXT:    jmp .LBB6_3
-; X64-NEXT:  .LBB6_5: # %bb2
-; X64-NEXT:    cmpq $.LBB6_5, %rdx
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
+; X64-NEXT:  .LBB6_4: # %bb2
+; X64-NEXT:    cmpq $.LBB6_4, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $13, %eax
-; X64-NEXT:    jmp .LBB6_3
-; X64-NEXT:  .LBB6_6: # %bb3
-; X64-NEXT:    cmpq $.LBB6_6, %rdx
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
+; X64-NEXT:  .LBB6_5: # %bb3
+; X64-NEXT:    cmpq $.LBB6_5, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $42, %eax
-; X64-NEXT:    jmp .LBB6_3
-; X64-NEXT:  .LBB6_7: # %bb5
-; X64-NEXT:    cmpq $.LBB6_7, %rdx
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
+; X64-NEXT:  .LBB6_6: # %bb5
+; X64-NEXT:    cmpq $.LBB6_6, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
-; X64-NEXT:    movl $11, %eax
-; X64-NEXT:  .LBB6_3: # %bb0
 ; X64-NEXT:    shlq $47, %rcx
+; X64-NEXT:    movl $11, %eax
 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    retq
 ;
 ; X64-PIC-LABEL: test_switch_jumptable:
 ; X64-PIC:       # %bb.0: # %entry
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    movq $-1, %rax
 ; X64-PIC-NEXT:    sarq $63, %rcx
 ; X64-PIC-NEXT:    cmpl $3, %edi
 ; X64-PIC-NEXT:    ja .LBB6_2
 ; X64-PIC-NEXT:  # %bb.1: # %entry
 ; X64-PIC-NEXT:    cmovaq %rax, %rcx
 ; X64-PIC-NEXT:    movl %edi, %edx
-; X64-PIC-NEXT:    leaq .LJTI6_0(%rip), %rsi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    movslq (%rsi,%rdx,4), %rdx
 ; X64-PIC-NEXT:    addq %rsi, %rdx
 ; X64-PIC-NEXT:    orq %rcx, %rdx
 ; X64-PIC-NEXT:    jmpq *%rdx
-; X64-PIC-NEXT:  .LBB6_4: # %bb1
-; X64-PIC-NEXT:    leaq .LBB6_4(%rip), %rsi
+; X64-PIC-NEXT:  .LBB6_3: # %bb1
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $7, %eax
-; X64-PIC-NEXT:    jmp .LBB6_3
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
 ; X64-PIC-NEXT:  .LBB6_2: # %bb0
 ; X64-PIC-NEXT:    cmovbeq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $2, %eax
-; X64-PIC-NEXT:    jmp .LBB6_3
-; X64-PIC-NEXT:  .LBB6_5: # %bb2
-; X64-PIC-NEXT:    leaq .LBB6_5(%rip), %rsi
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
+; X64-PIC-NEXT:  .LBB6_4: # %bb2
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $13, %eax
-; X64-PIC-NEXT:    jmp .LBB6_3
-; X64-PIC-NEXT:  .LBB6_6: # %bb3
-; X64-PIC-NEXT:    leaq .LBB6_6(%rip), %rsi
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
+; X64-PIC-NEXT:  .LBB6_5: # %bb3
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $42, %eax
-; X64-PIC-NEXT:    jmp .LBB6_3
-; X64-PIC-NEXT:  .LBB6_7: # %bb5
-; X64-PIC-NEXT:    leaq .LBB6_7(%rip), %rsi
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
+; X64-PIC-NEXT:  .LBB6_6: # %bb5
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
-; X64-PIC-NEXT:    movl $11, %eax
-; X64-PIC-NEXT:  .LBB6_3: # %bb0
 ; X64-PIC-NEXT:    shlq $47, %rcx
+; X64-PIC-NEXT:    movl $11, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    retq
 ;
 ; X64-RETPOLINE-LABEL: test_switch_jumptable:
 ; X64-RETPOLINE:       # %bb.0: # %entry
 ; X64-RETPOLINE-NEXT:    movq %rsp, %rcx
 ; X64-RETPOLINE-NEXT:    movq $-1, %rax
 ; X64-RETPOLINE-NEXT:    sarq $63, %rcx
 ; X64-RETPOLINE-NEXT:    cmpl $1, %edi
 ; X64-RETPOLINE-NEXT:    jg .LBB7_4
 ; X64-RETPOLINE-NEXT:  # %bb.1: # %entry
 ; X64-RETPOLINE-NEXT:    cmovgq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    testl %edi, %edi
-; X64-RETPOLINE-NEXT:    je .LBB7_8
+; X64-RETPOLINE-NEXT:    je .LBB7_7
 ; X64-RETPOLINE-NEXT:  # %bb.2: # %entry
 ; X64-RETPOLINE-NEXT:    cmoveq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    cmpl $1, %edi
 ; X64-RETPOLINE-NEXT:    jne .LBB7_6
 ; X64-RETPOLINE-NEXT:  # %bb.3: # %bb2
 ; X64-RETPOLINE-NEXT:    cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT:    shlq $47, %rcx
 ; X64-RETPOLINE-NEXT:    movl $13, %eax
-; X64-RETPOLINE-NEXT:    jmp .LBB7_7
+; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
+; X64-RETPOLINE-NEXT:    retq
 ; X64-RETPOLINE-NEXT:  .LBB7_4: # %entry
 ; X64-RETPOLINE-NEXT:    cmovleq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    cmpl $2, %edi
-; X64-RETPOLINE-NEXT:    je .LBB7_9
+; X64-RETPOLINE-NEXT:    je .LBB7_8
 ; X64-RETPOLINE-NEXT:  # %bb.5: # %entry
 ; X64-RETPOLINE-NEXT:    cmoveq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    cmpl $3, %edi
 ; X64-RETPOLINE-NEXT:    jne .LBB7_6
-; X64-RETPOLINE-NEXT:  # %bb.10: # %bb5
+; X64-RETPOLINE-NEXT:  # %bb.9: # %bb5
 ; X64-RETPOLINE-NEXT:    cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT:    shlq $47, %rcx
 ; X64-RETPOLINE-NEXT:    movl $11, %eax
-; X64-RETPOLINE-NEXT:    jmp .LBB7_7
+; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
+; X64-RETPOLINE-NEXT:    retq
 ; X64-RETPOLINE-NEXT:  .LBB7_6:
 ; X64-RETPOLINE-NEXT:    cmoveq %rax, %rcx
+; X64-RETPOLINE-NEXT:    shlq $47, %rcx
 ; X64-RETPOLINE-NEXT:    movl $2, %eax
-; X64-RETPOLINE-NEXT:    jmp .LBB7_7
-; X64-RETPOLINE-NEXT:  .LBB7_8: # %bb1
+; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
+; X64-RETPOLINE-NEXT:    retq
+; X64-RETPOLINE-NEXT:  .LBB7_7: # %bb1
 ; X64-RETPOLINE-NEXT:    cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT:    shlq $47, %rcx
 ; X64-RETPOLINE-NEXT:    movl $7, %eax
-; X64-RETPOLINE-NEXT:    jmp .LBB7_7
-; X64-RETPOLINE-NEXT:  .LBB7_9: # %bb3
+; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
+; X64-RETPOLINE-NEXT:    retq
+; X64-RETPOLINE-NEXT:  .LBB7_8: # %bb3
 ; X64-RETPOLINE-NEXT:    cmovneq %rax, %rcx
-; X64-RETPOLINE-NEXT:    movl $42, %eax
-; X64-RETPOLINE-NEXT:  .LBB7_7: # %bb0
 ; X64-RETPOLINE-NEXT:    shlq $47, %rcx
+; X64-RETPOLINE-NEXT:    movl $42, %eax
 ; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
 ; X64-RETPOLINE-NEXT:    retq
 entry:
   switch i32 %idx, label %bb0 [
     i32 0, label %bb1
     i32 1, label %bb2
     i32 2, label %bb3
     i32 3, label %bb5

 ; X64-PIC-NEXT:    movq $-1, %r10
 ; X64-PIC-NEXT:    sarq $63, %r9
 ; X64-PIC-NEXT:    cmpl $3, %edi
 ; X64-PIC-NEXT:    ja .LBB7_2
 ; X64-PIC-NEXT:  # %bb.1: # %entry
 ; X64-PIC-NEXT:    cmovaq %r10, %r9
 ; X64-PIC-NEXT:    xorl %eax, %eax
 ; X64-PIC-NEXT:    movl %edi, %esi
-; X64-PIC-NEXT:    leaq .LJTI7_0(%rip), %rdi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rdi
 ; X64-PIC-NEXT:    movslq (%rdi,%rsi,4), %rsi
 ; X64-PIC-NEXT:    addq %rdi, %rsi
 ; X64-PIC-NEXT:    orq %r9, %rsi
 ; X64-PIC-NEXT:    jmpq *%rsi
 ; X64-PIC-NEXT:  .LBB7_2: # %bb0
 ; X64-PIC-NEXT:    cmovbeq %r10, %r9
 ; X64-PIC-NEXT:    movl (%rsi), %eax
 ; X64-PIC-NEXT:    orl %r9d, %eax
-; X64-PIC-NEXT:    leaq .LBB7_3(%rip), %rsi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:  .LBB7_3: # %bb1
-; X64-PIC-NEXT:    leaq .LBB7_3(%rip), %rdi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rdi
 ; X64-PIC-NEXT:    cmpq %rdi, %rsi
 ; X64-PIC-NEXT:    cmovneq %r10, %r9
 ; X64-PIC-NEXT:    addl (%rdx), %eax
 ; X64-PIC-NEXT:    orl %r9d, %eax
-; X64-PIC-NEXT:    leaq .LBB7_4(%rip), %rsi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:  .LBB7_4: # %bb2
-; X64-PIC-NEXT:    leaq .LBB7_4(%rip), %rdx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rdx
 ; X64-PIC-NEXT:    cmpq %rdx, %rsi
 ; X64-PIC-NEXT:    cmovneq %r10, %r9
 ; X64-PIC-NEXT:    addl (%rcx), %eax
 ; X64-PIC-NEXT:    orl %r9d, %eax
-; X64-PIC-NEXT:    leaq .LBB7_5(%rip), %rsi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:  .LBB7_5: # %bb3
-; X64-PIC-NEXT:    leaq .LBB7_5(%rip), %rcx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-PIC-NEXT:    cmpq %rcx, %rsi
 ; X64-PIC-NEXT:    cmovneq %r10, %r9
 ; X64-PIC-NEXT:    addl (%r8), %eax
 ; X64-PIC-NEXT:    orl %r9d, %eax
-; X64-PIC-NEXT:    leaq .LBB7_6(%rip), %rsi
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rsi
 ; X64-PIC-NEXT:  .LBB7_6: # %bb4
-; X64-PIC-NEXT:    leaq .LBB7_6(%rip), %rcx
+; X64-PIC-NEXT:    leaq {{.*}}(%rip), %rcx
 ; X64-PIC-NEXT:    cmpq %rcx, %rsi
 ; X64-PIC-NEXT:    cmovneq %r10, %r9
 ; X64-PIC-NEXT:    shlq $47, %r9
 ; X64-PIC-NEXT:    orq %r9, %rsp
 ; X64-PIC-NEXT:    retq
 ;
 ; X64-RETPOLINE-LABEL: test_switch_jumptable_fallthrough:
 ; X64-RETPOLINE:       # %bb.0: # %entry

llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll

 ; X64-NEXT:  .Lslh_ret_addr4:
 ; X64-NEXT:    movq %rsp, %rcx
 ; X64-NEXT:    movq -{{[0-9]+}}(%rsp), %rdx
 ; X64-NEXT:    sarq $63, %rcx
 ; X64-NEXT:    cmpq $.Lslh_ret_addr4, %rdx
 ; X64-NEXT:    cmovneq %r15, %rcx
 ; X64-NEXT:    movl %ebp, (%rax)
 ; X64-NEXT:  .Ltmp0:
-; X64-NEXT:    xorl %esi, %esi
-; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movq %rax, %rdi
+; X64-NEXT:    xorl %esi, %esi
+; X64-NEXT:    xorl %edx, %edx
 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    callq __cxa_throw
 ; X64-NEXT:  .Lslh_ret_addr5:
 ; X64-NEXT:    movq %rsp, %rax
 ; X64-NEXT:    movq -{{[0-9]+}}(%rsp), %rcx
 ; X64-NEXT:    sarq $63, %rax
 ; X64-NEXT:    cmpq $.Lslh_ret_addr5, %rcx
 ; X64-NEXT:    cmovneq %r15, %rax

 ; X64-LFENCE-NEXT:    movq %rsi, %rbx
 ; X64-LFENCE-NEXT:    lfence
 ; X64-LFENCE-NEXT:    movslq %edi, %rax
 ; X64-LFENCE-NEXT:    movl (%rsi,%rax,4), %ebp
 ; X64-LFENCE-NEXT:    movl $4, %edi
 ; X64-LFENCE-NEXT:    callq __cxa_allocate_exception
 ; X64-LFENCE-NEXT:    movl %ebp, (%rax)
 ; X64-LFENCE-NEXT:  .Ltmp0:
+; X64-LFENCE-NEXT:    movq %rax, %rdi
 ; X64-LFENCE-NEXT:    xorl %esi, %esi
 ; X64-LFENCE-NEXT:    xorl %edx, %edx
-; X64-LFENCE-NEXT:    movq %rax, %rdi
 ; X64-LFENCE-NEXT:    callq __cxa_throw
 ; X64-LFENCE-NEXT:  .Ltmp1:
 ; X64-LFENCE-NEXT:  .LBB4_2: # %exit
 ; X64-LFENCE-NEXT:    lfence
 ; X64-LFENCE-NEXT:    popq %rbx
 ; X64-LFENCE-NEXT:    .cfi_def_cfa_offset 24
 ; X64-LFENCE-NEXT:    popq %r14
 ; X64-LFENCE-NEXT:    .cfi_def_cfa_offset 16

llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll

; X64-AVX512-NEXT:    retq ## encoding: [0xc3]
   ret i32 %res
 }
 
 
 define i32 @test_x86_sse42_pcmpestria128(<16 x i8> %a0, <16 x i8> %a2) nounwind {
 ; X86-SSE-LABEL: test_x86_sse42_pcmpestria128:
 ; X86-SSE:       ## %bb.0:
 ; X86-SSE-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X86-SSE-NEXT:    seta %bl ## encoding: [0x0f,0x97,0xc3]
 ; X86-SSE-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-SSE-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-SSE-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X86-AVX-LABEL: test_x86_sse42_pcmpestria128:
 ; X86-AVX:       ## %bb.0:
 ; X86-AVX-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X86-AVX-NEXT:    seta %bl ## encoding: [0x0f,0x97,0xc3]
 ; X86-AVX-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-AVX-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-AVX-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X64-SSE-LABEL: test_x86_sse42_pcmpestria128:
 ; X64-SSE:       ## %bb.0:
+; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X64-SSE-NEXT:    seta %sil ## encoding: [0x40,0x0f,0x97,0xc6]
 ; X64-SSE-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-SSE-NEXT:    retq ## encoding: [0xc3]
 ;
 ; X64-AVX-LABEL: test_x86_sse42_pcmpestria128:
 ; X64-AVX:       ## %bb.0:
+; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X64-AVX-NEXT:    seta %sil ## encoding: [0x40,0x0f,0x97,0xc6]
 ; X64-AVX-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-AVX-NEXT:    retq ## encoding: [0xc3]
   %res = call i32 @llvm.x86.sse42.pcmpestria128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
 declare i32 @llvm.x86.sse42.pcmpestria128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
 
 
 define i32 @test_x86_sse42_pcmpestric128(<16 x i8> %a0, <16 x i8> %a2) nounwind {
 ; X86-SSE-LABEL: test_x86_sse42_pcmpestric128:
 ; X86-SSE:       ## %bb.0:
 ; X86-SSE-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X86-SSE-NEXT:    setb %bl ## encoding: [0x0f,0x92,0xc3]
 ; X86-SSE-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-SSE-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-SSE-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X86-AVX-LABEL: test_x86_sse42_pcmpestric128:
 ; X86-AVX:       ## %bb.0:
 ; X86-AVX-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X86-AVX-NEXT:    setb %bl ## encoding: [0x0f,0x92,0xc3]
 ; X86-AVX-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-AVX-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-AVX-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X64-SSE-LABEL: test_x86_sse42_pcmpestric128:
 ; X64-SSE:       ## %bb.0:
+; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X64-SSE-NEXT:    setb %sil ## encoding: [0x40,0x0f,0x92,0xc6]
 ; X64-SSE-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-SSE-NEXT:    retq ## encoding: [0xc3]
 ;
 ; X64-AVX-LABEL: test_x86_sse42_pcmpestric128:
 ; X64-AVX:       ## %bb.0:
+; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X64-AVX-NEXT:    setb %sil ## encoding: [0x40,0x0f,0x92,0xc6]
 ; X64-AVX-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-AVX-NEXT:    retq ## encoding: [0xc3]
   %res = call i32 @llvm.x86.sse42.pcmpestric128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
 declare i32 @llvm.x86.sse42.pcmpestric128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
 
 
 define i32 @test_x86_sse42_pcmpestrio128(<16 x i8> %a0, <16 x i8> %a2) nounwind {
 ; X86-SSE-LABEL: test_x86_sse42_pcmpestrio128:
 ; X86-SSE:       ## %bb.0:
 ; X86-SSE-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X86-SSE-NEXT:    seto %bl ## encoding: [0x0f,0x90,0xc3]
 ; X86-SSE-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-SSE-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-SSE-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X86-AVX-LABEL: test_x86_sse42_pcmpestrio128:
 ; X86-AVX:       ## %bb.0:
 ; X86-AVX-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X86-AVX-NEXT:    seto %bl ## encoding: [0x0f,0x90,0xc3]
 ; X86-AVX-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-AVX-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-AVX-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X64-SSE-LABEL: test_x86_sse42_pcmpestrio128:
 ; X64-SSE:       ## %bb.0:
+; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X64-SSE-NEXT:    seto %sil ## encoding: [0x40,0x0f,0x90,0xc6]
 ; X64-SSE-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-SSE-NEXT:    retq ## encoding: [0xc3]
 ;
 ; X64-AVX-LABEL: test_x86_sse42_pcmpestrio128:
 ; X64-AVX:       ## %bb.0:
+; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X64-AVX-NEXT:    seto %sil ## encoding: [0x40,0x0f,0x90,0xc6]
 ; X64-AVX-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-AVX-NEXT:    retq ## encoding: [0xc3]
   %res = call i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
 declare i32 @llvm.x86.sse42.pcmpestrio128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
 
 
 define i32 @test_x86_sse42_pcmpestris128(<16 x i8> %a0, <16 x i8> %a2) nounwind {
 ; X86-SSE-LABEL: test_x86_sse42_pcmpestris128:
 ; X86-SSE:       ## %bb.0:
 ; X86-SSE-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X86-SSE-NEXT:    sets %bl ## encoding: [0x0f,0x98,0xc3]
 ; X86-SSE-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-SSE-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-SSE-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X86-AVX-LABEL: test_x86_sse42_pcmpestris128:
 ; X86-AVX:       ## %bb.0:
 ; X86-AVX-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X86-AVX-NEXT:    sets %bl ## encoding: [0x0f,0x98,0xc3]
 ; X86-AVX-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-AVX-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-AVX-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X64-SSE-LABEL: test_x86_sse42_pcmpestris128:
 ; X64-SSE:       ## %bb.0:
+; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X64-SSE-NEXT:    sets %sil ## encoding: [0x40,0x0f,0x98,0xc6]
 ; X64-SSE-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-SSE-NEXT:    retq ## encoding: [0xc3]
 ;
 ; X64-AVX-LABEL: test_x86_sse42_pcmpestris128:
 ; X64-AVX:       ## %bb.0:
+; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X64-AVX-NEXT:    sets %sil ## encoding: [0x40,0x0f,0x98,0xc6]
 ; X64-AVX-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-AVX-NEXT:    retq ## encoding: [0xc3]
   %res = call i32 @llvm.x86.sse42.pcmpestris128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
 declare i32 @llvm.x86.sse42.pcmpestris128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone
 
 
 define i32 @test_x86_sse42_pcmpestriz128(<16 x i8> %a0, <16 x i8> %a2) nounwind {
 ; X86-SSE-LABEL: test_x86_sse42_pcmpestriz128:
 ; X86-SSE:       ## %bb.0:
 ; X86-SSE-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X86-SSE-NEXT:    sete %bl ## encoding: [0x0f,0x94,0xc3]
 ; X86-SSE-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-SSE-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-SSE-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X86-AVX-LABEL: test_x86_sse42_pcmpestriz128:
 ; X86-AVX:       ## %bb.0:
 ; X86-AVX-NEXT:    pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X86-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT:    xorl %ebx, %ebx ## encoding: [0x31,0xdb]
 ; X86-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X86-AVX-NEXT:    sete %bl ## encoding: [0x0f,0x94,0xc3]
 ; X86-AVX-NEXT:    movl %ebx, %eax ## encoding: [0x89,0xd8]
 ; X86-AVX-NEXT:    popl %ebx ## encoding: [0x5b]
 ; X86-AVX-NEXT:    retl ## encoding: [0xc3]
 ;
 ; X64-SSE-LABEL: test_x86_sse42_pcmpestriz128:
 ; X64-SSE:       ## %bb.0:
+; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-SSE-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-SSE-NEXT:    pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
 ; X64-SSE-NEXT:    sete %sil ## encoding: [0x40,0x0f,0x94,0xc6]
 ; X64-SSE-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-SSE-NEXT:    retq ## encoding: [0xc3]
 ;
 ; X64-AVX-LABEL: test_x86_sse42_pcmpestriz128:
 ; X64-AVX:       ## %bb.0:
+; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
 ; X64-AVX-NEXT:    movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT:    xorl %esi, %esi ## encoding: [0x31,0xf6]
 ; X64-AVX-NEXT:    vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
 ; X64-AVX-NEXT:    sete %sil ## encoding: [0x40,0x0f,0x94,0xc6]
 ; X64-AVX-NEXT:    movl %esi, %eax ## encoding: [0x89,0xf0]
 ; X64-AVX-NEXT:    retq ## encoding: [0xc3]
   %res = call i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8> %a0, i32 7, <16 x i8> %a2, i32 7, i8 7) ; <i32> [#uses=1]
   ret i32 %res
 }
 declare i32 @llvm.x86.sse42.pcmpestriz128(<16 x i8>, i32, <16 x i8>, i32, i8) nounwind readnone

llvm/trunk/test/CodeGen/X86/vector-idiv-v2i32.ll

 ; X86-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,0,1]
 ; X86-NEXT:    movd %xmm0, %eax
 ; X86-NEXT:    movd %xmm1, %ebx
 ; X86-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,1,0,1]
 ; X86-NEXT:    movd %xmm1, %esi
 ; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    divl %esi
 ; X86-NEXT:    movl %eax, %esi
-; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    movl %ecx, %eax
+; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    divl %ebx
 ; X86-NEXT:    movd %eax, %xmm0
 ; X86-NEXT:    movd %esi, %xmm1
 ; X86-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; X86-NEXT:    movq %xmm0, (%edi)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    popl %edi
 ; X86-NEXT:    popl %ebx

 ; X86_WIDEN-NEXT:    movl {{[0-9]+}}(%esp), %edi
 ; X86_WIDEN-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; X86_WIDEN-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86_WIDEN-NEXT:    movl (%ecx), %eax
 ; X86_WIDEN-NEXT:    movl 4(%ecx), %ecx
 ; X86_WIDEN-NEXT:    xorl %edx, %edx
 ; X86_WIDEN-NEXT:    divl (%ebx)
 ; X86_WIDEN-NEXT:    movl %eax, %esi
-; X86_WIDEN-NEXT:    xorl %edx, %edx
 ; X86_WIDEN-NEXT:    movl %ecx, %eax
+; X86_WIDEN-NEXT:    xorl %edx, %edx
 ; X86_WIDEN-NEXT:    divl 4(%ebx)
 ; X86_WIDEN-NEXT:    movl %eax, 4(%edi)
 ; X86_WIDEN-NEXT:    movl %esi, (%edi)
 ; X86_WIDEN-NEXT:    popl %esi
 ; X86_WIDEN-NEXT:    popl %edi
 ; X86_WIDEN-NEXT:    popl %ebx
 ; X86_WIDEN-NEXT:    retl
   %a = load <2 x i32>, <2 x i32>* %x

 ; X86-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,0,1]
 ; X86-NEXT:    movd %xmm0, %eax
 ; X86-NEXT:    movd %xmm1, %ebx
 ; X86-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,1,0,1]
 ; X86-NEXT:    movd %xmm1, %esi
 ; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    divl %esi
 ; X86-NEXT:    movl %edx, %esi
-; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    movl %ecx, %eax
+; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    divl %ebx
 ; X86-NEXT:    movd %edx, %xmm0
 ; X86-NEXT:    movd %esi, %xmm1
 ; X86-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; X86-NEXT:    movq %xmm0, (%edi)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    popl %edi
 ; X86-NEXT:    popl %ebx

 ; X86_WIDEN-NEXT:    movl {{[0-9]+}}(%esp), %edi
 ; X86_WIDEN-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; X86_WIDEN-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86_WIDEN-NEXT:    movl (%ecx), %eax
 ; X86_WIDEN-NEXT:    movl 4(%ecx), %ecx
 ; X86_WIDEN-NEXT:    xorl %edx, %edx
 ; X86_WIDEN-NEXT:    divl (%ebx)
 ; X86_WIDEN-NEXT:    movl %edx, %esi
-; X86_WIDEN-NEXT:    xorl %edx, %edx
 ; X86_WIDEN-NEXT:    movl %ecx, %eax
+; X86_WIDEN-NEXT:    xorl %edx, %edx
 ; X86_WIDEN-NEXT:    divl 4(%ebx)
 ; X86_WIDEN-NEXT:    movl %edx, 4(%edi)
 ; X86_WIDEN-NEXT:    movl %esi, (%edi)
 ; X86_WIDEN-NEXT:    popl %esi
 ; X86_WIDEN-NEXT:    popl %edi
 ; X86_WIDEN-NEXT:    popl %ebx
 ; X86_WIDEN-NEXT:    retl
   %a = load <2 x i32>, <2 x i32>* %x

llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll

 if.end:                                           ; preds = %for.body, %if.else
   %sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]
   ret i32 %sum.0
 }
 
 ; Check that we handle calls to variadic functions correctly.
 ; CHECK-LABEL: callVariadicFunc:
 ;
+; ENABLE: movl %esi, %eax
 ; ENABLE: testl %edi, %edi
 ; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Prologue code.
 ; CHECK: pushq
 ;
+; DISABLE: movl %esi, %eax
 ; DISABLE: testl %edi, %edi
 ; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
 ;
 ; Setup of the varags.
-; CHECK: movl %esi, (%rsp)
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: %esi, %edi
-; CHECK-NEXT: %esi, %edx
-; CHECK-NEXT: %esi, %ecx
-; CHECK-NEXT: %esi, %r8d
-; CHECK-NEXT: %esi, %r9d
+; CHECK:       movl %eax, (%rsp)
+; CHECK-NEXT:  movl %eax, %edi
+; CHECK-NEXT:  movl %eax, %esi
+; CHECK-NEXT:  movl %eax, %edx
+; CHECK-NEXT:  movl %eax, %ecx
+; CHECK-NEXT:  movl %eax, %r8d
+; CHECK-NEXT:  movl %eax, %r9d
+; CHECK-NEXT:  xorl %eax, %eax
 ; CHECK-NEXT: callq _someVariadicFunc
-; CHECK-NEXT: movl %eax, %esi
-; CHECK-NEXT: shll $3, %esi
+; CHECK-NEXT: shll $3, %eax
 ;
 ; ENABLE-NEXT: addq $8, %rsp
-; ENABLE-NEXT: movl %esi, %eax
 ; ENABLE-NEXT: retq
 ;
-; DISABLE: jmp [[IFEND_LABEL:LBB[0-9_]+]]
-;
+
 ; CHECK: [[ELSE_LABEL]]: ## %if.else
 ; Shift second argument by one and store into returned register.
-; CHECK: addl %esi, %esi
-;
-; DISABLE: [[IFEND_LABEL]]: ## %if.end
+; CHECK: addl %eax, %eax
 ;
 ; Epilogue code.
-; CHECK-NEXT: movl %esi, %eax
 ; DISABLE-NEXT: popq
 ; CHECK-NEXT: retq
 define i32 @callVariadicFunc(i32 %cond, i32 %N) {
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry

llvm/trunk/test/DebugInfo/X86/live-debug-values.ll

 ; extension is tested here.
 
 ; DBG_VALUE for variable "n" is extended into %bb.5 from its predecessors %bb.3
 ; and %bb.4.
 ; CHECK:       .LBB0_5:
 ; CHECK-NEXT:  #DEBUG_VALUE: main:n <- $ebx
 ;   Other register values have been clobbered.
 ; CHECK-NOT:   #DEBUG_VALUE:
-; CHECK:         movl    %esi, m(%rip)
+; CHECK:         movl    %e{{..}}, m(%rip)
 
 ; ModuleID = 'LiveDebugValues.c'
 source_filename = "test/DebugInfo/X86/live-debug-values.ll"
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 @m = common global i32 0, align 4, !dbg !0
 @.str = private unnamed_addr constant [13 x i8] c"m(main): %d\0A\00", align 1