[WebAssembly] Retain shuffle types during custom lowering

[tlively]

Summary

Changing the node type in lowering was violating assumptions made in
the DAG combiner, so don't change the node type any more. This fixes
one of the issues reported in bug 39275.

[aheejin]

I think adding which DAGCombiner assertion the previous code broke on the CL description / commit message would help readers. Otherwise LGTM

llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

for (size_t I = 0, Lanes = Mask.size(); I < Lanes; ++I) {
     for (size_t J = 0; J < LaneBytes; ++J) {
       // Lower undefs (represented by -1 in mask) to zero
       uint64_t ByteIndex =
           Mask[I] == -1 ? 0 : (uint64_t)Mask[I] * LaneBytes + J;
       Ops[OpIdx++] = DAG.getConstant(ByteIndex, DL, MVT::i32);
     }
   }
 
-  return DAG.getNode(WebAssemblyISD::SHUFFLE, DL, MVT::v16i8, Ops);
+  return DAG.getNode(WebAssemblyISD::SHUFFLE, DL, Op.getValueType(), Ops);
 }
 
 SDValue WebAssemblyTargetLowering::LowerShift(SDValue Op,
                                               SelectionDAG &DAG) const {
   SDLoc DL(Op);
   auto *ShiftVec = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
   APInt SplatValue, SplatUndef;
   unsigned SplatBitSize;

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

def : Pat<(v4f32 (build_vector
             )),
             3, F32:$x3
           ))>;
 def : Pat<(v2f64 (build_vector (f64 F64:$x0), (f64 F64:$x1))),
           (v2f64 (REPLACE_LANE_v2f64
             (v2f64 (SPLAT_v2f64 (f64 F64:$x0))), 1, F64:$x1))>;
 
 // Shuffle lanes: shuffle
-defm SHUFFLE_v16i8 :
+defm SHUFFLE :
   SIMD_I<(outs V128:$dst),
          (ins V128:$x, V128:$y,
            vec_i8imm_op:$m0, vec_i8imm_op:$m1,
            vec_i8imm_op:$m2, vec_i8imm_op:$m3,
            vec_i8imm_op:$m4, vec_i8imm_op:$m5,
            vec_i8imm_op:$m6, vec_i8imm_op:$m7,
            vec_i8imm_op:$m8, vec_i8imm_op:$m9,
            vec_i8imm_op:$mA, vec_i8imm_op:$mB,
SIMD_I<(outs V128:$dst),
            "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
            "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
          23>;
 
 // Shuffles after custom lowering
 def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
 def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
-def : Pat<(v16i8 (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
+def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
             (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
             (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
             (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
             (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
             (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
             (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
             (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
             (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))),
-          (v16i8 (SHUFFLE_v16i8 (vec_t V128:$x), (vec_t V128:$y),
+          (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y),
             (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
             (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
             (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
             (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
             (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
             (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
             (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
             (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;

llvm/trunk/test/CodeGen/WebAssembly/simd-nested-shuffles.ll

+; RUN: llc < %s -mattr=+simd128 | FileCheck %s --check-prefixes CHECK
+
+; Check that shuffles maintain their type when being custom
+; lowered. Regression test for bug 39275.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK: v8x16.shuffle
+define <4 x i32> @foo(<4 x i32> %x) {
+  %1 = shufflevector <4 x i32> %x, <4 x i32> undef,
+    <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef,
+    <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+  %3 = add <4 x i32> %2, %2
+  ret <4 x i32> %3
+}