[llvm-mca] Move namespace mca inside llvm::

[MaskRay]

Summary

This allows to remove using namespace llvm; in those *.cpp files

[MaskRay]

Friendly ping :)

[andreadb]

In D53407#1272829, @MaskRay wrote:

Friendly ping :)

Hi!

Thanks for the patch.

I am okay with this change provided that you only change files in llvm-mca/include or in llvm-mca/lib.
There is a plan to move the core abstractions of llvm-mca into llvm/lib (at some point; hopefully in the near future). So, files that are not part of the library (for example, Views) should not be touched.

Also, if you are going to move namespace mca under namespace llvm, then please update the code by removing all the redundant llvm:: prefixes.

Thanks,
-Andrea

[MaskRay]

I am okay with this change provided that you only change files in llvm-mca/include or in llvm-mca/lib.

Why is the difference between llvm-mca/include/* and llvm-mca/Views/*?

If llvm-mca/Views/* names want to stay in namespace mca, as they reference llvm-mca/include/*, they need to be written as:

namespace mca {
using namespace llvm::mca;

or use qualified llvm::mca::* (which is clumsy)

Having both namespace mca and namespace llvm::mca will make it easy to cause name conflict.

[andreadb]

In D53407#1274525, @MaskRay wrote:

I am okay with this change provided that you only change files in llvm-mca/include or in llvm-mca/lib.

Why is the difference between llvm-mca/include/* and llvm-mca/Views/*?

If llvm-mca/Views/* names want to stay in namespace mca, as they reference llvm-mca/include/*, they need to be written as:

namespace mca {
using namespace llvm::mca;

or use qualified llvm::mca::* (which is clumsy)

Having both namespace mca and namespace llvm::mca will make it easy to cause name conflict.

I am okay with having the core abstractions defined inside namespace llvm::mca.
I am not a big fan of having all the driver components (like views) defined in namespace llvm::mca too. If the ultimate goal is just to remove a bunch of "using namespace" from a few files, then this patch looks like a too big change for very little gain.

That being said. I am not strongly against this change. So, I spoke with other people about your patch. We definitely want to move the core abstractions of mca inside namespace llvm; that would simplify the transition from the tools/mca directory to llvm/lib. We all agree that (at least conceptually) it is much nicer if driver abstractions don't live inside of namespace llvm. However, nobody felt strongly about it either.

In conclusion. It is fine if you want to move everything under llvm::mca. However, we may revisit this decision in future.

Please rebase your original patch, and remove all the redundant llvm:: prefixes from header files when possible.

Thanks,
Andrea

[MaskRay]

In D53407#1278719, @andreadb wrote:

In D53407#1274525, @MaskRay wrote:

I am okay with this change provided that you only change files in llvm-mca/include or in llvm-mca/lib.

Why is the difference between llvm-mca/include/* and llvm-mca/Views/*?

If llvm-mca/Views/* names want to stay in namespace mca, as they reference llvm-mca/include/*, they need to be written as:

namespace mca {
using namespace llvm::mca;

or use qualified llvm::mca::* (which is clumsy)

Having both namespace mca and namespace llvm::mca will make it easy to cause name conflict.

I am okay with having the core abstractions defined inside namespace llvm::mca.
I am not a big fan of having all the driver components (like views) defined in namespace llvm::mca too. If the ultimate goal is just to remove a bunch of "using namespace" from a few files, then this patch looks like a too big change for very little gain.

That being said. I am not strongly against this change. So, I spoke with other people about your patch. We definitely want to move the core abstractions of mca inside namespace llvm; that would simplify the transition from the tools/mca directory to llvm/lib. We all agree that (at least conceptually) it is much nicer if driver abstractions don't live inside of namespace llvm. However, nobody felt strongly about it either.

In conclusion. It is fine if you want to move everything under llvm::mca. However, we may revisit this decision in future.

Please rebase your original patch, and remove all the redundant llvm:: prefixes from header files when possible.

Thanks,
Andrea

Thanks for the feedback.

Rebased. I decide to go with the easy route: moving the whole namespace mca inside llvm:: , the justification is

• Having both llvm::mca mca cause namespace lookup ambiguity for mca::
• In driver components' header files, I would otherwise use llvm::mca::* (core abstractions) here and there

When we want to revisit the decision (everything in llvm::mca::*) in the future, we can move things to a nested namespace of llvm::mca::, to conceptually make them separate from the rest of llvm::mca::*

[andreadb]

LGTM. Thanks!

tools/llvm-mca/CodeRegion.h

 #define LLVM_TOOLS_LLVM_MCA_CODEREGION_H
 
 #include "llvm/ADT/StringRef.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/SMLoc.h"
 #include "llvm/Support/SourceMgr.h"
 #include <vector>
 
+namespace llvm {
 namespace mca {
 
 /// A region of assembly code.
 ///
 /// It identifies a sequence of machine instructions.
 class CodeRegion {
   // An optional descriptor for this region.
   llvm::StringRef Description;
bool empty() const {
     return std::all_of(Regions.begin(), Regions.end(),
                        [](const std::unique_ptr<CodeRegion> &Region) {
                          return Region->empty();
                        });
   }
 };
 
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/CodeRegion.cpp

 //===-------------------------- CodeRegion.cpp -----------------*- C++ -* -===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements methods from the CodeRegions interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "CodeRegion.h"
 
-using namespace llvm;
-
+namespace llvm {
 namespace mca {
 
 bool CodeRegion::isLocInRange(SMLoc Loc) const {
   if (RangeEnd.isValid() && Loc.getPointer() > RangeEnd.getPointer())
     return false;
   if (RangeStart.isValid() && Loc.getPointer() < RangeStart.getPointer())
     return false;
   return true;
const auto It =
                    [Loc](const std::unique_ptr<CodeRegion> &Region) {
                      return Region->isLocInRange(Loc);
                    });
   if (It != Regions.rend())
     (*It)->addInstruction(std::move(Instruction));
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/PipelinePrinter.h

 
 #include "Pipeline.h"
 #include "Views/View.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
+namespace llvm {
 namespace mca {
 
 /// A printer class that knows how to collects statistics on the
 /// code analyzed by the llvm-mca tool.
 ///
 /// This class knows how to print out the analysis information collected
 /// during the execution of the code. Internally, it delegates to other
 /// classes the task of printing out timeline information as well as
 /// resource pressure.
 class PipelinePrinter {
   Pipeline &P;
   llvm::SmallVector<std::unique_ptr<View>, 8> Views;
 
 public:
   PipelinePrinter(Pipeline &pipeline) : P(pipeline) {}
 
   void addView(std::unique_ptr<View> V) {
     P.addEventListener(V.get());
     Views.emplace_back(std::move(V));
   }
 
   void printReport(llvm::raw_ostream &OS) const;
 };
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H

tools/llvm-mca/PipelinePrinter.cpp

 ///
 /// This file implements the PipelinePrinter interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "PipelinePrinter.h"
 #include "Views/View.h"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 void PipelinePrinter::printReport(llvm::raw_ostream &OS) const {
   for (const auto &V : Views)
     V->printView(OS);
 }
 } // namespace mca.
+} // namespace llvm

tools/llvm-mca/Views/DispatchStatistics.h

 #ifndef LLVM_TOOLS_LLVM_MCA_DISPATCHVIEW_H
 #define LLVM_TOOLS_LLVM_MCA_DISPATCHVIEW_H
 
 #include "Views/View.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
+namespace llvm {
 namespace mca {
 
 class DispatchStatistics : public View {
   unsigned NumDispatched;
   unsigned NumCycles;
 
   // Counts dispatch stall events caused by unavailability of resources.  There
   // is one counter for every generic stall kind (see class HWStallEvent).
public:
   void onCycleEnd() override { updateHistograms(); }
 
   void printView(llvm::raw_ostream &OS) const override {
     printDispatchStalls(OS);
     printDispatchHistogram(OS);
   }
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/Views/DispatchStatistics.cpp

 ///
 /// This file implements the DispatchStatistics interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/DispatchStatistics.h"
 #include "llvm/Support/Format.h"
 
-using namespace llvm;
-
+namespace llvm {
 namespace mca {
 
 void DispatchStatistics::onEvent(const HWStallEvent &Event) {
   if (Event.Type < HWStallEvent::LastGenericEvent)
     HWStalls[Event.Type]++;
 }
 
 void DispatchStatistics::onEvent(const HWInstructionEvent &Event) {
void DispatchStatistics::printDispatchStalls(raw_ostream &OS) const {
   SS << "\nGROUP   - Static restrictions on the dispatch group: ";
   printStalls(SS, HWStalls[HWStallEvent::DispatchGroupStall], NumCycles);
   SS << '\n';
   SS.flush();
   OS << Buffer;
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/Views/InstructionInfoView.h

 #include "Views/View.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
+namespace llvm {
 namespace mca {
 
 /// A view that prints out generic instruction information.
 class InstructionInfoView : public View {
   const llvm::MCSubtargetInfo &STI;
   const llvm::MCInstrInfo &MCII;
   const SourceMgr &Source;
   llvm::MCInstPrinter &MCIP;
 
 public:
   InstructionInfoView(const llvm::MCSubtargetInfo &sti,
                       const llvm::MCInstrInfo &mcii, const SourceMgr &S,
                       llvm::MCInstPrinter &IP)
       : STI(sti), MCII(mcii), Source(S), MCIP(IP) {}
 
   void printView(llvm::raw_ostream &OS) const override;
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/Views/InstructionInfoView.cpp

 //===--------------------- InstructionInfoView.cpp --------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements the InstructionInfoView API.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/InstructionInfoView.h"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 void InstructionInfoView::printView(raw_ostream &OS) const {
   std::string Buffer;
   raw_string_ostream TempStream(Buffer);
   const MCSchedModel &SM = STI.getSchedModel();
   unsigned Instructions = Source.size();
 
   std::string Instruction;
   raw_string_ostream InstrStream(Instruction);
for (unsigned I = 0, E = Instructions; I < E; ++I) {
     TempStream << "    " << Str << '\n';
     Instruction = "";
   }
 
   TempStream.flush();
   OS << Buffer;
 }
 } // namespace mca.
+} // namespace llvm

tools/llvm-mca/Views/RegisterFileStatistics.h

 
 #ifndef LLVM_TOOLS_LLVM_MCA_REGISTERFILESTATISTICS_H
 #define LLVM_TOOLS_LLVM_MCA_REGISTERFILESTATISTICS_H
 
 #include "Views/View.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
+namespace llvm {
 namespace mca {
 
 class RegisterFileStatistics : public View {
   const llvm::MCSubtargetInfo &STI;
 
   // Used to track the number of physical registers used in a register file.
   struct RegisterFileUsage {
     unsigned TotalMappings;
     unsigned MaxUsedMappings;
     unsigned CurrentlyUsedMappings;
   };
 
   // There is one entry for each register file implemented by the processor.
   llvm::SmallVector<RegisterFileUsage, 4> RegisterFiles;
 
 public:
   RegisterFileStatistics(const llvm::MCSubtargetInfo &sti);
 
   void onEvent(const HWInstructionEvent &Event) override;
   void printView(llvm::raw_ostream &OS) const override;
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/Views/RegisterFileStatistics.cpp

 ///
 /// This file implements the RegisterFileStatistics interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/RegisterFileStatistics.h"
 #include "llvm/Support/Format.h"
 
-using namespace llvm;
-
+namespace llvm {
 namespace mca {
 
 RegisterFileStatistics::RegisterFileStatistics(const llvm::MCSubtargetInfo &sti)
     : STI(sti) {
   const MCSchedModel &SM = STI.getSchedModel();
   RegisterFileUsage Empty = {0, 0, 0};
   if (!SM.hasExtraProcessorInfo()) {
     // Assume a single register file.
TempStream << "\n   Max number of mappings used:      "
                << RFU.MaxUsedMappings << '\n';
   }
 
   TempStream.flush();
   OS << Buffer;
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/Views/ResourcePressureView.h

 
 #include "SourceMgr.h"
 #include "Views/View.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
+namespace llvm {
 namespace mca {
 
 /// This class collects resource pressure statistics and it is able to print
 /// out all the collected information as a table to an output stream.
 class ResourcePressureView : public View {
   const llvm::MCSubtargetInfo &STI;
   llvm::MCInstPrinter &MCIP;
   const SourceMgr &Source;
public:
 
   void printView(llvm::raw_ostream &OS) const override {
     unsigned Executions = Source.getNumIterations();
     printResourcePressurePerIteration(OS, Executions);
     printResourcePressurePerInstruction(OS, Executions);
   }
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/Views/ResourcePressureView.cpp

 /// This file implements methods in the ResourcePressureView interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/ResourcePressureView.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/raw_ostream.h"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 void ResourcePressureView::initialize() {
   // Populate the map of resource descriptors.
   unsigned R2VIndex = 0;
   const MCSchedModel &SM = STI.getSchedModel();
   for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
     const MCProcResourceDesc &ProcResource = *SM.getProcResource(I);
     unsigned NumUnits = ProcResource.NumUnits;
     // Skip groups and invalid resources with zero units.
for (unsigned I = 0, E = Source.size(); I < E; ++I) {
     Instruction = "";
 
     FOS.flush();
     OS << Buffer;
     Buffer = "";
   }
 }
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/Views/RetireControlUnitStatistics.h

 
 #ifndef LLVM_TOOLS_LLVM_MCA_RETIRECONTROLUNITSTATISTICS_H
 #define LLVM_TOOLS_LLVM_MCA_RETIRECONTROLUNITSTATISTICS_H
 
 #include "Views/View.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
+namespace llvm {
 namespace mca {
 
 class RetireControlUnitStatistics : public View {
   using Histogram = std::map<unsigned, unsigned>;
   Histogram RetiredPerCycle;
 
   unsigned NumRetired;
   unsigned NumCycles;
public:
 
   void onCycleBegin() override { NumCycles++; }
 
   void onCycleEnd() override { updateHistograms(); }
 
   void printView(llvm::raw_ostream &OS) const override;
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/Views/RetireControlUnitStatistics.cpp

 ///
 /// This file implements the RetireControlUnitStatistics interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/RetireControlUnitStatistics.h"
 #include "llvm/Support/Format.h"
 
-using namespace llvm;
-
+namespace llvm {
 namespace mca {
 
 void RetireControlUnitStatistics::onEvent(const HWInstructionEvent &Event) {
   if (Event.Type == HWInstructionEvent::Retired)
     ++NumRetired;
 }
 
 void RetireControlUnitStatistics::printView(llvm::raw_ostream &OS) const {
TempStream << Entry.second << "  ("
                << "%)\n";
   }
 
   TempStream.flush();
   OS << Buffer;
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/Views/SchedulerStatistics.h

 #ifndef LLVM_TOOLS_LLVM_MCA_SCHEDULERSTATISTICS_H
 #define LLVM_TOOLS_LLVM_MCA_SCHEDULERSTATISTICS_H
 
 #include "Views/View.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
+namespace llvm {
 namespace mca {
 
 class SchedulerStatistics final : public View {
   const llvm::MCSchedModel &SM;
   unsigned NumIssued;
   unsigned NumCycles;
 
   // Tracks the usage of a scheduler's queue.
public:
   // Decreases by one the number of used scheduler queue slots of every
   // buffered resource in the Buffers set.
   void onReleasedBuffers(const InstRef &IR,
                          llvm::ArrayRef<unsigned> Buffers) override;
 
   void printView(llvm::raw_ostream &OS) const override;
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/Views/SchedulerStatistics.cpp

 /// This file implements the SchedulerStatistics interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/SchedulerStatistics.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/FormattedStream.h"
 
-using namespace llvm;
-
+namespace llvm {
 namespace mca {
 
 void SchedulerStatistics::onEvent(const HWInstructionEvent &Event) {
   if (Event.Type == HWInstructionEvent::Issued)
     ++NumIssued;
 }
 
 void SchedulerStatistics::onReservedBuffers(const InstRef & /* unused */,

 }
 
 void SchedulerStatistics::printView(llvm::raw_ostream &OS) const {
   printSchedulerStats(OS);
   printSchedulerUsage(OS);
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/Views/SummaryView.h

 #define LLVM_TOOLS_LLVM_MCA_SUMMARYVIEW_H
 
 #include "SourceMgr.h"
 #include "Views/View.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/Support/raw_ostream.h"
 
+namespace llvm {
 namespace mca {
 
 /// A view that collects and prints a few performance numbers.
 class SummaryView : public View {
   const llvm::MCSchedModel &SM;
   const SourceMgr &Source;
   const unsigned DispatchWidth;
   unsigned TotalCycles;
public:
 
   void onCycleEnd() override { ++TotalCycles; }
 
   void onEvent(const HWInstructionEvent &Event) override;
 
   void printView(llvm::raw_ostream &OS) const override;
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/Views/SummaryView.cpp

 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/SummaryView.h"
 #include "Support.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Format.h"
 
+namespace llvm {
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 
-using namespace llvm;
-
 SummaryView::SummaryView(const llvm::MCSchedModel &Model, const SourceMgr &S,
                          unsigned Width)
     : SM(Model), Source(S), DispatchWidth(Width), TotalCycles(0),
       NumMicroOps(0), ProcResourceUsage(Model.getNumProcResourceKinds(), 0),
       ProcResourceMasks(Model.getNumProcResourceKinds(), 0) {
   computeProcResourceMasks(SM, ProcResourceMasks);
 }
 
TempStream << "\nIPC:               "
              << format("%.2f", floor((IPC * 100) + 0.5) / 100);
   TempStream << "\nBlock RThroughput: "
              << format("%.1f", floor((BlockRThroughput * 10) + 0.5) / 10)
              << '\n';
   TempStream.flush();
   OS << Buffer;
 }
 } // namespace mca.
+} // namespace llvm

tools/llvm-mca/Views/TimelineView.h

 
 #include "SourceMgr.h"
 #include "Views/View.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/raw_ostream.h"
 
+namespace llvm {
 namespace mca {
 
 /// This class listens to instruction state transition events
 /// in order to construct a timeline information.
 ///
 /// For every instruction executed by the Pipeline, this class constructs
 /// a TimelineViewEntry object. TimelineViewEntry objects are then used
 /// to print the timeline information, as well as the "average wait times"
public:
   void printTimeline(llvm::raw_ostream &OS) const;
   void printAverageWaitTimes(llvm::raw_ostream &OS) const;
   void printView(llvm::raw_ostream &OS) const override {
     printTimeline(OS);
     printAverageWaitTimes(OS);
   }
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/Views/TimelineView.cpp

 //===--------------------- TimelineView.cpp ---------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \brief
 ///
 /// This file implements the TimelineView interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/TimelineView.h"
 
-using namespace llvm;
-
+namespace llvm {
 namespace mca {
 
 TimelineView::TimelineView(const MCSubtargetInfo &sti, MCInstPrinter &Printer,
                            const SourceMgr &S, unsigned MaxIterations,
                            unsigned Cycles)
     : STI(sti), MCIP(Printer), AsmSequence(S), CurrentCycle(0),
       MaxCycle(Cycles == 0 ? 80 : Cycles), LastCycle(0), WaitTime(S.size()),
       UsedBuffer(S.size()) {
for (unsigned I = 0, E = Timeline.size(); I < E; ++I) {
     StringRef Str(Instruction);
     Str = Str.ltrim();
     FOS << "   " << Str << '\n';
     FOS.flush();
     Instruction = "";
   }
 }
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/Views/View.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_VIEW_H
 #define LLVM_TOOLS_LLVM_MCA_VIEW_H
 
 #include "HWEventListener.h"
 #include "llvm/Support/raw_ostream.h"
 
+namespace llvm {
 namespace mca {
 
 class View : public HWEventListener {
 public:
   virtual void printView(llvm::raw_ostream &OS) const = 0;
   virtual ~View() = default;
   void anchor() override;
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/Views/View.cpp

 //===----------------------- View.cpp ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines the virtual anchor method in View.h to pin the vtable.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Views/View.h"
 
+namespace llvm {
 namespace mca {
 
 void View::anchor() {}
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/include/Context.h

 #include "HardwareUnits/HardwareUnit.h"
 #include "InstrBuilder.h"
 #include "Pipeline.h"
 #include "SourceMgr.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <memory>
 
+namespace llvm {
 namespace mca {
 
 /// This is a convenience struct to hold the parameters necessary for creating
 /// the pre-built "default" out-of-order pipeline.
 struct PipelineOptions {
   PipelineOptions(unsigned DW, unsigned RFS, unsigned LQS, unsigned SQS,
                   bool NoAlias)
       : DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS),
public:
   /// Construct a basic pipeline for simulating an out-of-order pipeline.
   /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
   std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
                                                   InstrBuilder &IB,
                                                   SourceMgr &SrcMgr);
 };
 
 } // namespace mca
+} // namespace llvm
 #endif // LLVM_TOOLS_LLVM_MCA_CONTEXT_H

tools/llvm-mca/include/HWEventListener.h

 
 #ifndef LLVM_TOOLS_LLVM_MCA_HWEVENTLISTENER_H
 #define LLVM_TOOLS_LLVM_MCA_HWEVENTLISTENER_H
 
 #include "Instruction.h"
 #include "Support.h"
 #include "llvm/ADT/ArrayRef.h"
 
+namespace llvm {
 namespace mca {
 
 // An HWInstructionEvent represents state changes of instructions that
 // listeners might be interested in. Listeners can choose to ignore any event
 // they are not interested in.
 class HWInstructionEvent {
 public:
   // This is the list of event types that are shared by all targets, that
virtual void onReleasedBuffers(const InstRef &Inst,
                                  llvm::ArrayRef<unsigned> Buffers) {}
 
   virtual ~HWEventListener() {}
 
 private:
   virtual void anchor();
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/include/HardwareUnits/HardwareUnit.h

 /// This file defines a base class for describing a simulated hardware
 /// unit.  These units are used to construct a simulated backend.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_HARDWAREUNIT_H
 #define LLVM_TOOLS_LLVM_MCA_HARDWAREUNIT_H
 
+namespace llvm {
 namespace mca {
 
 class HardwareUnit {
   HardwareUnit(const HardwareUnit &H) = delete;
   HardwareUnit &operator=(const HardwareUnit &H) = delete;
 
 public:
   HardwareUnit() = default;
   virtual ~HardwareUnit();
 };
 
 } // namespace mca
+} // namespace llvm
 #endif // LLVM_TOOLS_LLVM_MCA_HARDWAREUNIT_H

tools/llvm-mca/include/HardwareUnits/LSUnit.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_LSUNIT_H
 #define LLVM_TOOLS_LLVM_MCA_LSUNIT_H
 
 #include "HardwareUnits/HardwareUnit.h"
 #include <set>
 
+namespace llvm {
 namespace mca {
 
 class InstRef;
 
 /// A Load/Store Unit implementing a load and store queues.
 ///
 /// This class implements a load queue and a store queue to emulate the
 /// out-of-order execution of memory operations.
#endif
   // 4. A store may not pass a previous load (regardless of flag 'NoAlias').
   // 5. A load has to wait until an older load barrier is fully executed.
   // 6. A store has to wait until an older store barrier is fully executed.
   virtual bool isReady(const InstRef &IR) const;
   void onInstructionExecuted(const InstRef &IR);
 };
 
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/include/HardwareUnits/RegisterFile.h

 
 #include "HardwareUnits/HardwareUnit.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/Support/Error.h"
 
+namespace llvm {
 namespace mca {
 
 class ReadState;
 class WriteState;
 class WriteRef;
 
 /// Manages hardware register files, and tracks register definitions for
 /// register renaming purposes.
public:
   void cycleStart();
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_REGISTER_FILE_H

tools/llvm-mca/include/HardwareUnits/ResourceManager.h

 
 #include "Instruction.h"
 #include "Support.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
 
+namespace llvm {
 namespace mca {
 
 /// Used to notify the internal state of a processor resource.
 ///
 /// A processor resource is available if it is not reserved, and there are
 /// available slots in the buffer.  A processor resource is unavailable if it
 /// is either reserved, or the associated buffer is full. A processor resource
 /// with a buffer size of -1 is always available if it is not reserved.

 #ifndef NDEBUG
   void dump() const {
     for (const std::unique_ptr<ResourceState> &Resource : Resources)
       Resource->dump();
   }
 #endif
 };
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_RESOURCE_MANAGER_H

tools/llvm-mca/include/HardwareUnits/RetireControlUnit.h

 #ifndef LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H
 #define LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H
 
 #include "HardwareUnits/HardwareUnit.h"
 #include "Instruction.h"
 #include "llvm/MC/MCSchedule.h"
 #include <vector>
 
+namespace llvm {
 namespace mca {
 
 /// This class tracks which instructions are in-flight (i.e., dispatched but not
 /// retired) in the OoO backend.
 //
 /// This class checks on every cycle if/which instructions can be retired.
 /// Instructions are retired in program order.
 /// In the event of an instruction being retired, the pipeline that owns
public:
   void onInstructionExecuted(unsigned TokenID);
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H

tools/llvm-mca/include/HardwareUnits/Scheduler.h

 
 #include "HardwareUnits/HardwareUnit.h"
 #include "HardwareUnits/LSUnit.h"
 #include "ResourceManager.h"
 #include "Support.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
 
+namespace llvm {
 namespace mca {
 
 class SchedulerStrategy {
 public:
   SchedulerStrategy() = default;
   virtual ~SchedulerStrategy();
 
   /// Returns true if Lhs should take priority over Rhs.
#ifndef NDEBUG
   void sanityCheck(const InstRef &IR) const {
     assert(llvm::find(WaitSet, IR) == WaitSet.end());
     assert(llvm::find(ReadySet, IR) == ReadySet.end());
     assert(llvm::find(IssuedSet, IR) == IssuedSet.end());
   }
 #endif // !NDEBUG
 };
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_SCHEDULER_H

tools/llvm-mca/include/InstrBuilder.h

 #include "Support.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Error.h"
 
+namespace llvm {
 namespace mca {
 
 /// A builder class that knows how to construct Instruction objects.
 ///
 /// Every llvm-mca Instruction is described by an object of class InstrDesc.
 /// An InstrDesc describes which registers are read/written by the instruction,
 /// as well as the instruction latency and hardware resources consumed.
 ///
public:
   }
 
   void clear() { VariantDescriptors.shrink_and_clear(); }
 
   llvm::Expected<std::unique_ptr<Instruction>>
   createInstruction(const llvm::MCInst &MCI);
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/include/Instruction.h

 #ifndef NDEBUG
 #include "llvm/Support/raw_ostream.h"
 #endif
 
 #include <memory>
 #include <set>
 #include <vector>
 
+namespace llvm {
 namespace mca {
 
 constexpr int UNKNOWN_CYCLES = -512;
 
 /// A register write descriptor.
 struct WriteDescriptor {
   // Operand index. The index is negative for implicit writes only.
   // For implicit writes, the actual operand index is computed performing
public:
   bool operator==(const WriteRef &Other) const { return Data == Other.Data; }
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/include/Pipeline.h

 #ifndef LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 #define LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 
 #include "HardwareUnits/Scheduler.h"
 #include "Stages/Stage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Error.h"
 
+namespace llvm {
 namespace mca {
 
 class HWEventListener;
 
 /// A pipeline for a specific subtarget.
 ///
 /// It emulates an out-of-order execution of instructions. Instructions are
 /// fetched from a MCInst sequence managed by an initial 'Fetch' stage.

 
 public:
   Pipeline() : Cycles(0) {}
   void appendStage(std::unique_ptr<Stage> S);
   llvm::Error run();
   void addEventListener(HWEventListener *Listener);
 };
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_PIPELINE_H

tools/llvm-mca/include/SourceMgr.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_SOURCEMGR_H
 #define LLVM_TOOLS_LLVM_MCA_SOURCEMGR_H
 
 #include "llvm/MC/MCInst.h"
 #include <vector>
 
+namespace llvm {
 namespace mca {
 
 typedef std::pair<unsigned, const llvm::MCInst *> SourceRef;
 
 class SourceMgr {
   using InstVec = std::vector<std::unique_ptr<const llvm::MCInst>>;
   const InstVec &Sequence;
   unsigned Current;
public:
 
   const llvm::MCInst &getMCInstFromIndex(unsigned Index) const {
     return *Sequence[Index % size()];
   }
 
   bool isEmpty() const { return size() == 0; }
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/include/Stages/DispatchStage.h

 #include "HWEventListener.h"
 #include "HardwareUnits/RegisterFile.h"
 #include "HardwareUnits/RetireControlUnit.h"
 #include "Instruction.h"
 #include "Stages/Stage.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
+namespace llvm {
 namespace mca {
 
 // Implements the hardware dispatch logic.
 //
 // This class is responsible for the dispatch stage, in which instructions are
 // dispatched in groups to the Scheduler.  An instruction can be dispatched if
 // the following conditions are met:
 //  1) There are enough entries in the reorder buffer (see class
public:
   llvm::Error cycleStart() override;
   llvm::Error execute(InstRef &IR) override;
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H

tools/llvm-mca/include/Stages/ExecuteStage.h

 #ifndef LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H
 
 #include "HardwareUnits/Scheduler.h"
 #include "Instruction.h"
 #include "Stages/Stage.h"
 #include "llvm/ADT/ArrayRef.h"
 
+namespace llvm {
 namespace mca {
 
 class ExecuteStage final : public Stage {
   Scheduler &HWS;
 
   llvm::Error issueInstruction(InstRef &IR);
 
   // Called at the beginning of each cycle to issue already dispatched
public:
   void notifyInstructionReady(const InstRef &IR) const;
   void notifyResourceAvailable(const ResourceRef &RR) const;
 
   // Notify listeners that buffered resources have been consumed or freed.
   void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
 };
 
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_EXECUTE_STAGE_H

tools/llvm-mca/include/Stages/FetchStage.h

 #ifndef LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
 
 #include "InstrBuilder.h"
 #include "SourceMgr.h"
 #include "Stages/Stage.h"
 #include <map>
 
+namespace llvm {
 namespace mca {
 
 class FetchStage final : public Stage {
   std::unique_ptr<Instruction> CurrentInstruction;
   using InstMap = std::map<unsigned, std::unique_ptr<Instruction>>;
   InstMap Instructions;
   InstrBuilder &IB;
   SourceMgr &SM;
public:
   bool isAvailable(const InstRef &IR) const override;
   bool hasWorkToComplete() const override;
   llvm::Error execute(InstRef &IR) override;
   llvm::Error cycleStart() override;
   llvm::Error cycleEnd() override;
 };
 
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H

tools/llvm-mca/include/Stages/InstructionTables.h

 #define LLVM_TOOLS_LLVM_MCA_INSTRUCTIONTABLES_H
 
 #include "HardwareUnits/Scheduler.h"
 #include "InstrBuilder.h"
 #include "Stages/Stage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
 
+namespace llvm {
 namespace mca {
 
 class InstructionTables final : public Stage {
   const llvm::MCSchedModel &SM;
   InstrBuilder &IB;
   llvm::SmallVector<std::pair<ResourceRef, ResourceCycles>, 4> UsedResources;
 
 public:
   InstructionTables(const llvm::MCSchedModel &Model, InstrBuilder &Builder)
       : Stage(), SM(Model), IB(Builder) {}
 
   bool hasWorkToComplete() const override { return false; }
   llvm::Error execute(InstRef &IR) override;
 };
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/include/Stages/RetireStage.h

 
 #ifndef LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
 
 #include "HardwareUnits/RegisterFile.h"
 #include "HardwareUnits/RetireControlUnit.h"
 #include "Stages/Stage.h"
 
+namespace llvm {
 namespace mca {
 
 class RetireStage final : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
   RetireControlUnit &RCU;
   RegisterFile &PRF;
 
   RetireStage(const RetireStage &Other) = delete;
   RetireStage &operator=(const RetireStage &Other) = delete;
 
 public:
   RetireStage(RetireControlUnit &R, RegisterFile &F)
       : Stage(), RCU(R), PRF(F) {}
 
   bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
   llvm::Error cycleStart() override;
   llvm::Error execute(InstRef &IR) override;
   void notifyInstructionRetired(const InstRef &IR) const;
 };
 
 } // namespace mca
+} // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H

tools/llvm-mca/include/Stages/Stage.h

 
 #ifndef LLVM_TOOLS_LLVM_MCA_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_STAGE_H
 
 #include "HWEventListener.h"
 #include "llvm/Support/Error.h"
 #include <set>
 
+namespace llvm {
 namespace mca {
 
 class InstRef;
 
 class Stage {
   Stage *NextInSequence;
   std::set<HWEventListener *> Listeners;
 
public:
   /// Notify listeners of a particular hardware event.
   template <typename EventT> void notifyEvent(const EventT &Event) const {
     for (HWEventListener *Listener : Listeners)
       Listener->onEvent(Event);
   }
 };
 
 } // namespace mca
+} // namespace llvm
 #endif // LLVM_TOOLS_LLVM_MCA_STAGE_H

tools/llvm-mca/include/Support.h

 
 #ifndef LLVM_TOOLS_LLVM_MCA_SUPPORT_H
 #define LLVM_TOOLS_LLVM_MCA_SUPPORT_H
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSchedule.h"
 
+namespace llvm {
 namespace mca {
 
 /// This class represents the number of cycles per resource (fractions of
 /// cycles).  That quantity is managed here as a ratio, and accessed via the
 /// double cast-operator below.  The two quantities, number of cycles and
 /// number of resources, are kept separate.  This is used by the
 /// ResourcePressureView to calculate the average resource cycles
 /// per instruction/iteration.

 /// Compute the reciprocal block throughput from a set of processor resource
 /// cycles. The reciprocal block throughput is computed as the MAX between:
 ///  - NumMicroOps / DispatchWidth
 ///  - ProcResourceCycles / #ProcResourceUnits  (for every consumed resource).
 double computeBlockRThroughput(const llvm::MCSchedModel &SM,
                                unsigned DispatchWidth, unsigned NumMicroOps,
                                llvm::ArrayRef<unsigned> ProcResourceUsage);
 } // namespace mca
+} // namespace llvm
 
 #endif

tools/llvm-mca/lib/Context.cpp

 #include "HardwareUnits/RegisterFile.h"
 #include "HardwareUnits/RetireControlUnit.h"
 #include "HardwareUnits/Scheduler.h"
 #include "Stages/DispatchStage.h"
 #include "Stages/ExecuteStage.h"
 #include "Stages/FetchStage.h"
 #include "Stages/RetireStage.h"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 std::unique_ptr<Pipeline>
 Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
                                SourceMgr &SrcMgr) {
   const MCSchedModel &SM = STI.getSchedModel();
 
   // Create the hardware units defining the backend.
   auto RCU = llvm::make_unique<RetireControlUnit>(SM);
   auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
   StagePipeline->appendStage(std::move(Fetch));
   StagePipeline->appendStage(std::move(Dispatch));
   StagePipeline->appendStage(std::move(Execute));
   StagePipeline->appendStage(std::move(Retire));
   return StagePipeline;
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/HWEventListener.cpp

 //===----------------------- HWEventListener.cpp ----------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file defines a vtable anchor for class HWEventListener.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "HWEventListener.h"
 
+namespace llvm {
 namespace mca {
 
 // Anchor the vtable here.
 void HWEventListener::anchor() {}
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/HardwareUnits/HardwareUnit.cpp

 ///
 /// This file defines the anchor for the base class that describes
 /// simulated hardware units.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "HardwareUnits/HardwareUnit.h"
 
+namespace llvm {
 namespace mca {
 
 // Pin the vtable with this method.
 HardwareUnit::~HardwareUnit() = default;
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/HardwareUnits/LSUnit.cpp

 ///
 //===----------------------------------------------------------------------===//
 
 #include "HardwareUnits/LSUnit.h"
 #include "Instruction.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
-using namespace llvm;
-
 #define DEBUG_TYPE "llvm-mca"
 
+namespace llvm {
 namespace mca {
 
 #ifndef NDEBUG
 void LSUnit::dump() const {
   dbgs() << "[LSUnit] LQ_Size = " << LQ_Size << '\n';
   dbgs() << "[LSUnit] SQ_Size = " << SQ_Size << '\n';
   dbgs() << "[LSUnit] NextLQSlotIdx = " << LoadQueue.size() << '\n';
   dbgs() << "[LSUnit] NextSQSlotIdx = " << StoreQueue.size() << '\n';
void LSUnit::onInstructionExecuted(const InstRef &IR) {
   }
   if (!LoadBarriers.empty() && Index == *LoadBarriers.begin()) {
     LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << Index
                       << " has been removed from the set of load barriers.\n");
     LoadBarriers.erase(LoadBarriers.begin());
   }
 }
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp

 /// between registers.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "HardwareUnits/RegisterFile.h"
 #include "Instruction.h"
 #include "llvm/Support/Debug.h"
 
-using namespace llvm;
-
 #define DEBUG_TYPE "llvm-mca"
 
+namespace llvm {
 namespace mca {
 
 RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
                            unsigned NumRegs)
     : MRI(mri),
       RegisterMappings(mri.getNumRegs(), {WriteRef(), RegisterRenamingInfo()}),
       ZeroRegisters(mri.getNumRegs(), false) {
   initialize(SM, NumRegs);
for (unsigned I = 0, E = getNumRegisterFiles(); I < E; ++I) {
     const RegisterMappingTracker &RMT = RegisterFiles[I];
     dbgs() << "\n  TotalMappings:        " << RMT.NumPhysRegs
            << "\n  NumUsedMappings:      " << RMT.NumUsedPhysRegs << '\n';
   }
 }
 #endif
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp

 ///
 //===----------------------------------------------------------------------===//
 
 #include "HardwareUnits/ResourceManager.h"
 #include "Support.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 #define DEBUG_TYPE "llvm-mca"
 ResourceStrategy::~ResourceStrategy() = default;
 
 void DefaultResourceStrategy::skipMask(uint64_t Mask) {
   NextInSequenceMask &= (~Mask);
   if (!NextInSequenceMask) {
     NextInSequenceMask = ResourceUnitMask ^ RemovedFromNextInSequence;
     RemovedFromNextInSequence = 0;

 }
 
 void ResourceManager::releaseResource(uint64_t ResourceID) {
   ResourceState &Resource = *Resources[getResourceStateIndex(ResourceID)];
   Resource.clearReserved();
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp

 ///
 /// This file simulates the hardware responsible for retiring instructions.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "HardwareUnits/RetireControlUnit.h"
 #include "llvm/Support/Debug.h"
 
-using namespace llvm;
-
 #define DEBUG_TYPE "llvm-mca"
 
+namespace llvm {
 namespace mca {
 
 RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
     : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
       AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0) {
   // Check if the scheduling model provides extra information about the machine
   // processor. If so, then use that information to set the reorder buffer size
   // and the maximum number of instructions retired per cycle.

 #ifndef NDEBUG
 void RetireControlUnit::dump() const {
   dbgs() << "Retire Unit: { Total Slots=" << Queue.size()
          << ", Available Slots=" << AvailableSlots << " }\n";
 }
 #endif
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp

 // A scheduler for processor resource units and processor resource groups.
 //
 //===----------------------------------------------------------------------===//
 
 #include "HardwareUnits/Scheduler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 #define DEBUG_TYPE "llvm-mca"
 
 void Scheduler::initializeStrategy(std::unique_ptr<SchedulerStrategy> S) {
   // Ensure we have a valid (non-null) strategy object.
   Strategy = S ? std::move(S) : llvm::make_unique<DefaultSchedulerStrategy>();
 }
 
 // Anchor the vtable of SchedulerStrategy and DefaultSchedulerStrategy.

 
 bool Scheduler::isReady(const InstRef &IR) const {
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   bool IsMemOp = Desc.MayLoad || Desc.MayStore;
   return IR.getInstruction()->isReady() && (!IsMemOp || LSU->isReady(IR));
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/InstrBuilder.cpp

 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/WithColor.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 static void initializeUsedResources(InstrDesc &ID,
                                     const MCSchedClassDesc &SCDesc,
                                     const MCSubtargetInfo &STI,
                                     ArrayRef<uint64_t> ProcResourceMasks) {
   const MCSchedModel &SM = STI.getSchedModel();
 
   // Populate resources consumed.
   using ResourcePlusCycles = std::pair<uint64_t, ResourceUsage>;
NewIS->getDefs().emplace_back(llvm::make_unique<WriteState>(
         WD, RegID, /* ClearsSuperRegs */ WriteMask[WriteIndex],
         /* WritesZero */ IsZeroIdiom));
     ++WriteIndex;
   }
 
   return std::move(NewIS);
 }
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/Instruction.cpp

 // register writes and instructions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "Instruction.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 void ReadState::writeStartEvent(unsigned Cycles) {
   assert(DependentWrites);
   assert(CyclesLeft == UNKNOWN_CYCLES);
 
   // This read may be dependent on more than one write. This typically occurs
   // when a definition is the result of multiple writes where at least one
   // write does a partial register update.
   // The HW is forced to do some extra bookkeeping to track of all the
void Instruction::cycleEvent() {
   CyclesLeft--;
   if (!CyclesLeft)
     Stage = IS_EXECUTED;
 }
 
 const unsigned WriteRef::INVALID_IID = std::numeric_limits<unsigned>::max();
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/Pipeline.cpp

 /// pipeline of a hardware backend.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Pipeline.h"
 #include "HWEventListener.h"
 #include "llvm/Support/Debug.h"
 
+namespace llvm {
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 
-using namespace llvm;
-
 void Pipeline::addEventListener(HWEventListener *Listener) {
   if (Listener)
     Listeners.insert(Listener);
   for (auto &S : Stages)
     S->addListener(Listener);
 }
 
 bool Pipeline::hasWorkToProcess() {

 }
 
 void Pipeline::notifyCycleEnd() {
   LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n\n");
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleEnd();
 }
 } // namespace mca.
+} // namespace llvm

tools/llvm-mca/lib/Stages/DispatchStage.cpp

 ///
 //===----------------------------------------------------------------------===//
 
 #include "Stages/DispatchStage.h"
 #include "HWEventListener.h"
 #include "HardwareUnits/Scheduler.h"
 #include "llvm/Support/Debug.h"
 
-using namespace llvm;
-
 #define DEBUG_TYPE "llvm-mca"
 
+namespace llvm {
 namespace mca {
 
 void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
                                                 ArrayRef<unsigned> UsedRegs,
                                                 unsigned UOps) const {
   LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: #" << IR << '\n');
   notifyEvent<HWInstructionEvent>(
       HWInstructionDispatchedEvent(IR, UsedRegs, UOps));

 
 #ifndef NDEBUG
 void DispatchStage::dump() const {
   PRF.dump();
   RCU.dump();
 }
 #endif
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/Stages/ExecuteStage.cpp

 //===----------------------------------------------------------------------===//
 
 #include "Stages/ExecuteStage.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 HWStallEvent::GenericEventType toHWStallEventType(Scheduler::Status Status) {
   switch (Status) {
   case Scheduler::SC_LOAD_QUEUE_FULL:
     return HWStallEvent::LoadQueueFull;
   case Scheduler::SC_STORE_QUEUE_FULL:
     return HWStallEvent::StoreQueueFull;
   case Scheduler::SC_BUFFERS_FULL:
     return HWStallEvent::SchedulerQueueFull;
if (Reserved) {
     return;
   }
 
   for (HWEventListener *Listener : getListeners())
     Listener->onReleasedBuffers(IR, BufferIDs);
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/Stages/FetchStage.cpp

 ///
 /// This file defines the Fetch stage of an instruction pipeline.  Its sole
 /// purpose in life is to produce instructions for the rest of the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Stages/FetchStage.h"
 
+namespace llvm {
 namespace mca {
 
 bool FetchStage::hasWorkToComplete() const {
   return CurrentInstruction.get() || SM.hasNext();
 }
 
 bool FetchStage::isAvailable(const InstRef & /* unused */) const {
   if (!CurrentInstruction)
llvm::Error FetchStage::cycleEnd() {
   // Erase instructions up to the first that hasn't been retired.
   if (It != Instructions.begin())
     Instructions.erase(Instructions.begin(), It);
 
   return llvm::ErrorSuccess();
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/Stages/InstructionTables.cpp

 /// Method execute() prints a theoretical resource pressure distribution based
 /// on the information available in the scheduling model, and without running
 /// the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Stages/InstructionTables.h"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 Error InstructionTables::execute(InstRef &IR) {
   ArrayRef<uint64_t> Masks = IB.getProcResourceMasks();
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   UsedResources.clear();
 
   // Identify the resources consumed by this instruction.
   for (const std::pair<uint64_t, ResourceUsage> Resource : Desc.Resources) {
     // Skip zero-cycle resources (i.e., unused resources).
Error InstructionTables::execute(InstRef &IR) {
 
   // Send a fake instruction issued event to all the views.
   HWInstructionIssuedEvent Event(IR, UsedResources);
   notifyEvent<HWInstructionIssuedEvent>(Event);
   return ErrorSuccess();
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/Stages/RetireStage.cpp

 //===----------------------------------------------------------------------===//
 
 #include "Stages/RetireStage.h"
 #include "HWEventListener.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
+namespace llvm {
 namespace mca {
 
 llvm::Error RetireStage::cycleStart() {
   if (RCU.isEmpty())
     return llvm::ErrorSuccess();
 
   const unsigned MaxRetirePerCycle = RCU.getMaxRetirePerCycle();
   unsigned NumRetired = 0;
void RetireStage::notifyInstructionRetired(const InstRef &IR) const {
   const Instruction &Inst = *IR.getInstruction();
 
   for (const std::unique_ptr<WriteState> &WS : Inst.getDefs())
     PRF.removeRegisterWrite(*WS.get(), FreedRegs);
   notifyEvent<HWInstructionEvent>(HWInstructionRetiredEvent(IR, FreedRegs));
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/Stages/Stage.cpp

 ///
 /// This file defines a stage.
 /// A chain of stages compose an instruction pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Stages/Stage.h"
 
+namespace llvm {
 namespace mca {
 
 // Pin the vtable here in the implementation file.
 Stage::~Stage() = default;
 
 void Stage::addListener(HWEventListener *Listener) {
   Listeners.insert(Listener);
 }
 
 } // namespace mca
+} // namespace llvm

tools/llvm-mca/lib/Support.cpp

 /// This file implements a few helper functions used by various pipeline
 /// components.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Support.h"
 #include "llvm/MC/MCSchedule.h"
 
+namespace llvm {
 namespace mca {
 
-using namespace llvm;
-
 void computeProcResourceMasks(const MCSchedModel &SM,
                               SmallVectorImpl<uint64_t> &Masks) {
   unsigned ProcResourceID = 0;
 
   // Create a unique bitmask for every processor resource unit.
   // Skip resource at index 0, since it always references 'InvalidUnit'.
   Masks.resize(SM.getNumProcResourceKinds());
   for (unsigned I = 1, E = SM.getNumProcResourceKinds(); I < E; ++I) {
double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
 
   // The block reciprocal throughput is computed as the MAX of:
   //  - (NumMicroOps / DispatchWidth)
   //  - (NumUnits / ResourceCycles)   for every consumed processor resource.
   return Max;
 }
 
 } // namespace mca
+} // namespace llvm