[ARM] Do not fuse VADD and VMUL, continued (2/2)

[SjoerdMeijer]

Summary

This is patch 2/2, following up on D53314, to prevent fusing of mul + add sequences.

[samparker]

test/CodeGen/ARM/fusedMAC.ll

10

should the f64 version not also be tested?

[SjoerdMeijer]

should the f64 version not also be tested?

Both the M4 and M33 have only Single-Precision VFP support. Thus f64 operations result in EABI calls and so I don't think there's much to test here. I have cleaned up the RUN line in the test case though as we only need the -mcpu=cortex-m33 part and not the other attributes.

[samparker]

Good point. Would it be worth adding a test for the M7 though? We seem to be a little lacking in our m-class FP tests.

test/CodeGen/ARM/fusedMAC.ll

2

this is a funny looking triple for the M33

[SjoerdMeijer]

Would it be worth adding a test for the M7 though? We seem to be a little lacking in our m-class FP tests.

Yep, agreed. Added tests for the M7 and M4.

this is a funny looking triple for the M33

Oops, copy-paste, but now fixed.

[samparker]

Thanks, LGTM. With one bonus question, are the fused operations fast on the M7..?

[SjoerdMeijer]

Cheers

With one bonus question, are the fused operations fast on the M7..?

:-)

From a first glance, it looks like we should give the M7 a similar treatment.
But I will double check, also run benchmarks, and will follow-up if necessary (which, again, looks very likely).

lib/Target/ARM/ARMInstrInfo.td

let RecomputePerFunction = 1 in {
 
   def UseFPVMLx: Predicate<"((Subtarget->useFPVMLx() &&"
                            " !TM.Options.AllowFPOpFusion == FPOpFusion::Fast) ||"
                            "MF->getFunction().optForMinSize())">;
 }
 def UseMulOps        : Predicate<"Subtarget->useMulOps()">;
 
 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
-// But only select them if more precision in FP computation is allowed.
+// But only select them if more precision in FP computation is allowed, and when
+// they are not slower than a mul + add sequence.
 // Do not use them for Darwin platforms.
 def UseFusedMAC      : Predicate<"(TM.Options.AllowFPOpFusion =="
                                  " FPOpFusion::Fast && "
                                  " Subtarget->hasVFP4()) && "
-                                 "!Subtarget->isTargetDarwin()">;
+                                 "!Subtarget->isTargetDarwin() &&"
+                                 "Subtarget->useFPVMLx()">;
 
 def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">;
 def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">;
 
 def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">;
 def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">;
 
 def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||"

test/CodeGen/ARM/fusedMAC.ll

 ; RUN: llc < %s -mtriple=armv7-eabi -mattr=+neon,+vfp4 -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mtriple=arm-arm-eabi -mcpu=cortex-m7  -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mtriple=arm-arm-eabi -mcpu=cortex-m4  -fp-contract=fast | FileCheck %s -check-prefix=DONT-FUSE
+; RUN: llc < %s -mtriple=arm-arm-eabi -mcpu=cortex-m33 -fp-contract=fast | FileCheck %s -check-prefix=DONT-FUSE
+
 ; Check generated fused MAC and MLS.
 
 define double @fusedMACTest1(double %d1, double %d2, double %d3) {
 ;CHECK-LABEL: fusedMACTest1:
 ;CHECK: vfma.f64
   %1 = fmul double %d1, %d2
   %2 = fadd double %1, %d3
   ret double %2
 }
 
 define float @fusedMACTest2(float %f1, float %f2, float %f3) {
 ;CHECK-LABEL: fusedMACTest2:
 ;CHECK: vfma.f32
+
+;DONT-FUSE-LABEL: fusedMACTest2:
+;DONT-FUSE:       vmul.f32
+;DONT-FUSE-NEXT:  vadd.f32
+
   %1 = fmul float %f1, %f2
   %2 = fadd float %1, %f3
   ret float %2
 }
 
 define double @fusedMACTest3(double %d1, double %d2, double %d3) {
 ;CHECK-LABEL: fusedMACTest3:
 ;CHECK: vfms.f64