[tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen.

[andreadb]

Summary

This patch adds the ability to identify instructions that are "move elimination candidates". It also allows scheduling models to describe processor register files that allow move elimination.

A move elimination candidate is an instruction that can be eliminated at register renaming stage.
Each subtarget can specify which instructions are move elimination candidates with the help of tablegen class "IsOptimizableMoveFunction" (see llvm/Target/TargetInstrPredicate.td).

For example, on X86, BtVer2 allows MMX/SSE moves to be eliminated only if source and destination are not the same register. The definition of 'IsOptimizableMoveFunction' for BtVer2 looks like this:

def : IsOptimizableMoveFunction<[
  InstructionEquivalenceClass<[
    // MMX variants.
    MMX_MOVQ64rr,

    // SSE variants.
    MOVAPSrr, MOVUPSrr,
    MOVAPDrr, MOVUPDrr,
    MOVDQArr, MOVDQUrr,

    // AVX variants.
    VMOVAPSrr, VMOVUPSrr,
    VMOVAPDrr, VMOVUPDrr,
    VMOVDQArr, VMOVDQUrr
  ], CheckNot<CheckSameRegOperand<0, 1>> >
]>;

Definitions of IsOptimizableMoveFunction from different processors of a same Target are used by the SubtargetEmitter to auto-generate target-specific overrides for the following predicate methods:

bool TargetSubtargetInfo::isOptimizableRegisterMove(const MachineInstr *MI) const;
bool MCInstrAnalysis::isOptimizableRegisterMove(const MCInst &MI, unsigned CPUID) const;

By default, those methods return false (i.e. no move elimination is allowed by the subtarget).

Tablegen class RegisterFile has been extended with the following information:

• The set of register classes that allow move elimination.
• Maxium number of moves that can be eliminated every cycle.
• Whether move elimination is restricted to moves from registers that are known to be zero.

This patch is structured in three part:

A first part (which is mostly boilerplate) adds the new 'isOptimizableRegisterMove' target hooks, and extends existing register file descriptors in MC by introducing new fields to describe properties related to move elimination.

A second part, uses the new tablegen constructs to describe move elimination in the BtVer2 scheduling model.

A third part, teaches llm-mca how to query the new 'isOptimizableRegisterMove' hook to mark instructions that are candidates for move elimination. It also teaches class RegisterFile how to describe constraints on move elimination at PRF granularity.

llvm-mca tests for btver2 show differences before/after this patch.

Please let me know if okay to commit.

Thanks,
Andrea

[andreadb]

Patch updated:

It turns out that on Btver2, same register moves can also be optimized at register renaming stage. I verified this with perf. Also, GPR zero moves can be optimized too. Thanks @RKSimon for pointing this out.

[mattd]

This LGTM! I didn't have much to say, your descriptions were clear, and from what I can tell the changes look good.

include/llvm/Target/TargetSchedule.td

463

nit: Add a period to the end of this line.

515

s/ther/there/

527

nit: Add a period to the end of this line.

[mattd]

I've accepted the patch, but it would be good to get others feedback before landing this.

[RKSimon]

include/llvm/CodeGen/TargetSubtargetInfo.h

176

Any reason why we don't reuse the name isOptimizableRegisterMove?

[andreadb]

include/llvm/CodeGen/TargetSubtargetInfo.h

176

No reason... I am happy to change the name of that class to "IsOptimizableRegisterMove".

include/llvm/Target/TargetSchedule.td

463

Will do.

515

Will do.

527

Will do.

[RKSimon]

LGTM - apart from 2 different names for the same thing and @mattd's minors

include/llvm/CodeGen/TargetSubtargetInfo.h

public:
   /// all dependency breaking instructions (i.e. not just zero-idioms).
   /// 
   /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies.
   /// (See method `isZeroIdiom` for a detailed description of Mask).
   virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
     return isZeroIdiom(MI, Mask);
   }
 
+  /// Returns true if MI is a candidate for move elimination.
+  ///
+  /// A candidate for move elimination may be optimized out at register renaming
+  /// stage. Subtargets can specify the set of optimizable moves by
+  /// instantiating tablegen class `IsOptimizableMoveFunction` (see
+  /// llvm/Target/TargetInstrPredicate.td).
+  ///
+  /// SubtargetEmitter is responsible for processing all the definitions of
+  /// class IsOptimizableMoveFunction, and auto-generate an override for
+  /// this method.
+  virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {
+    return false;
+  }
+
   /// True if the subtarget should run MachineScheduler after aggressive
   /// coalescing.
   ///
   /// This currently replaces the SelectionDAG scheduler with the "source" order
   /// scheduler (though see below for an option to turn this off and use the
   /// TargetLowering preference). It does not yet disable the postRA scheduler.
   virtual bool enableMachineScheduler() const;
 

include/llvm/MC/MCInstrAnalysis.h

public:
   ///
   /// The only exception is for when Mask is all zeroes. That means: explicit
   /// input operands of MI are independent.
   virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask,
                                     unsigned CPUID) const {
     return isZeroIdiom(MI, Mask, CPUID);
   }
 
+  /// Returns true if MI is a candidate for move elimination.
+  ///
+  /// Different subtargets may apply different constraints to optimizable
+  /// register moves. For example, on most X86 subtargets, a candidate for move
+  /// elimination cannot specify the same register for both source and
+  /// destination.
+  virtual bool isOptimizableRegisterMove(const MCInst &MI,
+                                         unsigned CPUID) const {
+    return false;
+  }
+
   /// Given a branch instruction try to get the address the branch
   /// targets. Return true on success, and the address in Target.
   virtual bool
   evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
                  uint64_t &Target) const;
 
   /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
   virtual std::vector<std::pair<uint64_t, uint64_t>>

include/llvm/MC/MCSchedule.h

 /// natively supports 128-bit data types, and operations on 256-bit registers
 /// (i.e. YMM registers) are internally split into two COPs (complex operations)
 /// and each COP updates a physical register. Basically, on Jaguar, a YMM
 /// register write effectively consumes two physical registers. That means,
 /// the cost of a YMM write in the BtVer2 model is 2.
 struct MCRegisterCostEntry {
   unsigned RegisterClassID;
   unsigned Cost;
+  bool AllowMoveElimination;
 };
 
 /// A register file descriptor.
 ///
 /// This struct allows to describe processor register files. In particular, it
 /// helps describing the size of the register file, as well as the cost of
 /// allocating a register file at register renaming stage.
 /// FIXME: this struct can be extended to provide information about the number
 /// of read/write ports to the register file.  A value of zero for field
 /// 'NumPhysRegs' means: this register file has an unbounded number of physical
 /// registers.
 struct MCRegisterFileDesc {
   const char *Name;
   uint16_t NumPhysRegs;
   uint16_t NumRegisterCostEntries;
   // Index of the first cost entry in MCExtraProcessorInfo::RegisterCostTable.
   uint16_t RegisterCostEntryIdx;
+  // A value of zero means: there is no limit in the number of moves that can be
+  // eliminated every cycle.
+  uint16_t MaxMovesEliminatedPerCycle;
+  // Ture if this register file only knows how to optimize register moves from
+  // known zero registers.
+  bool AllowZeroMoveEliminationOnly;
 };
 
 /// Provide extra details about the machine processor.
 ///
 /// This is a collection of "optional" processor information that is not
 /// normally used by the LLVM machine schedulers, but that can be consumed by
 /// external tools like llvm-mca to improve the quality of the peformance
 /// analysis.

include/llvm/Target/TargetInstrPredicate.td

 class STIPredicate<STIPredicateDecl declaration,
                    list<InstructionEquivalenceClass> classes> {
   STIPredicateDecl Declaration = declaration;
   list<InstructionEquivalenceClass> Classes = classes;
   SchedMachineModel SchedModel = ?;
 }
 
 // Convenience classes and definitions used by processor scheduling models to
-// describe dependency breaking instructions.
+// describe dependency breaking instructions and move elimination candidates.
 let UpdatesOpcodeMask = 1 in {
 
 def IsZeroIdiomDecl : STIPredicateDecl<"isZeroIdiom">;
 
 let Delegates = [IsZeroIdiomDecl] in
 def IsDepBreakingDecl : STIPredicateDecl<"isDependencyBreaking">;
 
 } // UpdatesOpcodeMask
 
+def IsOptimizableMoveDecl : STIPredicateDecl<"isOptimizableRegisterMove">;
+
 class IsZeroIdiomFunction<list<DepBreakingClass> classes>
     : STIPredicate<IsZeroIdiomDecl, classes>;
 
 class IsDepBreakingFunction<list<DepBreakingClass> classes>
     : STIPredicate<IsDepBreakingDecl, classes>;
+
+class IsOptimizableMoveFunction<list<InstructionEquivalenceClass> classes>
+    : STIPredicate<IsOptimizableMoveDecl, classes>;

include/llvm/Target/TargetSchedule.td

 // Allow the definition of processor register files for register renaming
 // purposes.
 //
 // Each processor register file declares:
 //  - The set of registers that can be renamed.
 //  - The number of physical registers which can be used for register renaming
 //    purpose.
 //  - The cost of a register rename.
+//  - The set of registers that allow move elimination
+//  - The maximum number of moves that can be eliminated every cycle.
+//  - Whether move elimination is limited to register moves whose input
+//    is known to be zero.
 //
 // The cost of a rename is the number of physical registers allocated by the
 // register alias table to map the new definition. By default, register can be
 // renamed at the cost of a single physical register.  Note that register costs
 // are defined at register class granularity (see field `Costs`).
 //
 // The set of registers that are subject to register renaming is declared using
 // a list of register classes (see field `RegClasses`). An empty list of

 //
 // TODO: we don't currently model merge penalties for the case where a write to
 // a part of a register is followed by a read from a larger part of the same
 // register. On some Intel chips, different parts of a GPR can be stored in
 // different physical registers. However, there is a cost to pay for when the
 // partial write is combined with the previous super-register definition.  We
 // should add support for these cases, and correctly model merge problems with
 // partial register accesses.
+//
+// Field MaxMovesEliminatedPerCycle specifies how many moves can be eliminated
+// every cycle. A default value of zero for that field means: ther is no limit
+// to the number of moves that can be eliminated by this register file.
+//
+// An instruction MI is a candidate for move elimination if a call to
+// method TargetSubtargetInfo::isOptimizableRegisterMove(MI) returns true (see
+// llvm/CodeGen/TargetSubtargetInfo.h, and llvm/MC/MCInstrAnalysis.h).
+//
+// Subtargets can instantiate tablegen class IsOptimizableMoveFunction (see
+// llvm/Target/TargetInstrPredicate.td) to customize the set of move elimination
+// candidates. By default, no instruction is a valid move elimination candidate.
+//
+// A register move MI is eliminated only if:
+//  - MI is a move elimination candidate
+//  - The destination register is from a register class that allows move
+//    elimination (see field `AllowMoveElimination` below).
+//  - Constraints on the move kind, and the maximum number of moves that can be
+//    eliminated per cycle are all met.
+
 class RegisterFile<int numPhysRegs, list<RegisterClass> Classes = [],
-                   list<int> Costs = []> {
+                   list<int> Costs = [], list<bit> AllowMoveElim = [],
+                   int MaxMoveElimPerCy = 0, bit AllowZeroMoveElimOnly = 0> {
   list<RegisterClass> RegClasses = Classes;
   list<int> RegCosts = Costs;
+  list<bit> AllowMoveElimination = AllowMoveElim;
   int NumPhysRegs = numPhysRegs;
+  int MaxMovesEliminatedPerCycle = MaxMoveElimPerCy;
+  bit AllowZeroMoveEliminationOnly = AllowZeroMoveElimOnly;
   SchedMachineModel SchedModel = ?;
 }
 
 // Describe the retire control unit.
 // A retire control unit specifies the size of the reorder buffer, as well as
 // the maximum number of opcodes that can be retired every cycle.
 // A value less-than-or-equal-to zero for field 'ReorderBufferSize' means: "the
 // size is unknown". The idea is that external tools can fall-back to using

lib/Target/X86/X86ScheduleBtVer2.td

 // Reference: www.realworldtech.com/jaguar/4/
 //
 // The processor always keeps the different parts of an integer register
 // together. An instruction that writes to a part of a register will therefore
 // have a false dependence on any previous write to the same register or any
 // part of it.
 // Reference: Section 21.10 "AMD Bobcat and Jaguar pipeline: Partial register
 // access" - Agner Fog's "microarchitecture.pdf".
-def JIntegerPRF : RegisterFile<64, [GR64, CCR]>;
+def JIntegerPRF : RegisterFile<64, [GR64, CCR], [1, 1], [1, 0],
+                               0,  // Max moves that can be eliminated per cycle.
+                               1>; // Restrict move elimination to zero regs.
 
 // The Jaguar FP Retire Queue renames SIMD and FP uOps onto a pool of 72 SSE
 // registers. Operations on 256-bit data types are cracked into two COPs.
 // Reference: www.realworldtech.com/jaguar/4/
-def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>;
+
+// The PRF in the floating point unit can eliminate a move from a MMX or SSE
+// register that is know to be zero (i.e. it has been zeroed using a zero-idiom
+// dependency breaking instruction, or via VZEROALL).
+// Reference: Section 21.8 "AMD Bobcat and Jaguar pipeline: Dependency-breaking
+// instructions" - Agner Fog's "microarchitecture.pdf"
+def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2], [1, 1, 0],
+                          0,  // Max moves that can be eliminated per cycle.
+                          1>; // Restrict move elimination to zero regs.
 
 // The retire control unit (RCU) can track up to 64 macro-ops in-flight. It can
 // retire up to two macro-ops per cycle.
 // Reference: "Software Optimization Guide for AMD Family 16h Processors"
 def JRCU : RetireControlUnit<64, 2>;
 
 // Integer Pipe Scheduler
 def JALU01 : ProcResGroup<[JALU0, JALU1]> {
def : IsDepBreakingFunction<[
   ], ZeroIdiomPredicate>,
 
   // AVX
   DepBreakingClass<[
     VPCMPEQBrr, VPCMPEQWrr, VPCMPEQDrr, VPCMPEQQrr
   ], ZeroIdiomPredicate>
 ]>;
 
+def : IsOptimizableMoveFunction<[
+  InstructionEquivalenceClass<[
+    // GPR variants.
+    MOV32rr, MOV64rr,
+
+    // MMX variants.
+    MMX_MOVQ64rr,
+
+    // SSE variants.
+    MOVAPSrr, MOVUPSrr,
+    MOVAPDrr, MOVUPDrr,
+    MOVDQArr, MOVDQUrr,
+
+    // AVX variants.
+    VMOVAPSrr, VMOVUPSrr,
+    VMOVAPDrr, VMOVUPDrr,
+    VMOVDQArr, VMOVDQUrr
+  ], TruePred >
+]>;
+
 } // SchedModel

test/tools/llvm-mca/X86/BtVer2/reg-move-elimination-1.s

 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      0     0.50                        vxorps  %xmm0, %xmm0, %xmm0
 # CHECK-NEXT:  1      1     0.50                        vmovaps %xmm0, %xmm1
 # CHECK-NEXT:  1      3     1.00                        vaddps  %xmm1, %xmm1, %xmm2
 
 # CHECK:      Register File statistics:
-# CHECK-NEXT: Total number of mappings created:    6
-# CHECK-NEXT: Max number of mappings used:         5
+# CHECK-NEXT: Total number of mappings created:    3
+# CHECK-NEXT: Max number of mappings used:         3
 
 # CHECK:      *  Register File #1 -- JFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     72
-# CHECK-NEXT:    Total number of mappings created: 6
-# CHECK-NEXT:    Max number of mappings used:      5
+# CHECK-NEXT:    Total number of mappings created: 3
+# CHECK-NEXT:    Max number of mappings used:      3
 
 # CHECK:      *  Register File #2 -- JIntegerPRF:
 # CHECK-NEXT:    Number of physical registers:     64
 # CHECK-NEXT:    Total number of mappings created: 0
 # CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - JALU0
 # CHECK-NEXT: [1]   - JALU1
 # CHECK-NEXT: [2]   - JDiv
 # CHECK-NEXT: [3]   - JFPA
 # CHECK-NEXT: [4]   - JFPM
 # CHECK-NEXT: [5]   - JFPU0
 # CHECK-NEXT: [6]   - JFPU1
 # CHECK-NEXT: [7]   - JLAGU
 # CHECK-NEXT: [8]   - JMul
 # CHECK-NEXT: [9]   - JSAGU
 # CHECK-NEXT: [10]  - JSTC
 # CHECK-NEXT: [11]  - JVALU0
 # CHECK-NEXT: [12]  - JVALU1
 # CHECK-NEXT: [13]  - JVIMUL
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]
-# CHECK-NEXT:  -      -      -     1.00   1.00   1.00   1.00    -      -      -      -      -      -      -
+# CHECK-NEXT:  -      -      -     1.00    -     1.00    -      -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     vxorps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT:  -      -      -      -     1.00    -     1.00    -      -      -      -      -      -      -     vmovaps %xmm0, %xmm1
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     vmovaps %xmm0, %xmm1
 # CHECK-NEXT:  -      -      -     1.00    -     1.00    -      -      -      -      -      -      -      -     vaddps  %xmm1, %xmm1, %xmm2
 
 # CHECK:      Timeline view:
 # CHECK-NEXT: Index     0123456789
 
 # CHECK:      [0,0]     DR   .   .   vxorps %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [0,1]     DeER .   .   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [0,1]     DR   .   .   vmovaps  %xmm0, %xmm1
 # CHECK-NEXT: [0,2]     .DeeeER  .   vaddps %xmm1, %xmm1, %xmm2
 # CHECK-NEXT: [1,0]     .D----R  .   vxorps %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [1,1]     . DeE--R .   vmovaps  %xmm0, %xmm1
-# CHECK-NEXT: [1,2]     . D=eeeER.   vaddps %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: [1,1]     . D----R .   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [1,2]     . DeeeER .   vaddps %xmm1, %xmm1, %xmm2
 # CHECK-NEXT: [2,0]     .  D----R.   vxorps %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [2,1]     .  DeE---R   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [2,1]     .  D----R.   vmovaps  %xmm0, %xmm1
 # CHECK-NEXT: [2,2]     .   DeeeER   vaddps %xmm1, %xmm1, %xmm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     0.0    0.0    2.7       vxorps %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: 1.     3     1.0    1.0    1.7       vmovaps  %xmm0, %xmm1
-# CHECK-NEXT: 2.     3     1.3    0.0    0.0       vaddps %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: 1.     3     0.0    0.0    2.7       vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: 2.     3     1.0    1.0    0.0       vaddps %xmm1, %xmm1, %xmm2

test/tools/llvm-mca/X86/BtVer2/reg-move-elimination-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s
 
 pxor %mm0, %mm0
 movq %mm0, %mm1
 
 xorps %xmm0, %xmm0
 movaps %xmm0, %xmm1
 movups %xmm1, %xmm2
 movapd %xmm2, %xmm3
 movupd %xmm3, %xmm4
 movdqa %xmm4, %xmm5
 movdqu %xmm5, %xmm0
 
 # CHECK:      Iterations:        3
 # CHECK-NEXT: Instructions:      27
-# CHECK-NEXT: Total Cycles:      19
+# CHECK-NEXT: Total Cycles:      15
 # CHECK-NEXT: Total uOps:        27
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    1.42
-# CHECK-NEXT: IPC:               1.42
+# CHECK-NEXT: uOps Per Cycle:    1.80
+# CHECK-NEXT: IPC:               1.80
 # CHECK-NEXT: Block RThroughput: 4.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      0     0.50                        pxor  %mm0, %mm0
 # CHECK-NEXT:  1      1     0.50                        movq  %mm0, %mm1
 # CHECK-NEXT:  1      0     0.50                        xorps %xmm0, %xmm0
 # CHECK-NEXT:  1      1     0.50                        movaps  %xmm0, %xmm1
 # CHECK-NEXT:  1      1     0.50                        movups  %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.50                        movapd  %xmm2, %xmm3
 # CHECK-NEXT:  1      1     0.50                        movupd  %xmm3, %xmm4
 # CHECK-NEXT:  1      1     0.50                        movdqa  %xmm4, %xmm5
 # CHECK-NEXT:  1      1     0.50                        movdqu  %xmm5, %xmm0
 
 # CHECK:      Register File statistics:
-# CHECK-NEXT: Total number of mappings created:    21
-# CHECK-NEXT: Max number of mappings used:         8
+# CHECK-NEXT: Total number of mappings created:    0
+# CHECK-NEXT: Max number of mappings used:         0
 
 # CHECK:      *  Register File #1 -- JFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     72
-# CHECK-NEXT:    Total number of mappings created: 21
-# CHECK-NEXT:    Max number of mappings used:      8
+# CHECK-NEXT:    Total number of mappings created: 0
+# CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      *  Register File #2 -- JIntegerPRF:
 # CHECK-NEXT:    Number of physical registers:     64
 # CHECK-NEXT:    Total number of mappings created: 0
 # CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - JALU0
 # CHECK-NEXT: [1]   - JALU1
 # CHECK-NEXT: [2]   - JDiv
 # CHECK-NEXT: [3]   - JFPA
 # CHECK-NEXT: [4]   - JFPM
 # CHECK-NEXT: [5]   - JFPU0
 # CHECK-NEXT: [6]   - JFPU1
 # CHECK-NEXT: [7]   - JLAGU
 # CHECK-NEXT: [8]   - JMul
 # CHECK-NEXT: [9]   - JSAGU
 # CHECK-NEXT: [10]  - JSTC
 # CHECK-NEXT: [11]  - JVALU0
 # CHECK-NEXT: [12]  - JVALU1
 # CHECK-NEXT: [13]  - JVIMUL
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]
-# CHECK-NEXT:  -      -      -     2.00   2.00   3.33   3.67    -      -      -      -     1.33   1.67    -
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     pxor  %mm0, %mm0
-# CHECK-NEXT:  -      -      -      -      -      -     1.00    -      -      -      -      -     1.00    -     movq  %mm0, %mm1
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movq  %mm0, %mm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     xorps %xmm0, %xmm0
-# CHECK-NEXT:  -      -      -      -     1.00   0.33   0.67    -      -      -      -      -      -      -     movaps  %xmm0, %xmm1
-# CHECK-NEXT:  -      -      -     1.00    -     0.33   0.67    -      -      -      -      -      -      -     movups  %xmm1, %xmm2
-# CHECK-NEXT:  -      -      -      -     1.00   0.67   0.33    -      -      -      -      -      -      -     movapd  %xmm2, %xmm3
-# CHECK-NEXT:  -      -      -     1.00    -     0.33   0.67    -      -      -      -      -      -      -     movupd  %xmm3, %xmm4
-# CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -      -      -     1.00    -      -     movdqa  %xmm4, %xmm5
-# CHECK-NEXT:  -      -      -      -      -     0.67   0.33    -      -      -      -     0.33   0.67    -     movdqu  %xmm5, %xmm0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movaps  %xmm0, %xmm1
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movups  %xmm1, %xmm2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movapd  %xmm2, %xmm3
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movupd  %xmm3, %xmm4
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movdqa  %xmm4, %xmm5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movdqu  %xmm5, %xmm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     012345678
+# CHECK-NEXT:                     01234
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DR   .    .    .  .   pxor  %mm0, %mm0
-# CHECK-NEXT: [0,1]     DeER .    .    .  .   movq  %mm0, %mm1
-# CHECK-NEXT: [0,2]     .D-R .    .    .  .   xorps %xmm0, %xmm0
-# CHECK-NEXT: [0,3]     .DeER.    .    .  .   movaps  %xmm0, %xmm1
-# CHECK-NEXT: [0,4]     . DeER    .    .  .   movups  %xmm1, %xmm2
-# CHECK-NEXT: [0,5]     . D=eER   .    .  .   movapd  %xmm2, %xmm3
-# CHECK-NEXT: [0,6]     .  D=eER  .    .  .   movupd  %xmm3, %xmm4
-# CHECK-NEXT: [0,7]     .  D==eER .    .  .   movdqa  %xmm4, %xmm5
-# CHECK-NEXT: [0,8]     .   D==eER.    .  .   movdqu  %xmm5, %xmm0
-# CHECK-NEXT: [1,0]     .   D----R.    .  .   pxor  %mm0, %mm0
-# CHECK-NEXT: [1,1]     .    DeE--R    .  .   movq  %mm0, %mm1
-# CHECK-NEXT: [1,2]     .    D----R    .  .   xorps %xmm0, %xmm0
-# CHECK-NEXT: [1,3]     .    .DeE--R   .  .   movaps  %xmm0, %xmm1
-# CHECK-NEXT: [1,4]     .    .D=eE-R   .  .   movups  %xmm1, %xmm2
-# CHECK-NEXT: [1,5]     .    . D=eE-R  .  .   movapd  %xmm2, %xmm3
-# CHECK-NEXT: [1,6]     .    . D==eER  .  .   movupd  %xmm3, %xmm4
-# CHECK-NEXT: [1,7]     .    .  D==eER .  .   movdqa  %xmm4, %xmm5
-# CHECK-NEXT: [1,8]     .    .  D===eER.  .   movdqu  %xmm5, %xmm0
-# CHECK-NEXT: [2,0]     .    .   D----R.  .   pxor  %mm0, %mm0
-# CHECK-NEXT: [2,1]     .    .   DeE---R  .   movq  %mm0, %mm1
-# CHECK-NEXT: [2,2]     .    .    D----R  .   xorps %xmm0, %xmm0
-# CHECK-NEXT: [2,3]     .    .    DeE---R .   movaps  %xmm0, %xmm1
-# CHECK-NEXT: [2,4]     .    .    .DeE--R .   movups  %xmm1, %xmm2
-# CHECK-NEXT: [2,5]     .    .    .D=eE--R.   movapd  %xmm2, %xmm3
-# CHECK-NEXT: [2,6]     .    .    . D=eE-R.   movupd  %xmm3, %xmm4
-# CHECK-NEXT: [2,7]     .    .    . D==eE-R   movdqa  %xmm4, %xmm5
-# CHECK-NEXT: [2,8]     .    .    .  D==eER   movdqu  %xmm5, %xmm0
+# CHECK:      [0,0]     DR   .    .   .   pxor  %mm0, %mm0
+# CHECK-NEXT: [0,1]     DR   .    .   .   movq  %mm0, %mm1
+# CHECK-NEXT: [0,2]     .DR  .    .   .   xorps %xmm0, %xmm0
+# CHECK-NEXT: [0,3]     .DR  .    .   .   movaps  %xmm0, %xmm1
+# CHECK-NEXT: [0,4]     . DR .    .   .   movups  %xmm1, %xmm2
+# CHECK-NEXT: [0,5]     . DR .    .   .   movapd  %xmm2, %xmm3
+# CHECK-NEXT: [0,6]     .  DR.    .   .   movupd  %xmm3, %xmm4
+# CHECK-NEXT: [0,7]     .  DR.    .   .   movdqa  %xmm4, %xmm5
+# CHECK-NEXT: [0,8]     .   DR    .   .   movdqu  %xmm5, %xmm0
+# CHECK-NEXT: [1,0]     .   DR    .   .   pxor  %mm0, %mm0
+# CHECK-NEXT: [1,1]     .    DR   .   .   movq  %mm0, %mm1
+# CHECK-NEXT: [1,2]     .    DR   .   .   xorps %xmm0, %xmm0
+# CHECK-NEXT: [1,3]     .    .DR  .   .   movaps  %xmm0, %xmm1
+# CHECK-NEXT: [1,4]     .    .DR  .   .   movups  %xmm1, %xmm2
+# CHECK-NEXT: [1,5]     .    . DR .   .   movapd  %xmm2, %xmm3
+# CHECK-NEXT: [1,6]     .    . DR .   .   movupd  %xmm3, %xmm4
+# CHECK-NEXT: [1,7]     .    .  DR.   .   movdqa  %xmm4, %xmm5
+# CHECK-NEXT: [1,8]     .    .  DR.   .   movdqu  %xmm5, %xmm0
+# CHECK-NEXT: [2,0]     .    .   DR   .   pxor  %mm0, %mm0
+# CHECK-NEXT: [2,1]     .    .   DR   .   movq  %mm0, %mm1
+# CHECK-NEXT: [2,2]     .    .    DR  .   xorps %xmm0, %xmm0
+# CHECK-NEXT: [2,3]     .    .    DR  .   movaps  %xmm0, %xmm1
+# CHECK-NEXT: [2,4]     .    .    .DR .   movups  %xmm1, %xmm2
+# CHECK-NEXT: [2,5]     .    .    .DR .   movapd  %xmm2, %xmm3
+# CHECK-NEXT: [2,6]     .    .    . DR.   movupd  %xmm3, %xmm4
+# CHECK-NEXT: [2,7]     .    .    . DR.   movdqa  %xmm4, %xmm5
+# CHECK-NEXT: [2,8]     .    .    .  DR   movdqu  %xmm5, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     0.0    0.0    2.7       pxor %mm0, %mm0
-# CHECK-NEXT: 1.     3     1.0    1.0    1.7       movq %mm0, %mm1
-# CHECK-NEXT: 2.     3     0.0    0.0    3.0       xorps  %xmm0, %xmm0
-# CHECK-NEXT: 3.     3     1.0    1.0    1.7       movaps %xmm0, %xmm1
-# CHECK-NEXT: 4.     3     1.3    0.0    1.0       movups %xmm1, %xmm2
-# CHECK-NEXT: 5.     3     2.0    0.0    1.0       movapd %xmm2, %xmm3
-# CHECK-NEXT: 6.     3     2.3    0.0    0.3       movupd %xmm3, %xmm4
-# CHECK-NEXT: 7.     3     3.0    0.0    0.3       movdqa %xmm4, %xmm5
-# CHECK-NEXT: 8.     3     3.3    0.0    0.0       movdqu %xmm5, %xmm0
+# CHECK-NEXT: 0.     3     0.0    0.0    0.0       pxor %mm0, %mm0
+# CHECK-NEXT: 1.     3     0.0    0.0    0.0       movq %mm0, %mm1
+# CHECK-NEXT: 2.     3     0.0    0.0    0.0       xorps  %xmm0, %xmm0
+# CHECK-NEXT: 3.     3     0.0    0.0    0.0       movaps %xmm0, %xmm1
+# CHECK-NEXT: 4.     3     0.0    0.0    0.0       movups %xmm1, %xmm2
+# CHECK-NEXT: 5.     3     0.0    0.0    0.0       movapd %xmm2, %xmm3
+# CHECK-NEXT: 6.     3     0.0    0.0    0.0       movupd %xmm3, %xmm4
+# CHECK-NEXT: 7.     3     0.0    0.0    0.0       movdqa %xmm4, %xmm5
+# CHECK-NEXT: 8.     3     0.0    0.0    0.0       movdqu %xmm5, %xmm0

test/tools/llvm-mca/X86/BtVer2/reg-move-elimination-3.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s
 
 vxorps  %xmm0, %xmm0, %xmm0
 vmovaps %xmm0, %xmm1
 vmovups %xmm1, %xmm2
 vmovapd %xmm2, %xmm3
 vmovupd %xmm3, %xmm4
 vmovdqa %xmm4, %xmm5
 vmovdqu %xmm5, %xmm0
 
 # CHECK:      Iterations:        3
 # CHECK-NEXT: Instructions:      21
-# CHECK-NEXT: Total Cycles:      16
+# CHECK-NEXT: Total Cycles:      12
 # CHECK-NEXT: Total uOps:        21
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    1.31
-# CHECK-NEXT: IPC:               1.31
+# CHECK-NEXT: uOps Per Cycle:    1.75
+# CHECK-NEXT: IPC:               1.75
 # CHECK-NEXT: Block RThroughput: 3.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      0     0.50                        vxorps  %xmm0, %xmm0, %xmm0
 # CHECK-NEXT:  1      1     0.50                        vmovaps %xmm0, %xmm1
 # CHECK-NEXT:  1      1     0.50                        vmovups %xmm1, %xmm2
 # CHECK-NEXT:  1      1     0.50                        vmovapd %xmm2, %xmm3
 # CHECK-NEXT:  1      1     0.50                        vmovupd %xmm3, %xmm4
 # CHECK-NEXT:  1      1     0.50                        vmovdqa %xmm4, %xmm5
 # CHECK-NEXT:  1      1     0.50                        vmovdqu %xmm5, %xmm0
 
 # CHECK:      Register File statistics:
-# CHECK-NEXT: Total number of mappings created:    18
-# CHECK-NEXT: Max number of mappings used:         9
+# CHECK-NEXT: Total number of mappings created:    0
+# CHECK-NEXT: Max number of mappings used:         0
 
 # CHECK:      *  Register File #1 -- JFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     72
-# CHECK-NEXT:    Total number of mappings created: 18
-# CHECK-NEXT:    Max number of mappings used:      9
+# CHECK-NEXT:    Total number of mappings created: 0
+# CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      *  Register File #2 -- JIntegerPRF:
 # CHECK-NEXT:    Number of physical registers:     64
 # CHECK-NEXT:    Total number of mappings created: 0
 # CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - JALU0
 # CHECK-NEXT: [1]   - JALU1
 # CHECK-NEXT: [2]   - JDiv
 # CHECK-NEXT: [3]   - JFPA
 # CHECK-NEXT: [4]   - JFPM
 # CHECK-NEXT: [5]   - JFPU0
 # CHECK-NEXT: [6]   - JFPU1
 # CHECK-NEXT: [7]   - JLAGU
 # CHECK-NEXT: [8]   - JMul
 # CHECK-NEXT: [9]   - JSAGU
 # CHECK-NEXT: [10]  - JSTC
 # CHECK-NEXT: [11]  - JVALU0
 # CHECK-NEXT: [12]  - JVALU1
 # CHECK-NEXT: [13]  - JVIMUL
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]
-# CHECK-NEXT:  -      -      -     2.00   2.00   3.00   3.00    -      -      -      -     1.00   1.00    -
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     vxorps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT:  -      -      -      -     1.00   0.33   0.67    -      -      -      -      -      -      -     vmovaps %xmm0, %xmm1
-# CHECK-NEXT:  -      -      -     1.00    -     0.67   0.33    -      -      -      -      -      -      -     vmovups %xmm1, %xmm2
-# CHECK-NEXT:  -      -      -      -     1.00    -     1.00    -      -      -      -      -      -      -     vmovapd %xmm2, %xmm3
-# CHECK-NEXT:  -      -      -     1.00    -     1.00    -      -      -      -      -      -      -      -     vmovupd %xmm3, %xmm4
-# CHECK-NEXT:  -      -      -      -      -     0.33   0.67    -      -      -      -      -     1.00    -     vmovdqa %xmm4, %xmm5
-# CHECK-NEXT:  -      -      -      -      -     0.67   0.33    -      -      -      -     1.00    -      -     vmovdqu %xmm5, %xmm0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     vmovaps %xmm0, %xmm1
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     vmovups %xmm1, %xmm2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     vmovapd %xmm2, %xmm3
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     vmovupd %xmm3, %xmm4
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     vmovdqa %xmm4, %xmm5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     vmovdqu %xmm5, %xmm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     012345
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DR   .    .    .   vxorps %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [0,1]     DeER .    .    .   vmovaps  %xmm0, %xmm1
-# CHECK-NEXT: [0,2]     .DeER.    .    .   vmovups  %xmm1, %xmm2
-# CHECK-NEXT: [0,3]     .D=eER    .    .   vmovapd  %xmm2, %xmm3
-# CHECK-NEXT: [0,4]     . D=eER   .    .   vmovupd  %xmm3, %xmm4
-# CHECK-NEXT: [0,5]     . D==eER  .    .   vmovdqa  %xmm4, %xmm5
-# CHECK-NEXT: [0,6]     .  D==eER .    .   vmovdqu  %xmm5, %xmm0
-# CHECK-NEXT: [1,0]     .  D----R .    .   vxorps %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [1,1]     .   DeE--R.    .   vmovaps  %xmm0, %xmm1
-# CHECK-NEXT: [1,2]     .   D=eE-R.    .   vmovups  %xmm1, %xmm2
-# CHECK-NEXT: [1,3]     .    D=eE-R    .   vmovapd  %xmm2, %xmm3
-# CHECK-NEXT: [1,4]     .    D==eER    .   vmovupd  %xmm3, %xmm4
-# CHECK-NEXT: [1,5]     .    .D==eER   .   vmovdqa  %xmm4, %xmm5
-# CHECK-NEXT: [1,6]     .    .D===eER  .   vmovdqu  %xmm5, %xmm0
-# CHECK-NEXT: [2,0]     .    . D----R  .   vxorps %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [2,1]     .    . DeE---R .   vmovaps  %xmm0, %xmm1
-# CHECK-NEXT: [2,2]     .    .  DeE--R .   vmovups  %xmm1, %xmm2
-# CHECK-NEXT: [2,3]     .    .  D=eE--R.   vmovapd  %xmm2, %xmm3
-# CHECK-NEXT: [2,4]     .    .   D=eE-R.   vmovupd  %xmm3, %xmm4
-# CHECK-NEXT: [2,5]     .    .   D==eE-R   vmovdqa  %xmm4, %xmm5
-# CHECK-NEXT: [2,6]     .    .    D==eER   vmovdqu  %xmm5, %xmm0
+# CHECK:      [0,0]     DR   .    ..   vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [0,1]     DR   .    ..   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [0,2]     .DR  .    ..   vmovups  %xmm1, %xmm2
+# CHECK-NEXT: [0,3]     .DR  .    ..   vmovapd  %xmm2, %xmm3
+# CHECK-NEXT: [0,4]     . DR .    ..   vmovupd  %xmm3, %xmm4
+# CHECK-NEXT: [0,5]     . DR .    ..   vmovdqa  %xmm4, %xmm5
+# CHECK-NEXT: [0,6]     .  DR.    ..   vmovdqu  %xmm5, %xmm0
+# CHECK-NEXT: [1,0]     .  DR.    ..   vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [1,1]     .   DR    ..   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [1,2]     .   DR    ..   vmovups  %xmm1, %xmm2
+# CHECK-NEXT: [1,3]     .    DR   ..   vmovapd  %xmm2, %xmm3
+# CHECK-NEXT: [1,4]     .    DR   ..   vmovupd  %xmm3, %xmm4
+# CHECK-NEXT: [1,5]     .    .DR  ..   vmovdqa  %xmm4, %xmm5
+# CHECK-NEXT: [1,6]     .    .DR  ..   vmovdqu  %xmm5, %xmm0
+# CHECK-NEXT: [2,0]     .    . DR ..   vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [2,1]     .    . DR ..   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [2,2]     .    .  DR..   vmovups  %xmm1, %xmm2
+# CHECK-NEXT: [2,3]     .    .  DR..   vmovapd  %xmm2, %xmm3
+# CHECK-NEXT: [2,4]     .    .   DR.   vmovupd  %xmm3, %xmm4
+# CHECK-NEXT: [2,5]     .    .   DR.   vmovdqa  %xmm4, %xmm5
+# CHECK-NEXT: [2,6]     .    .    DR   vmovdqu  %xmm5, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     0.0    0.0    2.7       vxorps %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: 1.     3     1.0    1.0    1.7       vmovaps  %xmm0, %xmm1
-# CHECK-NEXT: 2.     3     1.3    0.0    1.0       vmovups  %xmm1, %xmm2
-# CHECK-NEXT: 3.     3     2.0    0.0    1.0       vmovapd  %xmm2, %xmm3
-# CHECK-NEXT: 4.     3     2.3    0.0    0.3       vmovupd  %xmm3, %xmm4
-# CHECK-NEXT: 5.     3     3.0    0.0    0.3       vmovdqa  %xmm4, %xmm5
-# CHECK-NEXT: 6.     3     3.3    0.0    0.0       vmovdqu  %xmm5, %xmm0
+# CHECK-NEXT: 0.     3     0.0    0.0    0.0       vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: 1.     3     0.0    0.0    0.0       vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: 2.     3     0.0    0.0    0.0       vmovups  %xmm1, %xmm2
+# CHECK-NEXT: 3.     3     0.0    0.0    0.0       vmovapd  %xmm2, %xmm3
+# CHECK-NEXT: 4.     3     0.0    0.0    0.0       vmovupd  %xmm3, %xmm4
+# CHECK-NEXT: 5.     3     0.0    0.0    0.0       vmovdqa  %xmm4, %xmm5
+# CHECK-NEXT: 6.     3     0.0    0.0    0.0       vmovdqu  %xmm5, %xmm0

test/tools/llvm-mca/X86/BtVer2/reg-move-elimination-4.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s
 
 xor %eax, %eax
 mov %eax, %ebx
 mov %ebx, %ecx
 mov %ecx, %edx
 mov %edx, %eax
 
 # CHECK:      Iterations:        3
 # CHECK-NEXT: Instructions:      15
-# CHECK-NEXT: Total Cycles:      12
+# CHECK-NEXT: Total Cycles:      9
 # CHECK-NEXT: Total uOps:        15
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    1.25
-# CHECK-NEXT: IPC:               1.25
+# CHECK-NEXT: uOps Per Cycle:    1.67
+# CHECK-NEXT: IPC:               1.67
 # CHECK-NEXT: Block RThroughput: 2.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      0     0.50                        xorl  %eax, %eax
 # CHECK-NEXT:  1      1     0.50                        movl  %eax, %ebx
 # CHECK-NEXT:  1      1     0.50                        movl  %ebx, %ecx
 # CHECK-NEXT:  1      1     0.50                        movl  %ecx, %edx
 # CHECK-NEXT:  1      1     0.50                        movl  %edx, %eax
 
 # CHECK:      Register File statistics:
-# CHECK-NEXT: Total number of mappings created:    12
-# CHECK-NEXT: Max number of mappings used:         7
+# CHECK-NEXT: Total number of mappings created:    0
+# CHECK-NEXT: Max number of mappings used:         0
 
 # CHECK:      *  Register File #1 -- JFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     72
 # CHECK-NEXT:    Total number of mappings created: 0
 # CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      *  Register File #2 -- JIntegerPRF:
 # CHECK-NEXT:    Number of physical registers:     64
-# CHECK-NEXT:    Total number of mappings created: 12
-# CHECK-NEXT:    Max number of mappings used:      7
+# CHECK-NEXT:    Total number of mappings created: 0
+# CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - JALU0
 # CHECK-NEXT: [1]   - JALU1
 # CHECK-NEXT: [2]   - JDiv
 # CHECK-NEXT: [3]   - JFPA
 # CHECK-NEXT: [4]   - JFPM
 # CHECK-NEXT: [5]   - JFPU0
 # CHECK-NEXT: [6]   - JFPU1
 # CHECK-NEXT: [7]   - JLAGU
 # CHECK-NEXT: [8]   - JMul
 # CHECK-NEXT: [9]   - JSAGU
 # CHECK-NEXT: [10]  - JSTC
 # CHECK-NEXT: [11]  - JVALU0
 # CHECK-NEXT: [12]  - JVALU1
 # CHECK-NEXT: [13]  - JVIMUL
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]
-# CHECK-NEXT: 2.00   2.00    -      -      -      -      -      -      -      -      -      -      -      -
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     xorl  %eax, %eax
-# CHECK-NEXT: 0.33   0.67    -      -      -      -      -      -      -      -      -      -      -      -     movl  %eax, %ebx
-# CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -     movl  %ebx, %ecx
-# CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -     movl  %ecx, %edx
-# CHECK-NEXT: 0.67   0.33    -      -      -      -      -      -      -      -      -      -      -      -     movl  %edx, %eax
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movl  %eax, %ebx
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movl  %ebx, %ecx
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movl  %ecx, %edx
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movl  %edx, %eax
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     012345678
 
-# CHECK:      [0,0]     DR   .    ..   xorl %eax, %eax
-# CHECK-NEXT: [0,1]     DeER .    ..   movl %eax, %ebx
-# CHECK-NEXT: [0,2]     .DeER.    ..   movl %ebx, %ecx
-# CHECK-NEXT: [0,3]     .D=eER    ..   movl %ecx, %edx
-# CHECK-NEXT: [0,4]     . D=eER   ..   movl %edx, %eax
-# CHECK-NEXT: [1,0]     . D---R   ..   xorl %eax, %eax
-# CHECK-NEXT: [1,1]     .  DeE-R  ..   movl %eax, %ebx
-# CHECK-NEXT: [1,2]     .  D=eER  ..   movl %ebx, %ecx
-# CHECK-NEXT: [1,3]     .   D=eER ..   movl %ecx, %edx
-# CHECK-NEXT: [1,4]     .   D==eER..   movl %edx, %eax
-# CHECK-NEXT: [2,0]     .    D---R..   xorl %eax, %eax
-# CHECK-NEXT: [2,1]     .    DeE--R.   movl %eax, %ebx
-# CHECK-NEXT: [2,2]     .    .DeE-R.   movl %ebx, %ecx
-# CHECK-NEXT: [2,3]     .    .D=eE-R   movl %ecx, %edx
-# CHECK-NEXT: [2,4]     .    . D=eER   movl %edx, %eax
+# CHECK:      [0,0]     DR   .  .   xorl  %eax, %eax
+# CHECK-NEXT: [0,1]     DR   .  .   movl  %eax, %ebx
+# CHECK-NEXT: [0,2]     .DR  .  .   movl  %ebx, %ecx
+# CHECK-NEXT: [0,3]     .DR  .  .   movl  %ecx, %edx
+# CHECK-NEXT: [0,4]     . DR .  .   movl  %edx, %eax
+# CHECK-NEXT: [1,0]     . DR .  .   xorl  %eax, %eax
+# CHECK-NEXT: [1,1]     .  DR.  .   movl  %eax, %ebx
+# CHECK-NEXT: [1,2]     .  DR.  .   movl  %ebx, %ecx
+# CHECK-NEXT: [1,3]     .   DR  .   movl  %ecx, %edx
+# CHECK-NEXT: [1,4]     .   DR  .   movl  %edx, %eax
+# CHECK-NEXT: [2,0]     .    DR .   xorl  %eax, %eax
+# CHECK-NEXT: [2,1]     .    DR .   movl  %eax, %ebx
+# CHECK-NEXT: [2,2]     .    .DR.   movl  %ebx, %ecx
+# CHECK-NEXT: [2,3]     .    .DR.   movl  %ecx, %edx
+# CHECK-NEXT: [2,4]     .    . DR   movl  %edx, %eax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     0.0    0.0    2.0       xorl %eax, %eax
-# CHECK-NEXT: 1.     3     1.0    1.0    1.0       movl %eax, %ebx
-# CHECK-NEXT: 2.     3     1.3    0.0    0.3       movl %ebx, %ecx
-# CHECK-NEXT: 3.     3     2.0    0.0    0.3       movl %ecx, %edx
-# CHECK-NEXT: 4.     3     2.3    0.0    0.0       movl %edx, %eax
+# CHECK-NEXT: 0.     3     0.0    0.0    0.0       xorl %eax, %eax
+# CHECK-NEXT: 1.     3     0.0    0.0    0.0       movl %eax, %ebx
+# CHECK-NEXT: 2.     3     0.0    0.0    0.0       movl %ebx, %ecx
+# CHECK-NEXT: 3.     3     0.0    0.0    0.0       movl %ecx, %edx
+# CHECK-NEXT: 4.     3     0.0    0.0    0.0       movl %edx, %eax

test/tools/llvm-mca/X86/BtVer2/reg-move-elimination-5.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s
 
 xor %rax, %rax
 mov %rax, %rbx
 mov %rbx, %rcx
 mov %rcx, %rdx
 mov %rdx, %rax
 
 # CHECK:      Iterations:        3
 # CHECK-NEXT: Instructions:      15
-# CHECK-NEXT: Total Cycles:      12
+# CHECK-NEXT: Total Cycles:      9
 # CHECK-NEXT: Total uOps:        15
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    1.25
-# CHECK-NEXT: IPC:               1.25
+# CHECK-NEXT: uOps Per Cycle:    1.67
+# CHECK-NEXT: IPC:               1.67
 # CHECK-NEXT: Block RThroughput: 2.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      0     0.50                        xorq  %rax, %rax
 # CHECK-NEXT:  1      1     0.50                        movq  %rax, %rbx
 # CHECK-NEXT:  1      1     0.50                        movq  %rbx, %rcx
 # CHECK-NEXT:  1      1     0.50                        movq  %rcx, %rdx
 # CHECK-NEXT:  1      1     0.50                        movq  %rdx, %rax
 
 # CHECK:      Register File statistics:
-# CHECK-NEXT: Total number of mappings created:    12
-# CHECK-NEXT: Max number of mappings used:         7
+# CHECK-NEXT: Total number of mappings created:    0
+# CHECK-NEXT: Max number of mappings used:         0
 
 # CHECK:      *  Register File #1 -- JFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     72
 # CHECK-NEXT:    Total number of mappings created: 0
 # CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      *  Register File #2 -- JIntegerPRF:
 # CHECK-NEXT:    Number of physical registers:     64
-# CHECK-NEXT:    Total number of mappings created: 12
-# CHECK-NEXT:    Max number of mappings used:      7
+# CHECK-NEXT:    Total number of mappings created: 0
+# CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - JALU0
 # CHECK-NEXT: [1]   - JALU1
 # CHECK-NEXT: [2]   - JDiv
 # CHECK-NEXT: [3]   - JFPA
 # CHECK-NEXT: [4]   - JFPM
 # CHECK-NEXT: [5]   - JFPU0
 # CHECK-NEXT: [6]   - JFPU1
 # CHECK-NEXT: [7]   - JLAGU
 # CHECK-NEXT: [8]   - JMul
 # CHECK-NEXT: [9]   - JSAGU
 # CHECK-NEXT: [10]  - JSTC
 # CHECK-NEXT: [11]  - JVALU0
 # CHECK-NEXT: [12]  - JVALU1
 # CHECK-NEXT: [13]  - JVIMUL
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]
-# CHECK-NEXT: 2.00   2.00    -      -      -      -      -      -      -      -      -      -      -      -
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     xorq  %rax, %rax
-# CHECK-NEXT: 0.33   0.67    -      -      -      -      -      -      -      -      -      -      -      -     movq  %rax, %rbx
-# CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -     movq  %rbx, %rcx
-# CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -     movq  %rcx, %rdx
-# CHECK-NEXT: 0.67   0.33    -      -      -      -      -      -      -      -      -      -      -      -     movq  %rdx, %rax
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movq  %rax, %rbx
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movq  %rbx, %rcx
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movq  %rcx, %rdx
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -     movq  %rdx, %rax
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     012345678
 
-# CHECK:      [0,0]     DR   .    ..   xorq %rax, %rax
-# CHECK-NEXT: [0,1]     DeER .    ..   movq %rax, %rbx
-# CHECK-NEXT: [0,2]     .DeER.    ..   movq %rbx, %rcx
-# CHECK-NEXT: [0,3]     .D=eER    ..   movq %rcx, %rdx
-# CHECK-NEXT: [0,4]     . D=eER   ..   movq %rdx, %rax
-# CHECK-NEXT: [1,0]     . D---R   ..   xorq %rax, %rax
-# CHECK-NEXT: [1,1]     .  DeE-R  ..   movq %rax, %rbx
-# CHECK-NEXT: [1,2]     .  D=eER  ..   movq %rbx, %rcx
-# CHECK-NEXT: [1,3]     .   D=eER ..   movq %rcx, %rdx
-# CHECK-NEXT: [1,4]     .   D==eER..   movq %rdx, %rax
-# CHECK-NEXT: [2,0]     .    D---R..   xorq %rax, %rax
-# CHECK-NEXT: [2,1]     .    DeE--R.   movq %rax, %rbx
-# CHECK-NEXT: [2,2]     .    .DeE-R.   movq %rbx, %rcx
-# CHECK-NEXT: [2,3]     .    .D=eE-R   movq %rcx, %rdx
-# CHECK-NEXT: [2,4]     .    . D=eER   movq %rdx, %rax
+# CHECK:      [0,0]     DR   .  .   xorq  %rax, %rax
+# CHECK-NEXT: [0,1]     DR   .  .   movq  %rax, %rbx
+# CHECK-NEXT: [0,2]     .DR  .  .   movq  %rbx, %rcx
+# CHECK-NEXT: [0,3]     .DR  .  .   movq  %rcx, %rdx
+# CHECK-NEXT: [0,4]     . DR .  .   movq  %rdx, %rax
+# CHECK-NEXT: [1,0]     . DR .  .   xorq  %rax, %rax
+# CHECK-NEXT: [1,1]     .  DR.  .   movq  %rax, %rbx
+# CHECK-NEXT: [1,2]     .  DR.  .   movq  %rbx, %rcx
+# CHECK-NEXT: [1,3]     .   DR  .   movq  %rcx, %rdx
+# CHECK-NEXT: [1,4]     .   DR  .   movq  %rdx, %rax
+# CHECK-NEXT: [2,0]     .    DR .   xorq  %rax, %rax
+# CHECK-NEXT: [2,1]     .    DR .   movq  %rax, %rbx
+# CHECK-NEXT: [2,2]     .    .DR.   movq  %rbx, %rcx
+# CHECK-NEXT: [2,3]     .    .DR.   movq  %rcx, %rdx
+# CHECK-NEXT: [2,4]     .    . DR   movq  %rdx, %rax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     0.0    0.0    2.0       xorq %rax, %rax
-# CHECK-NEXT: 1.     3     1.0    1.0    1.0       movq %rax, %rbx
-# CHECK-NEXT: 2.     3     1.3    0.0    0.3       movq %rbx, %rcx
-# CHECK-NEXT: 3.     3     2.0    0.0    0.3       movq %rcx, %rdx
-# CHECK-NEXT: 4.     3     2.3    0.0    0.0       movq %rdx, %rax
+# CHECK-NEXT: 0.     3     0.0    0.0    0.0       xorq %rax, %rax
+# CHECK-NEXT: 1.     3     0.0    0.0    0.0       movq %rax, %rbx
+# CHECK-NEXT: 2.     3     0.0    0.0    0.0       movq %rbx, %rcx
+# CHECK-NEXT: 3.     3     0.0    0.0    0.0       movq %rcx, %rdx
+# CHECK-NEXT: 4.     3     0.0    0.0    0.0       movq %rdx, %rax

tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp

 void RegisterFile::addRegisterFile(const MCRegisterFileDesc &RF,
                                    ArrayRef<MCRegisterCostEntry> Entries) {
   // A default register file is always allocated at index #0. That register file
   // is mainly used to count the total number of mappings created by all
   // register files at runtime. Users can limit the number of available physical
   // registers in register file #0 through the command line flag
   // `-register-file-size`.
   unsigned RegisterFileIndex = RegisterFiles.size();
-  RegisterFiles.emplace_back(RF.NumPhysRegs);
+  RegisterFiles.emplace_back(RF.NumPhysRegs, RF.MaxMovesEliminatedPerCycle,
+                             RF.AllowZeroMoveEliminationOnly);
 
   // Special case where there is no register class identifier in the set.
   // An empty set of register classes means: this register file contains all
   // the physical registers specified by the target.
   // We optimistically assume that a register can be renamed at the cost of a
   // single physical register. The constructor of RegisterFile ensures that
   // a RegisterMapping exists for each logical register defined by the Target.
   if (Entries.empty())
for (const MCPhysReg Reg : RC) {
         // The only register file that is allowed to overlap is the default
         // register file at index #0. The analysis is inaccurate if register
         // files overlap.
         errs() << "warning: register " << MRI.getName(Reg)
                << " defined in multiple register files.";
       }
       IPC = std::make_pair(RegisterFileIndex, RCE.Cost);
       Entry.RenameAs = Reg;
+      Entry.AllowMoveElimination = RCE.AllowMoveElimination;
 
       // Assume the same cost for each sub-register.
       for (MCSubRegIterator I(Reg, &MRI); I.isValid(); ++I) {
         RegisterRenamingInfo &OtherEntry = RegisterMappings[*I].second;
         if (!OtherEntry.IndexPlusCost.first &&
             (!OtherEntry.RenameAs ||
              MRI.isSuperRegister(*I, OtherEntry.RenameAs))) {
           OtherEntry.IndexPlusCost = IPC;
if (OtherWR.getWriteState() == &WS)
       OtherWR.invalidate();
   }
 }
 
 bool RegisterFile::tryEliminateMove(WriteState &WS, const ReadState &RS) {
   const RegisterMapping &RMFrom = RegisterMappings[RS.getRegisterID()];
   const RegisterMapping &RMTo = RegisterMappings[WS.getRegisterID()];
 
-  // Early exit if the PRF doesn't support move elimination for this register.
-  if (!RMTo.second.AllowMoveElimination)
-    return false;
-
   // From and To must be owned by the same PRF.
   const RegisterRenamingInfo &RRIFrom = RMFrom.second;
   const RegisterRenamingInfo &RRITo = RMTo.second;
   unsigned RegisterFileIndex = RRIFrom.IndexPlusCost.first;
   if (RegisterFileIndex != RRITo.IndexPlusCost.first)
     return false;
 
   // We only allow move elimination for writes that update a full physical
   // register. On X86, move elimination is possible with 32-bit general purpose
   // registers because writes to those registers are not partial writes.  If a
   // register move is a partial write, then we conservatively assume that move
   // elimination fails, since it would either trigger a partial update, or the
   // issue of a merge opcode.
   //
   // Note that this constraint may be lifted in future.  For example, we could
   // make this model more flexible, and let users customize the set of registers
   // (i.e. register classes) that allow move elimination.
   //
   // For now, we assume that there is a strong correlation between registers
   // that allow move elimination, and how those same registers are renamed in
   // hardware.
-  if (RRITo.RenameAs && RRITo.RenameAs != WS.getRegisterID())
+  if (RRITo.RenameAs && RRITo.RenameAs != WS.getRegisterID()) {
+    // Early exit if the PRF doesn't support move elimination for this register.
+    if (!RegisterMappings[RRITo.RenameAs].second.AllowMoveElimination)
+      return false;
     if (!WS.clearsSuperRegisters())
       return false;
+  }
 
   RegisterMappingTracker &RMT = RegisterFiles[RegisterFileIndex];
   if (RMT.MaxMoveEliminatedPerCycle &&
       RMT.NumMoveEliminated == RMT.MaxMoveEliminatedPerCycle)
     return false;
 
   bool IsZeroMove = ZeroRegisters[RS.getRegisterID()];
   if (RMT.AllowZeroMoveEliminationOnly && !IsZeroMove)

tools/llvm-mca/lib/InstrBuilder.cpp

InstrBuilder::createInstruction(const MCInst &MCI) {
 
   // Check if this is a dependency breaking instruction.
   APInt Mask;
 
   unsigned ProcID = STI.getSchedModel().getProcessorID();
   bool IsZeroIdiom = MCIA.isZeroIdiom(MCI, Mask, ProcID);
   bool IsDepBreaking =
       IsZeroIdiom || MCIA.isDependencyBreaking(MCI, Mask, ProcID);
+  if (MCIA.isOptimizableRegisterMove(MCI, ProcID))
+    NewIS->setOptimizableMove();
 
   // Initialize Reads first.
   for (const ReadDescriptor &RD : D.Reads) {
     int RegID = -1;
     if (!RD.isImplicitRead()) {
       // explicit read.
       const MCOperand &Op = MCI.getOperand(RD.OpIndex);
       // Skip non-register operands.

utils/TableGen/CodeGenSchedule.h

 /// Represent the cost of allocating a register of register class RCDef.
 ///
 /// The cost of allocating a register is equivalent to the number of physical
 /// registers used by the register renamer. Register costs are defined at
 /// register class granularity.
 struct CodeGenRegisterCost {
   Record *RCDef;
   unsigned Cost;
-  CodeGenRegisterCost(Record *RC, unsigned RegisterCost)
-      : RCDef(RC), Cost(RegisterCost) {}
+  bool AllowMoveElimination;
+  CodeGenRegisterCost(Record *RC, unsigned RegisterCost, bool AllowMoveElim = false)
+      : RCDef(RC), Cost(RegisterCost), AllowMoveElimination(AllowMoveElim) {}
   CodeGenRegisterCost(const CodeGenRegisterCost &) = default;
   CodeGenRegisterCost &operator=(const CodeGenRegisterCost &) = delete;
 };
 
 /// A processor register file.
 ///
 /// This class describes a processor register file. Register file information is
 /// currently consumed by external tools like llvm-mca to predict dispatch
 /// stalls due to register pressure.
 struct CodeGenRegisterFile {
   std::string Name;
   Record *RegisterFileDef;
+  unsigned MaxMovesEliminatedPerCycle;
+  bool AllowZeroMoveEliminationOnly;
 
   unsigned NumPhysRegs;
   std::vector<CodeGenRegisterCost> Costs;
 
-  CodeGenRegisterFile(StringRef name, Record *def)
-      : Name(name), RegisterFileDef(def), NumPhysRegs(0) {}
+  CodeGenRegisterFile(StringRef name, Record *def, unsigned MaxMoveElimPerCy = 0,
+                      bool AllowZeroMoveElimOnly = false)
+      : Name(name), RegisterFileDef(def),
+        MaxMovesEliminatedPerCycle(MaxMoveElimPerCy),
+        AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly),
+        NumPhysRegs(0) {}
 
   bool hasDefaultCosts() const { return Costs.empty(); }
 };
 
 // Processor model.
 //
 // ModelName is a unique name used to name an instantiation of MCSchedModel.
 //

utils/TableGen/CodeGenSchedule.cpp

void CodeGenSchedModels::collectRegisterFiles() {
 
   // RegisterFiles is the vector of CodeGenRegisterFile.
   for (Record *RF : RegisterFileDefs) {
     // For each register file definition, construct a CodeGenRegisterFile object
     // and add it to the appropriate scheduling model.
     CodeGenProcModel &PM = getProcModel(RF->getValueAsDef("SchedModel"));
     PM.RegisterFiles.emplace_back(CodeGenRegisterFile(RF->getName(),RF));
     CodeGenRegisterFile &CGRF = PM.RegisterFiles.back();
+    CGRF.MaxMovesEliminatedPerCycle =
+        RF->getValueAsInt("MaxMovesEliminatedPerCycle");
+    CGRF.AllowZeroMoveEliminationOnly =
+        RF->getValueAsBit("AllowZeroMoveEliminationOnly");
 
     // Now set the number of physical registers as well as the cost of registers
     // in each register class.
     CGRF.NumPhysRegs = RF->getValueAsInt("NumPhysRegs");
     if (!CGRF.NumPhysRegs) {
       PrintFatalError(RF->getLoc(),
                       "Invalid RegisterFile with zero physical registers");
     }
 
     RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");
     std::vector<int64_t> RegisterCosts = RF->getValueAsListOfInts("RegCosts");
+    ListInit *MoveElimInfo = RF->getValueAsListInit("AllowMoveElimination");
     for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) {
       int Cost = RegisterCosts.size() > I ? RegisterCosts[I] : 1;
-      CGRF.Costs.emplace_back(RegisterClasses[I], Cost);
+
+      bool AllowMoveElim = false;
+      if (MoveElimInfo->size() > I) {
+        BitInit *Val = cast<BitInit>(MoveElimInfo->getElement(I));
+        AllowMoveElim = Val->getValue();
+      }
+
+      CGRF.Costs.emplace_back(RegisterClasses[I], Cost, AllowMoveElim);
     }
   }
 }
 
 // Collect all the RegisterFile definitions available in this target.
 void CodeGenSchedModels::collectPfmCounters() {
   for (Record *Def : Records.getAllDerivedDefinitions("PfmIssueCounter")) {
     CodeGenProcModel &PM = getProcModel(Def->getValueAsDef("SchedModel"));

utils/TableGen/SubtargetEmitter.cpp

 SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
                                          raw_ostream &OS) {
   if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) {
         return RF.hasDefaultCosts();
       }))
     return 0;
 
   // Print the RegisterCost table first.
-  OS << "\n// {RegisterClassID, Register Cost}\n";
+  OS << "\n// {RegisterClassID, Register Cost, AllowMoveElimination }\n";
   OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName
      << "RegisterCosts"
      << "[] = {\n";
 
   for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) {
     // Skip register files with a default cost table.
     if (RF.hasDefaultCosts())
       continue;
     // Add entries to the cost table.
     for (const CodeGenRegisterCost &RC : RF.Costs) {
       OS << "  { ";
       Record *Rec = RC.RCDef;
       if (Rec->getValue("Namespace"))
         OS << Rec->getValueAsString("Namespace") << "::";
-      OS << Rec->getName() << "RegClassID, " << RC.Cost << "},\n";
+      OS << Rec->getName() << "RegClassID, " << RC.Cost << ", "
+         << RC.AllowMoveElimination << "},\n";
     }
   }
   OS << "};\n";
 
   // Now generate a table with register file info.
-  OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl}\n";
+  OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl, "
+     << "MaxMovesEliminatedPerCycle, AllowZeroMoveEliminationOnly }\n";
   OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName
      << "RegisterFiles"
      << "[] = {\n"
-     << "  { \"InvalidRegisterFile\", 0, 0, 0 },\n";
+     << "  { \"InvalidRegisterFile\", 0, 0, 0, 0, 0 },\n";
   unsigned CostTblIndex = 0;
 
   for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {
     OS << "  { ";
     OS << '"' << RD.Name << '"' << ", " << RD.NumPhysRegs << ", ";
     unsigned NumCostEntries = RD.Costs.size();
-    OS << NumCostEntries << ", " << CostTblIndex << "},\n";
+    OS << NumCostEntries << ", " << CostTblIndex << ", "
+       << RD.MaxMovesEliminatedPerCycle << ", "
+       << RD.AllowZeroMoveEliminationOnly << "},\n";
     CostTblIndex += NumCostEntries;
   }
   OS << "};\n";
 
   return CostTblIndex;
 }
 
 static bool EmitPfmIssueCountersTable(const CodeGenProcModel &ProcModel,