This patch adds the ability to identify instructions that are "move elimination candidates". It also allows scheduling models to describe processor register files that allow move elimination.
A move elimination candidate is an instruction that can be eliminated at register renaming stage.
Each subtarget can specify which instructions are move elimination candidates with the help of tablegen class "IsOptimizableMoveFunction" (see llvm/Target/TargetInstrPredicate.td).
For example, on X86, BtVer2 allows MMX/SSE moves to be eliminated only if source and destination are not the same register. The definition of 'IsOptimizableMoveFunction' for BtVer2 looks like this:
def : IsOptimizableMoveFunction<[ InstructionEquivalenceClass<[ // MMX variants. MMX_MOVQ64rr, // SSE variants. MOVAPSrr, MOVUPSrr, MOVAPDrr, MOVUPDrr, MOVDQArr, MOVDQUrr, // AVX variants. VMOVAPSrr, VMOVUPSrr, VMOVAPDrr, VMOVUPDrr, VMOVDQArr, VMOVDQUrr ], CheckNot<CheckSameRegOperand<0, 1>> > ]>;
Definitions of IsOptimizableMoveFunction from different processors of a same Target are used by the SubtargetEmitter to auto-generate target-specific overrides for the following predicate methods:
bool TargetSubtargetInfo::isOptimizableRegisterMove(const MachineInstr *MI) const; bool MCInstrAnalysis::isOptimizableRegisterMove(const MCInst &MI, unsigned CPUID) const;
By default, those methods return false (i.e. no move elimination is allowed by the subtarget).
Tablegen class RegisterFile has been extended with the following information:
- The set of register classes that allow move elimination.
- Maxium number of moves that can be eliminated every cycle.
- Whether move elimination is restricted to moves from registers that are known to be zero.
This patch is structured in three part:
A first part (which is mostly boilerplate) adds the new 'isOptimizableRegisterMove' target hooks, and extends existing register file descriptors in MC by introducing new fields to describe properties related to move elimination.
A second part, uses the new tablegen constructs to describe move elimination in the BtVer2 scheduling model.
A third part, teaches llm-mca how to query the new 'isOptimizableRegisterMove' hook to mark instructions that are candidates for move elimination. It also teaches class RegisterFile how to describe constraints on move elimination at PRF granularity.
llvm-mca tests for btver2 show differences before/after this patch.
Please let me know if okay to commit.