[WebAssembly] Fix fneg lowering

[tlively]

Summary

Subtraction from zero and floating point negation do not have the same
semantics, so fix lowering.

[aheejin]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

187 ↗

(On Diff #168535)

Can we define ivneg or something like

// Integer vector negation
def ivneg : PatFrag<(ops node:$in), (sub immAllZeroesV, node:$in)>;

And change this pattern to resemble the simpler SIMDNegFP one, using ivneg in place of fneg, to make it simpler and symmetrical? The reason I said ivneg instead of ineg is there's already an [[ https://github.com/llvm-mirror/llvm/blob/8cc4d7e1c6c2a61e560268413a1355d0260a81b3/include/llvm/Target/TargetSelectionDAG.td#L757 | ineg ]] node there, which does not seem to support vectors.

And this is irrelevant to this CL, but there also seems to be a [[ https://github.com/llvm-mirror/llvm/blob/8cc4d7e1c6c2a61e560268413a1355d0260a81b3/include/llvm/Target/TargetSelectionDAG.td#L756 | vnot ]] node. Can we possibly use this to simplify SIMDNot pattern?

test/CodeGen/WebAssembly/simd-arith.ll

747 ↗

(On Diff #168535)

To make this to work, does a floating point instruction has to have fast attribute, or only some of these fast-math flags?

[tlively]

• Rebase and unify FP and Int Negs

[tlively]

• change fast flag to nsz

[tlively]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

187 ↗

(On Diff #168535)

Good call. vnot is on my list of things to do!

test/CodeGen/WebAssembly/simd-arith.ll

747 ↗

(On Diff #168535)

Looks like only nsz was necessary.

[aheejin]

test/CodeGen/WebAssembly/simd-arith.ll

747 ↗

(On Diff #168535)

One-line comment on why nsz is necessary would be good

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 2)>;
 }
 
 multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
   defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 3)>;
 }
 
+// Integer vector negation
+def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
+
 // Integer addition: add
 let isCommutable = 1 in
 defm ADD : SIMDBinaryInt<add, "add", 24>;
 
 // Integer subtraction: sub
 defm SUB : SIMDBinaryInt<sub, "sub", 28>;
 
 // Integer multiplication: mul
 defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 32>;
 
 // Integer negation: neg
-multiclass SIMDNeg<ValueType vec_t, string vec, PatFrag splat_pat,
-                   ValueType lane_t, SDNode node, dag lane, bits<32> simdop> {
-  defm NEG_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
-                           (outs), (ins),
-                           [(set
-                             (vec_t V128:$dst),
-                             (vec_t (node
-                               (vec_t (splat_pat lane)),
-                               (vec_t V128:$vec)
-                             ))
+multiclass SIMDNeg<ValueType vec_t, string vec, SDNode neg, bits<32> simdop> {
+  defm NEG_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+                           [(set (vec_t V128:$dst),
+                             (vec_t (neg (vec_t V128:$vec)))
                            )],
                            vec#".neg\t$dst, $vec", vec#".neg", simdop>;
 }
 
-multiclass SIMDNegInt<ValueType vec_t, string vec, PatFrag splat_pat,
-                      ValueType lane_t, bits<32> simdop> {
-  defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, sub, (lane_t 0), simdop>;
-}
-
-defm "" : SIMDNegInt<v16i8, "i8x16", splat16, i32, 36>;
-defm "" : SIMDNegInt<v8i16, "i16x8", splat8, i32, 37>;
-defm "" : SIMDNegInt<v4i32, "i32x4", splat4, i32, 38>;
-defm "" : SIMDNegInt<v2i64, "i64x2", splat2, i64, 39>;
+defm "" : SIMDNeg<v16i8, "i8x16", ivneg, 36>;
+defm "" : SIMDNeg<v8i16, "i16x8", ivneg, 37>;
+defm "" : SIMDNeg<v4i32, "i32x4", ivneg, 38>;
+defm "" : SIMDNeg<v2i64, "i64x2", ivneg, 39>;
 
 //===----------------------------------------------------------------------===//
 // Saturating integer arithmetic
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDBinarySat<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
   defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 2)>;

 def : StorePatExternSymOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
 }
 
 //===----------------------------------------------------------------------===//
 // Floating-point sign bit operations
 //===----------------------------------------------------------------------===//
 
 // Negation: neg
-def fpimm0 : FPImmLeaf<fAny, [{ return Imm.isExactlyValue(+0.0); }]>;
-multiclass SIMDNegFP<ValueType vec_t, string vec, PatFrag splat_pat,
-                     ValueType lane_t, bits<32> simdop> {
-  defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, fsub, (lane_t fpimm0),
-                    simdop>;
-}
-
-defm "" : SIMDNegFP<v4f32, "f32x4", splat4, f32, 125>;
-defm "" : SIMDNegFP<v2f64, "f64x2", splat2, f64, 126>;
+defm "" : SIMDNeg<v4f32, "f32x4", fneg, 125>;
+defm "" : SIMDNeg<v2f64, "f64x2", fneg, 126>;
 
 // Absolute value: abs
 multiclass SIMDAbs<ValueType vec_t, string vec, bits<32> simdop> {
   defm ABS_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
                            [(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))],
                            vec#".abs\t$dst, $vec", vec#".abs", simdop>;
 }
 

llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll

 ; ==============================================================================
 ; CHECK-LABEL: neg_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .param v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @neg_v4f32(<4 x float> %x) {
-  %a = fsub <4 x float> <float 0., float 0., float 0., float 0.>, %x
+  ; nsz makes this semantically equivalent to flipping sign bit
+  %a = fsub nsz <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, %x
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: abs_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .param v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f32x4.abs $push[[R:[0-9]+]]=, $0{{$}}

 ; ==============================================================================
 ; CHECK-LABEL: neg_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .param v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @neg_v2f64(<2 x double> %x) {
-  %a = fsub <2 x double> <double 0., double 0.>, %x
+  ; nsz makes this semantically equivalent to flipping sign bit
+  %a = fsub nsz <2 x double> <double 0., double 0.>, %x
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: abs_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .param v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f64x2.abs $push[[R:[0-9]+]]=, $0{{$}}