[WebAssembly] Fix fneg lowering

[tlively]

Summary

Subtraction from zero and floating point negation do not have the same
semantics, so fix lowering.

[aheejin]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

187

Can we define ivneg or something like

// Integer vector negation
def ivneg : PatFrag<(ops node:$in), (sub immAllZeroesV, node:$in)>;

And change this pattern to resemble the simpler SIMDNegFP one, using ivneg in place of fneg, to make it simpler and symmetrical? The reason I said ivneg instead of ineg is there's already an [[ https://github.com/llvm-mirror/llvm/blob/8cc4d7e1c6c2a61e560268413a1355d0260a81b3/include/llvm/Target/TargetSelectionDAG.td#L757 | ineg ]] node there, which does not seem to support vectors.

And this is irrelevant to this CL, but there also seems to be a [[ https://github.com/llvm-mirror/llvm/blob/8cc4d7e1c6c2a61e560268413a1355d0260a81b3/include/llvm/Target/TargetSelectionDAG.td#L756 | vnot ]] node. Can we possibly use this to simplify SIMDNot pattern?

test/CodeGen/WebAssembly/simd-arith.ll

747

To make this to work, does a floating point instruction has to have fast attribute, or only some of these fast-math flags?

[tlively]

• Rebase and unify FP and Int Negs

[tlively]

• change fast flag to nsz

[tlively]

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

187

Good call. vnot is on my list of things to do!

test/CodeGen/WebAssembly/simd-arith.ll

747

Looks like only nsz was necessary.

[aheejin]

test/CodeGen/WebAssembly/simd-arith.ll

747

One-line comment on why nsz is necessary would be good

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

defm "" : SIMDShift<v2i64, "i64x2", node, (splat2 (i64 (zext I32:$x))),
                       name, !add(baseInst, !if(skip, 6, 3))>;
 }
 multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
   defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
   defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
 }
-multiclass SIMDNeg<ValueType vec_t, string vec, PatFrag splat_pat,
-                   ValueType lane_t, SDNode node, dag lane, bits<32> simdop> {
+multiclass SIMDNegInt<ValueType vec_t, string vec, bits<32> simdop> {
   defm NEG_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
                            (outs), (ins),
                            [(set
                              (vec_t V128:$dst),
-                             (vec_t (node
-                               (vec_t (splat_pat lane)),
+                             (vec_t (sub
+                               (vec_t immAllZerosV),
                                (vec_t V128:$vec)
                              ))
                            )],
                            vec#".neg\t$dst, $vec", vec#".neg", simdop>;
 }
-multiclass SIMDNegInt<ValueType vec_t, string vec, PatFrag splat_pat,
-                      ValueType lane_t, bits<32> simdop> {
-  defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, sub, (lane_t 0), simdop>;
-}
-def fpimm0 : FPImmLeaf<fAny, [{ return Imm.isExactlyValue(+0.0); }]>;
-multiclass SIMDNegFP<ValueType vec_t, string vec, PatFrag splat_pat,
-                     ValueType lane_t, bits<32> simdop> {
-  defm "" : SIMDNeg<vec_t, vec, splat_pat, lane_t, fsub, (lane_t fpimm0),
-                    simdop>;
+multiclass SIMDNegFP<ValueType vec_t, string vec, bits<32> simdop> {
+  defm NEG_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
+                           (outs), (ins),
+                           [(set (vec_t V128:$dst), (vec_t (fneg V128:$vec)))],
+                           vec#".neg\t$dst, $vec", vec#".neg", simdop>;
 }
 multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> {
   defm NOT_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
                            (outs), (ins),
                            [(set
                              (vec_t V128:$dst),
                              (vec_t (xor
                                (vec_t V128:$vec),

 } // isCommutable = 1
 
 defm SUB : SIMDBinaryInt<sub, "sub", 28>;
 defm SUB : SIMDBinaryFP<fsub, "sub", 135>;
 defm SUB_SAT_S : SIMDBinarySat<wasm_sub_sat_s, "sub_saturate_s", 44>;
 defm SUB_SAT_U : SIMDBinarySat<wasm_sub_sat_u, "sub_saturate_u", 45>;
 defm DIV : SIMDBinaryFP<fdiv, "div", 137>;
 
-defm "" : SIMDNegInt<v16i8, "i8x16", splat16, i32, 36>;
-defm "" : SIMDNegInt<v8i16, "i16x8", splat8, i32, 37>;
-defm "" : SIMDNegInt<v4i32, "i32x4", splat4, i32, 38>;
-defm "" : SIMDNegInt<v2i64, "i64x2", splat2, i64, 39>;
-defm "" : SIMDNegFP<v4f32, "f32x4", splat4, f32, 125>;
-defm "" : SIMDNegFP<v2f64, "f64x2", splat2, f64, 126>;
+defm "" : SIMDNegInt<v16i8, "i8x16", 36>;
+defm "" : SIMDNegInt<v8i16, "i16x8", 37>;
+defm "" : SIMDNegInt<v4i32, "i32x4", 38>;
+defm "" : SIMDNegInt<v2i64, "i64x2", 39>;
+defm "" : SIMDNegFP<v4f32, "f32x4", 125>;
+defm "" : SIMDNegFP<v2f64, "f64x2", 126>;
 
 defm SHL : SIMDShiftInt<shl, "shl", 48, 0>;
 defm SHR_S : SIMDShiftInt<sra, "shr_s", 52, 1>;
 defm SHR_U : SIMDShiftInt<srl, "shr_u", 53, 1>;
 
 let isCommutable = 1 in {
 defm AND : SIMDBitwise<and, "and", 60>;
 defm OR : SIMDBitwise<or, "or", 61>;

test/CodeGen/WebAssembly/simd-arith.ll

 ; ==============================================================================
 ; CHECK-LABEL: neg_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .param v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @neg_v4f32(<4 x float> %x) {
-  %a = fsub <4 x float> <float 0., float 0., float 0., float 0.>, %x
+  %a = fsub fast <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, %x
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: abs_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .param v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f32x4.abs $push[[R:[0-9]+]]=, $0{{$}}

 ; ==============================================================================
 ; CHECK-LABEL: neg_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .param v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @neg_v2f64(<2 x double> %x) {
-  %a = fsub <2 x double> <double 0., double 0.>, %x
+  %a = fsub fast <2 x double> <double 0., double 0.>, %x
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: abs_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .param v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f64x2.abs $push[[R:[0-9]+]]=, $0{{$}}