AMDGPU: Add support pattern for SUB of one bit

[cfang]

Summary

Add selection patterns to support one bit Sub.

[nhaehnle]

Could you expand the test so that both uniform and non-uniform cases are tested?

[arsenm]

Like the add case I'm worried about some cases in control flow and some other edge cases

[cfang]

Add test for non-uniform case.

[rampitec]

LGTM

lib/Target/AMDGPU/SIInstructions.td

   (S_XOR_B64 $src0, $src1)
 >;
 
 def : GCNPat <
   (i1 (add i1:$src0, i1:$src1)),
   (S_XOR_B64 $src0, $src1)
 >;
 
+def : GCNPat <
+  (i1 (sub i1:$src0, i1:$src1)),
+  (S_XOR_B64 $src0, $src1)
+>;
+
 let AddedComplexity = 1 in {
 def : GCNPat <
   (i1 (add i1:$src0, (i1 -1))),
   (S_NOT_B64 $src0)
 >;
+
+def : GCNPat <
+  (i1 (sub i1:$src0, (i1 -1))),
+  (S_NOT_B64 $src0)
+>;
 }
 
 def : GCNPat <
   (f16 (sint_to_fp i1:$src)),
   (V_CVT_F16_F32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_NEG_ONE), $src))
 >;
 
 def : GCNPat <

test/CodeGen/AMDGPU/sub_i1.ll

+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+
+; GCN-LABEL: {{^}}sub_var_var_i1:
+; GCN: s_xor_b64
+define amdgpu_kernel void @sub_var_var_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
+  %a = load volatile i1, i1 addrspace(1)* %in0
+  %b = load volatile i1, i1 addrspace(1)* %in1
+  %sub = sub i1 %a, %b
+  store i1 %sub, i1 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}sub_var_imm_i1:
+; GCN: s_not_b64
+define amdgpu_kernel void @sub_var_imm_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) {
+  %a = load volatile i1, i1 addrspace(1)* %in
+  %sub = sub i1 %a, 1
+  store i1 %sub, i1 addrspace(1)* %out
+  ret void
+}