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Differential D52469

AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patterns
ClosedPublic

Authored by tstellar on Sep 25 2018, 6:57 AM.

Details

Reviewers
arsenm
nhaehnle
Commits
rG344475fce536: AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patterns
rL343125: AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patterns
Summary

This is essentially NFC, because the complex pattern used for these patterns
will fail on non-CI, but this makes the pattern consistent with other CI
smrd patterns. It is also a performance improvement, because the pattern
will now fail earlier on non-CI.

Diff Detail

Repository
rL LLVM

Event Timeline

tstellar created this revision.Sep 25 2018, 6:57 AM
Harbormaster completed remote builds in B23059: Diff 166877.Sep 25 2018, 6:57 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptSep 25 2018, 6:57 AM
arsenm accepted this revision.Sep 25 2018, 4:27 PM

LGTM

This revision is now accepted and ready to land.Sep 25 2018, 4:27 PM
Closed by commit rL343125: AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patterns (authored by tstellar). · Explain WhySep 26 2018, 9:57 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
2 lines

Diff 167158

llvm/trunk/lib/Target/AMDGPU/SMInstructions.td

Show First 20 Lines • Show All 771 Lines • ▼ Show 20 Lines
def : SMRD_Pattern_ci <"S_LOAD_DWORDX2", v2i32>; def : SMRD_Pattern_ci <"S_LOAD_DWORDX2", v2i32>;
def : SMRD_Pattern_ci <"S_LOAD_DWORDX4", v4i32>; def : SMRD_Pattern_ci <"S_LOAD_DWORDX4", v4i32>;
def : SMRD_Pattern_ci <"S_LOAD_DWORDX8", v8i32>; def : SMRD_Pattern_ci <"S_LOAD_DWORDX8", v8i32>;
def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>; def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>;
class SMLoad_Pattern_ci <string Instr, ValueType vt> : GCNPat < class SMLoad_Pattern_ci <string Instr, ValueType vt> : GCNPat <
(vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)), (vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)),
(!cast<InstSI>(Instr) $sbase, $offset, (as_i1imm $glc))> { (!cast<InstSI>(Instr) $sbase, $offset, (as_i1imm $glc))> {
let OtherPredicates = [isCI]; // should this be isCIOnly? let OtherPredicates = [isCIOnly];
} }
def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORD_IMM_ci", i32>; def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORD_IMM_ci", i32>;
def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORDX2_IMM_ci", v2i32>; def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORDX2_IMM_ci", v2i32>;
def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORDX4_IMM_ci", v4i32>; def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORDX4_IMM_ci", v4i32>;
def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORDX8_IMM_ci", v8i32>; def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORDX8_IMM_ci", v8i32>;
def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORDX16_IMM_ci", v16i32>; def : SMLoad_Pattern_ci <"S_BUFFER_LOAD_DWORDX16_IMM_ci", v16i32>;
} // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity } // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity