[WebAssembly] SIMD sqrt

[tlively]

• Add encoding tests

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
   defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
                               !add(baseInst, 1)>;
 }
 multiclass SIMDAbs<ValueType vec_t, string vec, bits<32> simdop> {
   defm ABS_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
                            [(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))],
                            vec#".abs\t$dst, $vec", vec#".abs", simdop>;
 }
+multiclass SIMDSqrt<ValueType vec_t, string vec, bits<32> simdop> {
+  defm SQRT_#vec_t :
+    SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+           [(set (vec_t V128:$dst), (vec_t (fsqrt V128:$vec)))],
+           vec#".sqrt\t$dst, $vec", vec#".sqrt", simdop>;
+}
 
 let Defs = [ARGUMENTS] in {
 defm "" : ConstVec<v16i8,
                    (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
                         vec_i8imm_op:$i2, vec_i8imm_op:$i3,
                         vec_i8imm_op:$i4, vec_i8imm_op:$i5,
                         vec_i8imm_op:$i6, vec_i8imm_op:$i7,
                         vec_i8imm_op:$i8, vec_i8imm_op:$i9,

 defm GT : SIMDConditionFP<"gt", SETOGT, 113>;
 defm GE_S : SIMDConditionInt<"ge_s", SETGE, 115, 2>;
 defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 116, 2>;
 defm GE : SIMDConditionFP<"ge", SETOGE, 123>;
 
 defm "" : SIMDAbs<v4f32, "f32x4", 127>;
 defm "" : SIMDAbs<v2f64, "f64x2", 128>;
 
+defm "" : SIMDSqrt<v4f32, "f32x4", 141>;
+defm "" : SIMDSqrt<v2f64, "f64x2", 142>;
+
 } // Defs = [ARGUMENTS]
 
 // Def load and store patterns from WebAssemblyInstrMemory.td for vector types
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
 
 def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>;
 def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>;

test/CodeGen/WebAssembly/simd-arith.ll

 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fmul <4 x float> %x, %y
   ret <4 x float> %a
 }
 
+; CHECK-LABEL: sqrt_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.sqrt $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
+define <4 x float> @sqrt_v4f32(<4 x float> %x) {
+  %a = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
+  ret <4 x float> %a
+}
+
 ; ==============================================================================
 ; 2 x double
 ; ==============================================================================
 ; CHECK-LABEL: neg_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-NEXT: .param v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f64x2.neg $push[[R:[0-9]+]]=, $0{{$}}

 ; SIMD128-NEXT: .param v128, v128{{$}}
 ; SIMD128-NEXT: .result v128{{$}}
 ; SIMD128-NEXT: f64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fmul <2 x double> %x, %y
   ret <2 x double> %a
 }
+
+; CHECK-LABEL: sqrt_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.sqrt $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
+define <2 x double> @sqrt_v2f64(<2 x double> %x) {
+  %a = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
+  ret <2 x double> %a
+}