Add support for dynamic libraries on Hexagon

[sidneym]

Summary

Write out the plt header and stub.
Hexagon uses RELA relocations

[ruiu]

ELF/Arch/Hexagon.cpp

44 ↗

(On Diff #166332)

Is this an ABI specification that it doesn't support lazy PLT resolution?

test/ELF/Inputs/hexagon-shared.s

1 ↗

(On Diff #166332)

remove the blank line.

[sidneym]

ELF/Arch/Hexagon.cpp

44 ↗

(On Diff #166332)

The ABI does support Lazy binding,

[sidneym]

ELF/Arch/Hexagon.cpp

44 ↗

(On Diff #166332)

I can add the header, I didn't because it wasn't getting used.

[ruiu]

ELF/Arch/Hexagon.cpp

44 ↗

(On Diff #166332)

OK, can you expand the comment a bit? It is not clear to me that why you mentioned musl here. I guess musl is a commonly used libc for Hexagon?

226 ↗

(On Diff #166332)

Format.

[sidneym]

Adds a PLT header.
Fixes formatting issue.

[ruiu]

ELF/Arch/Hexagon.cpp

235 ↗

(On Diff #167204)

We fill gaps with a trap instruction. Is 0x00 a formal trap instruction (e.g. INT3 on x86)? If not, please choose a trap instruction for Hexagon ISA and replace 0x00 with that instruction.

Also, why do we have a padding at end of each PLT entry? Can we simply remove them?

[sidneym]

Swap zero pad with nop insn pad.
Reduce the padding but still bring plt0 to a 16byte alignment. There was no obvious reason for the additional padding and it is not part of the ABI.

[sidneym]

ELF/Arch/Hexagon.cpp

232 ↗

(On Diff #167376)

OK, the blank line isn't needed.

[sidneym]

ELF/Arch/Hexagon.cpp

236 ↗

(On Diff #167376)

OK, a trap, fine. Only after I submit do I carefully read the comments.

[sidneym]

Remove the blank line
Put a trap into the gap between the PLT header and plt0.
Update testcase

[sidneym]

ELF/Arch/Hexagon.cpp

235 ↗

(On Diff #167382)

Above should be a 0x0c, 0xdb, 0x00, 0x54 not 0x0c, 0xdb, 0x00, 0x52 I didn't git add that change prior to my format-patch.

[ruiu]

LGTM

ELF/Arch/Hexagon.cpp

250–251 ↗

(On Diff #167382)

Indentation of the comment.

[MaskRay]

test/ELF/hexagon-shared.s

2 ↗

(On Diff #167382)

Though not strictly required, object files are better suffixed with .o and shared objects .so

5 ↗

(On Diff #167382)

This test may not be affected but some might (it happened in the past for a few times)

When a t.so is used to link t. DT_SONAME of t.so will end up in the .dynstr section of t. Its length may change the section size sometimes. FileCheck on t may get different results on some systems.

For intermediate %t3 here, it'd be better to specify -soname t3.so to fix the length of its DT_SONAME.

[MaskRay]

test/ELF/hexagon-shared.s

5 ↗

(On Diff #167382)

DT_SONAME of t.so will end up in the .dynstr section of t

Correction: DT_SONAME (if exists) or filename

https://github.com/llvm-mirror/lld/tree/master/ELF/Driver.cpp#L232

// DSOs usually have DT_SONAME tags in their ELF headers, and the
// sonames are used to identify DSOs. But if they are missing,
// they are identified by filenames. We don't know whether the new
// file has a DT_SONAME or not because we haven't parsed it yet.
// Here, we set the default soname for the file because we might
// need it later.
//
// If a file was specified by -lfoo, the directory part is not
// significant, as a user did not specify it. This behavior is
// compatible with GNU.

%t is a temporary filename including a directory name, it may be of varying lengths.

[sidneym]

ELF/Arch/Hexagon.cpp

250–251 ↗

(On Diff #167382)

OK, <<2.

test/ELF/hexagon-shared.s

5 ↗

(On Diff #167382)

OK, I will commit using file extensions, .o and .so I will also add -soname to the link.

lld/trunk/ELF/Arch/Hexagon.cpp

 //===-- Hexagon.cpp -------------------------------------------------------===//
 //
 //                             The LLVM Linker
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "InputFiles.h"
 #include "Symbols.h"
+#include "SyntheticSections.h"
 #include "Target.h"
 #include "lld/Common/ErrorHandler.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/Object/ELF.h"
 #include "llvm/Support/Endian.h"
 
 using namespace llvm;
 using namespace llvm::object;
 using namespace llvm::support::endian;
 using namespace llvm::ELF;
 using namespace lld;
 using namespace lld::elf;
 
 namespace {
 class Hexagon final : public TargetInfo {
 public:
   Hexagon();
   uint32_t calcEFlags() const override;
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
   void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void writePltHeader(uint8_t *Buf) const override;
+  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+                int32_t Index, unsigned RelOff) const override;
 };
 } // namespace
 
 Hexagon::Hexagon() {
+  PltRel = R_HEX_JMP_SLOT;
+  RelativeRel = R_HEX_RELATIVE;
+  PltEntrySize = 16;
+  PltHeaderSize = 32;
+
   // Hexagon Linux uses 64K pages by default.
   DefaultMaxPageSize = 0x10000;
   NoneRel = R_HEX_NONE;
 }
 
 // Support V60 only at the moment.
 uint32_t Hexagon::calcEFlags() const { return 0x60; }
 

 RelExpr Hexagon::getRelExpr(RelType Type, const Symbol &S,
                             const uint8_t *Loc) const {
   switch (Type) {
   case R_HEX_B9_PCREL:
   case R_HEX_B9_PCREL_X:
   case R_HEX_B13_PCREL:
   case R_HEX_B15_PCREL:
   case R_HEX_B15_PCREL_X:
+  case R_HEX_6_PCREL_X:
+    return R_PC;
   case R_HEX_B22_PCREL:
   case R_HEX_B22_PCREL_X:
   case R_HEX_B32_PCREL_X:
-  case R_HEX_6_PCREL_X:
-    return R_PC;
+    return R_PLT_PC;
   default:
     return R_ABS;
   }
 }
 
 static uint32_t findMaskR6(uint32_t Insn) {
   // There are (arguably too) many relocation masks for the DSP's
   // R_HEX_6_X type.  The table below is used to select the correct mask
case R_HEX_10_X:
     or32le(Loc, applyMask(0x00203fe0, Val & 0x3f));
     break;
   case R_HEX_11_X:
     or32le(Loc, applyMask(findMaskR11(read32le(Loc)), Val & 0x3f));
     break;
   case R_HEX_12_X:
     or32le(Loc, applyMask(0x000007e0, Val));
     break;
-  case R_HEX_16_X:  // This reloc only has 6 effective bits.
+  case R_HEX_16_X: // This reloc only has 6 effective bits.
     or32le(Loc, applyMask(findMaskR16(read32le(Loc)), Val & 0x3f));
     break;
   case R_HEX_32:
     or32le(Loc, Val);
     break;
   case R_HEX_32_6_X:
     or32le(Loc, applyMask(0x0fff3fff, Val >> 6));
     break;
case R_HEX_LO16:
     or32le(Loc, applyMask(0x00c03fff, Val));
     break;
   default:
     error(getErrorLocation(Loc) + "unrecognized reloc " + toString(Type));
     break;
   }
 }
 
+void Hexagon::writePltHeader(uint8_t *Buf) const {
+  const uint8_t PltData[] = {
+      0x00, 0x40, 0x00, 0x00, // { immext (#0)
+      0x1c, 0xc0, 0x49, 0x6a, //   r28 = add (pc, ##GOT0@PCREL) } # @GOT0
+      0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16)  # offset of GOTn
+      0x4f, 0x40, 0x9c, 0x91, //   r15 = memw (r28 + #8)  # object ID at GOT2
+      0x3c, 0xc0, 0x9c, 0x91, //   r28 = memw (r28 + #4) }# dynamic link at GOT1
+      0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2)    # index of PLTn
+      0x00, 0xc0, 0x9c, 0x52, //   jumpr r28 }            # call dynamic linker
+      0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
+  };
+  memcpy(Buf, PltData, sizeof(PltData));
+
+  // offset from PLT0 to the GOT.
+  relocateOne(Buf, R_HEX_B32_PCREL_X, In.GotPlt->getVA() - In.Plt->getVA());
+  relocateOne(Buf + 4, R_HEX_6_PCREL_X,
+              In.GotPlt->getVA() - In.Plt->getVA());
+}
+void Hexagon::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+                       uint64_t PltEntryAddr, int32_t Index,
+                       unsigned RelOff) const {
+  const uint8_t Inst[] = {
+      0x00, 0x40, 0x00, 0x00, // { immext (#0)
+      0x0e, 0xc0, 0x49, 0x6a, //   r14 = add (pc, ##GOTn@PCREL) }
+      0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
+      0x00, 0xc0, 0x9c, 0x52, // jumpr r28
+  };
+  memcpy(Buf, Inst, sizeof(Inst));
+
+  relocateOne(Buf, R_HEX_B32_PCREL_X, GotPltEntryAddr - PltEntryAddr);
+  relocateOne(Buf + 4, R_HEX_6_PCREL_X, GotPltEntryAddr - PltEntryAddr);
+}
+
 TargetInfo *elf::getHexagonTargetInfo() {
   static Hexagon Target;
   return &Target;
 }

lld/trunk/ELF/Driver.cpp

static void setConfigs(opt::InputArgList &Args) {
   // In other words, Rela makes it easy to read addends at the price of extra
   // 4 or 8 byte for each relocation entry. We don't know why ELF defined two
   // different mechanisms in the first place, but this is how the spec is
   // defined.
   //
   // You cannot choose which one, Rel or Rela, you want to use. Instead each
   // ABI defines which one you need to use. The following expression expresses
   // that.
-  Config->IsRela = M == EM_AARCH64 || M == EM_AMDGPU || M == EM_PPC ||
-                   M == EM_PPC64 || M == EM_RISCV || M == EM_X86_64;
+  Config->IsRela = M == EM_AARCH64 || M == EM_AMDGPU || M == EM_HEXAGON ||
+                   M == EM_PPC || M == EM_PPC64 || M == EM_RISCV ||
+                   M == EM_X86_64;
 
   // If the output uses REL relocations we must store the dynamic relocation
   // addends to the output sections. We also store addends for RELA relocations
   // if --apply-dynamic-relocs is used.
   // We default to not writing the addends when using RELA relocations since
   // any standard conforming tool can find it in r_addend.
   Config->WriteAddends = Args.hasFlag(OPT_apply_dynamic_relocs,
                                       OPT_no_apply_dynamic_relocs, false) ||

lld/trunk/test/ELF/Inputs/hexagon-shared.s

+.global bar
+bar:
+   jumpr lr

lld/trunk/test/ELF/hexagon-shared.s

+# REQUIRES: hexagon
+# RUN: llvm-mc -filetype=obj -triple=hexagon-unknown-elf %s -o %t
+# RUN: llvm-mc -filetype=obj -triple=hexagon-unknown-elf %S/Inputs/hexagon-shared.s -o %t2.o
+# RUN: ld.lld -shared %t2.o -soname %t3.so -o %t3.so
+# RUN: ld.lld -shared %t %t3.so -soname %t4.so -o %t4.so
+# RUN: llvm-objdump -d -j .plt %t4.so | FileCheck %s
+
+.global foo
+foo:
+call ##bar
+
+# CHECK: { immext(#65472
+# CHECK: r28 = add(pc,##65520) }
+# CHECK: { r14 -= add(r28,#16)
+# CHECK: r15 = memw(r28+#8)
+# CHECK: r28 = memw(r28+#4) }
+# CHECK: { r14 = asr(r14,#2)
+# CHECK: jumpr r28 }
+# CHECK: { trap0(#219) }
+# CHECK: immext(#65472)
+# CHECK: r14 = add(pc,##65488) }
+# CHECK: r28 = memw(r14+#0) }
+# CHECK: jumpr r28 }