[PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1

[• wuzish]

Summary

Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. But the special condition is that the element number is 1, such as <1 x i128>. So just early exit to fix the assert.

[nemanjai]

Minor nit, but LGTM.

llvm/test/CodeGen/PowerPC/crash.ll

18 ↗

(On Diff #165419)

Please add a comment:

;  A BUILD_VECTOR of 1 element caused a crash in combineBVOfConsecutiveLoads().
; Test that this is no longer the case.

[• wuzish]

Add some comments in test cases.

[• wuzish]

Please help me to commit this patch. Thanks a lot.

[steven.zhang]

I will commit the patch for you.

[• wuzish]

In D52072#1240092, @steven.zhang wrote:

I will commit the patch for you.

Thank you

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) {
   bool IsRoundOfExtLoad = false;
 
   if (FirstInput.getOpcode() == ISD::FP_ROUND &&
       FirstInput.getOperand(0).getOpcode() == ISD::LOAD) {
     LoadSDNode *LD = dyn_cast<LoadSDNode>(FirstInput.getOperand(0));
     IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD;
   }
   // Not a build vector of (possibly fp_rounded) loads.
-  if (!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD)
+  if ((!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD) ||
+      N->getNumOperands() == 1)
     return SDValue();
 
   for (int i = 1, e = N->getNumOperands(); i < e; ++i) {
     // If any inputs are fp_round(extload), they all must be.
     if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND)
       return SDValue();
 
     SDValue NextInput = IsRoundOfExtLoad ? N->getOperand(i).getOperand(0) :

llvm/trunk/test/CodeGen/PowerPC/crash.ll

 
 if.then:
   ret void
 
 if.end:
   store i8 %bf.set, i8* %x3, align 4
   ret void
 }
+
+; A BUILD_VECTOR of 1 element caused a crash in combineBVOfConsecutiveLoads()
+; Test that this is no longer the case
+define signext i32 @test2() {
+entry:
+  %retval = alloca i32, align 4
+  %__a = alloca i128, align 16
+  %b = alloca i64, align 8
+  store i32 0, i32* %retval, align 4
+  %0 = load i128, i128* %__a, align 16
+  %splat.splatinsert = insertelement <1 x i128> undef, i128 %0, i32 0
+  %splat.splat = shufflevector <1 x i128> %splat.splatinsert, <1 x i128> undef, <1 x i32> zeroinitializer
+  %1 = bitcast <1 x i128> %splat.splat to <2 x i64>
+  %2 = extractelement <2 x i64> %1, i32 0
+  store i64 %2, i64* %b, align 8
+  ret i32 0
+}