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Differential D51954

AMDGPU: Print all kernel descriptor directives (including the ones with default values)
ClosedPublic

Authored by kzhuravl on Sep 11 2018, 3:24 PM.

Details

Reviewers
scott.linder
t-tye
arsenm
Commits
rG6e551e0e49be: AMDGPU: Print all kernel descriptor directives (including the ones with default…
rL342077: AMDGPU: Print all kernel descriptor directives (including the ones with default…
Summary

Change by @t-tye

Diff Detail

Repository
rL LLVM

Event Timeline

kzhuravl created this revision.Sep 11 2018, 3:24 PM
Herald added subscribers: tpr, dstuttard, yaxunl and 4 others. · View Herald TranscriptSep 11 2018, 3:24 PM
scott.linder added a reviewer: arsenm.Sep 11 2018, 3:48 PM

LGTM, but adding Matt because I think he was the one to originally request eliding defaulted fields. From what Tony described I agree we can't do this generally because of options which depend on attributes, e.g. -mattr=+/-xnack changes the "default".

This revision was not accepted when it landed; it landed in state Needs Review.Sep 12 2018, 1:27 PM
Closed by commit rL342077: AMDGPU: Print all kernel descriptor directives (including the ones with default… (authored by kzhuravl). · Explain Why
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
MCTargetDesc/
189 lines
test/
MC/
AMDGPU/
10 lines

Diff 165141

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Linesbool AMDGPUTargetAsmStreamer::EmitPALMetadata(
OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n'; OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n';
return true; return true;
} }
void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
const MCSubtargetInfo &STI, StringRef KernelName, const MCSubtargetInfo &STI, StringRef KernelName,
const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR, const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) { bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
amdhsa::kernel_descriptor_t DefaultKD = getDefaultAmdhsaKernelDescriptor();
IsaVersion IVersion = getIsaVersion(STI.getCPU()); IsaVersion IVersion = getIsaVersion(STI.getCPU());
OS << "\t.amdhsa_kernel " << KernelName << '\n'; OS << "\t.amdhsa_kernel " << KernelName << '\n';
#define PRINT_IF_NOT_DEFAULT(STREAM, DIRECTIVE, KERNEL_DESC, \ #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
DEFAULT_KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
if (AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) != \
AMDHSA_BITS_GET(DEFAULT_KERNEL_DESC.MEMBER_NAME, FIELD_NAME)) \
STREAM << "\t\t" << DIRECTIVE << " " \ STREAM << "\t\t" << DIRECTIVE << " " \
<< AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n'; << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
if (KD.group_segment_fixed_size != DefaultKD.group_segment_fixed_size)
OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
<< '\n'; << '\n';
if (KD.private_segment_fixed_size != DefaultKD.private_segment_fixed_size)
OS << "\t\t.amdhsa_private_segment_fixed_size " OS << "\t\t.amdhsa_private_segment_fixed_size "
<< KD.private_segment_fixed_size << '\n'; << KD.private_segment_fixed_size << '\n';
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, DefaultKD,
kernel_code_properties, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
kernel_code_properties, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_user_sgpr_queue_ptr", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
kernel_code_properties, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, DefaultKD,
kernel_code_properties, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_user_sgpr_dispatch_id", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
kernel_code_properties, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, DefaultKD,
kernel_code_properties, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
OS, ".amdhsa_user_sgpr_private_segment_size", KD, DefaultKD,
kernel_code_properties, kernel_code_properties,
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(
OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, DefaultKD, OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_info", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_vgpr_workitem_id", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
// These directives are required. // These directives are required.
OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n'; OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n'; OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
if (!ReserveVCC) if (!ReserveVCC)
OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n'; OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
if (IVersion.Major >= 7 && !ReserveFlatScr) if (IVersion.Major >= 7 && !ReserveFlatScr)
OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n'; OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI)) if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI))
OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n'; OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n';
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_round_mode_32", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
compute_pgm_rsrc1, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_round_mode_16_64", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
compute_pgm_rsrc1, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_denorm_mode_32", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
compute_pgm_rsrc1, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_denorm_mode_16_64", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
compute_pgm_rsrc1, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_dx10_clamp", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
compute_pgm_rsrc1, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_ieee_mode", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
compute_pgm_rsrc1, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
if (IVersion.Major >= 9) if (IVersion.Major >= 9)
PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_fp16_overflow", KD, DefaultKD, PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
compute_pgm_rsrc1, compute_pgm_rsrc1,
amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL); amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(
OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, DefaultKD, OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
OS, ".amdhsa_exception_fp_denorm_src", KD, DefaultKD, compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(
OS, ".amdhsa_exception_fp_ieee_div_zero", KD, DefaultKD, OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
OS, ".amdhsa_exception_fp_ieee_overflow", KD, DefaultKD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
OS, ".amdhsa_exception_fp_ieee_underflow", KD, DefaultKD,
compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
OS, ".amdhsa_exception_fp_ieee_inexact", KD, DefaultKD, compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
PRINT_IF_NOT_DEFAULT( PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
OS, ".amdhsa_exception_int_div_zero", KD, DefaultKD, compute_pgm_rsrc2, compute_pgm_rsrc2,
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
#undef PRINT_IF_NOT_DEFAULT #undef PRINT_FIELD
OS << "\t.end_amdhsa_kernel\n"; OS << "\t.end_amdhsa_kernel\n";
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AMDGPUTargetELFStreamer // AMDGPUTargetELFStreamer
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 206 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AMDGPU/hsa-v3.s

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
// values are omitted. // values are omitted.
.p2align 6 .p2align 6
.amdhsa_kernel minimal .amdhsa_kernel minimal
.amdhsa_next_free_vgpr 0 .amdhsa_next_free_vgpr 0
.amdhsa_next_free_sgpr 0 .amdhsa_next_free_sgpr 0
.end_amdhsa_kernel .end_amdhsa_kernel
// ASM: .amdhsa_kernel minimal // ASM: .amdhsa_kernel minimal
// ASM-NEXT: .amdhsa_next_free_vgpr 0 // ASM: .amdhsa_next_free_vgpr 0
// ASM-NEXT: .amdhsa_next_free_sgpr 0 // ASM-NEXT: .amdhsa_next_free_sgpr 0
// ASM-NEXT: .end_amdhsa_kernel // ASM: .end_amdhsa_kernel
// Test that we can specify all available directives with non-default values. // Test that we can specify all available directives with non-default values.
.p2align 6 .p2align 6
.amdhsa_kernel complete .amdhsa_kernel complete
.amdhsa_group_segment_fixed_size 1 .amdhsa_group_segment_fixed_size 1
.amdhsa_private_segment_fixed_size 1 .amdhsa_private_segment_fixed_size 1
.amdhsa_user_sgpr_private_segment_buffer 1 .amdhsa_user_sgpr_private_segment_buffer 1
.amdhsa_user_sgpr_dispatch_ptr 1 .amdhsa_user_sgpr_dispatch_ptr 1
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines.amdhsa_kernel special_sgpr
.amdhsa_float_denorm_mode_16_64 0 .amdhsa_float_denorm_mode_16_64 0
.amdhsa_dx10_clamp 0 .amdhsa_dx10_clamp 0
.amdhsa_ieee_mode 0 .amdhsa_ieee_mode 0
.amdhsa_next_free_vgpr 0 .amdhsa_next_free_vgpr 0
.end_amdhsa_kernel .end_amdhsa_kernel
// ASM: .amdhsa_kernel special_sgpr // ASM: .amdhsa_kernel special_sgpr
// ASM-NEXT: .amdhsa_next_free_vgpr 0 // ASM: .amdhsa_next_free_vgpr 0
// ASM-NEXT: .amdhsa_next_free_sgpr 27 // ASM-NEXT: .amdhsa_next_free_sgpr 27
// ASM-NEXT: .amdhsa_reserve_vcc 0 // ASM-NEXT: .amdhsa_reserve_vcc 0
// ASM-NEXT: .amdhsa_reserve_xnack_mask 0 // ASM-NEXT: .amdhsa_reserve_xnack_mask 0
// ASM-NEXT: .amdhsa_float_denorm_mode_16_64 0 // ASM: .amdhsa_float_denorm_mode_16_64 0
// ASM-NEXT: .amdhsa_dx10_clamp 0 // ASM-NEXT: .amdhsa_dx10_clamp 0
// ASM-NEXT: .amdhsa_ieee_mode 0 // ASM-NEXT: .amdhsa_ieee_mode 0
// ASM-NEXT: .end_amdhsa_kernel // ASM: .end_amdhsa_kernel
.section .foo .section .foo
.byte .amdgcn.gfx_generation_number .byte .amdgcn.gfx_generation_number
// ASM: .byte 9 // ASM: .byte 9
.byte .amdgcn.next_free_vgpr .byte .amdgcn.next_free_vgpr
// ASM: .byte 0 // ASM: .byte 0
Show All 24 Lines