[Arm builtins] Remove non-necessary IS check

[hug-dev]

Summary

This patch removes the instruction set check to make the msr APSR_nzcvq,
ip instruction only execute if Thumb2 is used.
The APSR is a subset of the bits of the CPSR
(B.1.3.3 of the Arm v7 A and R ARM [1]) and is only available for A and
R profiles.
However in section B.9.3.11 of the same document we see that:

• "In the A and R profiles, APSR_nzcvq is the same as CPSR_f"
• "ARM recommends the APSR forms when only the N, Z, C, V, Q, and GE[3:0] bits are being written."

This patch also make those files assemble for Armv8-M Mainline
architecture profile.

The builtins were cross-compiled for Arm, Aarch64 and Armv6-M, Armv7-M
and Armv7E-M targets.
Cross-compiled tests were executed for Arm target.

[1]: https://developer.arm.com/docs/ddi0406/latest/arm-architecture-reference-manual-armv7-a-and-armv7-r-edition

[peter.smith]

I agree that we should be using APSR_nzcvq rather than CPSR_f as both assemble to the same instruction encoding (they disassemble to APSR_nzcvq). I think it is worth seeing if there are any objections to removing the case for ARM state msr CPSR_f, #APSR_C as it saves one instruction. Overall looking good to me though.

lib/builtins/arm/aeabi_cdcmp.S

57

We are going from 1 instruction in ARM state to two here (only ARM state supports the msr register, immediate form). Personally I think the simplicity of having a single code sequence outweighs having an extra instruction as I suspect the majority of people are using Thumb2. If there is anyone that prefers the immediate form it will be worth changing msr CPSR_F, #APSR_C to msr APSR_nzcvq, #APSR_C.

[hug-dev]

Ping! I do not mind updating the patch to use 1 instruction instead of 2, as Peter said, if anyone prefers that.

[peter.smith]

In D51854#1240515, @hug-dev wrote:

Ping! I do not mind updating the patch to use 1 instruction instead of 2, as Peter said, if anyone prefers that.

While I personally don't mind the patch is, I think that if there are no other approvals it is safer to update the patch to use 1 instruction instead of 2. What I suggest is to wait to see if there are any approvals by the end of the week and if not, then update the patch to use 1 instruction and I'll approve.

[hug-dev]

Update the patch to use 1 instruction instead of 2 for Arm state as suggested by @peter.smith

[peter.smith]

Looks good to me, thanks for the update.

[hug-dev]

Thanks Peter! As I don't have commit access, can I ask for someone to commit this on my behalf?

[peter.smith]

In D51854#1252572, @hug-dev wrote:

Thanks Peter! As I don't have commit access, can I ask for someone to commit this on my behalf?

I'll do it tomorrow morning if no-one else beats me to it.

[kristina]

In D51854#1252577, @peter.smith wrote:

In D51854#1252572, @hug-dev wrote:

Thanks Peter! As I don't have commit access, can I ask for someone to commit this on my behalf?

I'll do it tomorrow morning if no-one else beats me to it.

I don't mind doing it.

[peter.smith]

In D51854#1252612, @kristina wrote:

In D51854#1252577, @peter.smith wrote:

In D51854#1252572, @hug-dev wrote:

Thanks Peter! As I don't have commit access, can I ask for someone to commit this on my behalf?

I'll do it tomorrow morning if no-one else beats me to it.

I don't mind doing it.

Sure please do, I'm likely to leave the office soon so I don't want to have to watch the bots to make sure I've not broken anything.

[hug-dev]

Thank you all!

lib/builtins/arm/aeabi_cdcmp.S

#else
         // Use "it ne" + unconditional branch to guarantee a supported relocation if
         // __aeabi_cdcmple is in a different section for some builds.
         IT(ne)
         bne __aeabi_cdcmple
 
 #if defined(USE_THUMB_2)
         mov ip, #APSR_C
         msr APSR_nzcvq, ip
 #else
-        msr CPSR_f, #APSR_C
+        msr APSR_nzcvq, #APSR_C
 #endif
         JMP(lr)
 #endif
 END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
 
 
 // void __aeabi_cdcmple(double a, double b) {
 //   if (__aeabi_dcmplt(a, b)) {
#else
         ldm sp, {r0-r3}
         bl __aeabi_dcmpeq
         cmp r0, #1
         ITE(eq)
         moveq ip, #(APSR_C | APSR_Z)
         movne ip, #(APSR_C)
 
 1:
-#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
         msr APSR_nzcvq, ip
-#else
-        msr CPSR_f, ip
-#endif
         pop {r0-r3}
         POP_PC()
 #endif
 END_COMPILERRT_FUNCTION(__aeabi_cdcmple)
 
 // int __aeabi_cdrcmple(double a, double b) {
 //   return __aeabi_cdcmple(b, a);
 // }

lib/builtins/arm/aeabi_cfcmp.S

#else
         // __aeabi_cfcmple is in a different section for some builds.
         IT(ne)
         bne __aeabi_cfcmple
 
 #if defined(USE_THUMB_2)
         mov ip, #APSR_C
         msr APSR_nzcvq, ip
 #else
-        msr CPSR_f, #APSR_C
+        msr APSR_nzcvq, #APSR_C
 #endif
         JMP(lr)
 #endif
 END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
 
 
 // void __aeabi_cfcmple(float a, float b) {
 //   if (__aeabi_fcmplt(a, b)) {
#else
         ldm sp, {r0-r3}
         bl __aeabi_fcmpeq
         cmp r0, #1
         ITE(eq)
         moveq ip, #(APSR_C | APSR_Z)
         movne ip, #(APSR_C)
 
 1:
-#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
         msr APSR_nzcvq, ip
-#else
-        msr CPSR_f, ip
-#endif
         pop {r0-r3}
         POP_PC()
 #endif
 END_COMPILERRT_FUNCTION(__aeabi_cfcmple)
 
 // int __aeabi_cfrcmple(float a, float b) {
 //   return __aeabi_cfcmple(b, a);
 // }