[WebAssembly] Made assembler only use stack instruction tablegen defs

[aardappel]

Summary

This ensures we have the non-register version of the instruction.

The stack version of call_indirect now wants a type index argument,
so that has been added in the existing tests.

Tested:
llvm-lit -v find test -name WebAssembly

[dschuff]

LGTM to ensure we are using the stack instructions.
It's unfortunate about the type index requirement. That will make it quite a pain to hand-write assembly files. It would be nice if we could eventually figure out a way to symbolize those like the wat format.

[jgravelle-google]

utils/TableGen/AsmMatcherEmitter.cpp

1482 ↗

(On Diff #163938)

nit: maybe IsWebAssemblyTarget? On first read I'd assumed that WebAssemblyTarget was the string "WebAssembly" and I was confused what Target.getName() was doing in this expression

[aardappel]

@dschuff I could also remove the type index argument from the table-gen defs for now, if you think that is better. Though a future assembler can possibly allow parsing symbolic operands and turn them into integers if it has seen a previous type declaration?

[aardappel]

Addressed review comment.

[tlively]

Would setting the isCodeGenOnly on the non-stack instructions accomplish this as well?

[aardappel]

@tlively that is entirely possible, I'll give it a go.

llvm/trunk/test/MC/WebAssembly/basic-assembly.s

test0:
     i32.ge_s
     br_if       0        # 0: down to label0
 .LBB0_1:
     loop             # label1:
     call        something1@FUNCTION
     i64.const   1234
     i32.call    something2@FUNCTION
     i32.const   0
-    call_indirect
+    call_indirect 0
     i32.const   1
     i32.add
     tee_local   0
     get_local   0
     i32.lt_s
     br_if       0        # 0: up to label1
 .LBB0_2:
     end_loop

 # CHECK-NEXT:      i32.ge_s
 # CHECK-NEXT:      br_if 0            # 0: down to label0
 # CHECK-NEXT:  .LBB0_1:
 # CHECK-NEXT:      loop                    # label1:
 # CHECK-NEXT:      call        something1@FUNCTION
 # CHECK-NEXT:      i64.const   1234
 # CHECK-NEXT:      i32.call    something2@FUNCTION
 # CHECK-NEXT:      i32.const   0
-# CHECK-NEXT:      call_indirect
+# CHECK-NEXT:      call_indirect 0
 # CHECK-NEXT:      i32.const   1
 # CHECK-NEXT:      i32.add
 # CHECK-NEXT:      tee_local   0
 # CHECK-NEXT:      get_local   0
 # CHECK-NEXT:      i32.lt_s
 # CHECK-NEXT:      br_if 0            # 0: up to label1
 # CHECK-NEXT:  .LBB0_2:
 # CHECK-NEXT:      end_loop
 # CHECK-NEXT:      end_block                       # label0:
 # CHECK-NEXT:      get_local   4
 # CHECK-NEXT:      get_local   5
 # CHECK-NEXT:      f32x4.add
 # CHECK-NEXT:      end_function

llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp

for (const auto &Pair : SubtargetFeatures)
     LLVM_DEBUG(Pair.second.dump());
 #endif // NDEBUG
   assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
 
   bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
   bool ReportMultipleNearMisses =
       AsmParser->getValueAsBit("ReportMultipleNearMisses");
 
+  bool IsWebAssemblyTarget = Target.getName() == "WebAssembly";
+
   // Parse the instructions; we need to do this first so that we can gather the
   // singleton register classes.
   SmallPtrSet<Record*, 16> SingletonRegisters;
   unsigned VariantCount = Target.getAsmParserVariantCount();
   for (unsigned VC = 0; VC != VariantCount; ++VC) {
     Record *AsmVariant = Target.getAsmParserVariant(VC);
     StringRef CommentDelimiter =
         AsmVariant->getValueAsString("CommentDelimiter");
for (const CodeGenInstruction *CGI : Target.getInstructionsByEnumValue()) {
       if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
         continue;
 
       // Ignore instructions for different instructions
       StringRef V = CGI->TheDef->getValueAsString("AsmVariantName");
       if (!V.empty() && V != Variant.Name)
         continue;
 
+      // [WebAssembly] Ignore non-stack instructions.
+      if (IsWebAssemblyTarget) {
+        auto Bit = CGI->TheDef->getValue("StackBased")->getValue()->
+                     getCastTo(BitRecTy::get());
+        if (!Bit || !reinterpret_cast<const BitInit *>(Bit)->getValue())
+          continue;
+      }
+
       auto II = llvm::make_unique<MatchableInfo>(*CGI);
 
       II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
 
       // Ignore instructions which shouldn't be matched and diagnose invalid
       // instruction definitions with an error.
       if (!II->validate(CommentDelimiter, false))
         continue;