[WebAssembly][NFC] Fix formatting and tests

[tlively]

Summary

Small fixes

[tlively]

• move test for consistency of test order

[tlively]

• Fix broken test

[tlively]

• One last small tweak

This should be ready for real now.

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

def _u : PatFrag<(ops node:$vec, node:$idx),
                        node:$idx
                      )),
                      (i32 mask)
                    ))>;
 }
 defm extract_i8x16 : ExtractPat<i8, 0xff>;
 defm extract_i16x8 : ExtractPat<i16, 0xffff>;
 multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
-  defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32,  baseInst, sign,
+  defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign,
                         !cast<PatFrag>("extract_i8x16"#sign)>;
   defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 2), sign,
                         !cast<PatFrag>("extract_i16x8"#sign)>;
 }
 multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
                        WebAssemblyRegClass reg_t, ValueType lane_t,
                        bits<32> simdop> {
   defm REPLACE_LANE_#vec_t :

llvm/trunk/test/CodeGen/WebAssembly/simd.ll

 define <16 x i8> @splat_v16i8(i8 %x) {
   %v = insertelement <16 x i8> undef, i8 %x, i32 0
   %res = shufflevector <16 x i8> %v, <16 x i8> undef,
     <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
                 i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i8> %res
 }
 
-; CHECK-LABEL: const_splat_v16i8
+; CHECK-LABEL: const_splat_v16i8:
 ; SIMD128; i8x16.splat
 define <16 x i8> @const_splat_v16i8() {
   ret <16 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
                  i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
 }
 
 ; CHECK-LABEL: extract_v16i8_s:
 ; NO-SIMD128-NOT: i8x16

 ; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
 define <4 x i32> @splat_v4i32(i32 %x) {
   %v = insertelement <4 x i32> undef, i32 %x, i32 0
   %res = shufflevector <4 x i32> %v, <4 x i32> undef,
     <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x i32> %res
 }
 
-; CHECK-LABEL: const_splat_v4i32
+; CHECK-LABEL: const_splat_v4i32:
 ; SIMD128; i32x4.splat
 define <4 x i32> @const_splat_v4i32() {
   ret <4 x i32> <i32 42, i32 42, i32 42, i32 42>
 }
 
 ; CHECK-LABEL: extract_v4i32:
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128: .param v128{{$}}

 ; SIMD128: i64x2.splat $push0=, $0 # encoding: [0xfd,0x06]{{$}}
 ; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
 define <2 x i64> @splat_v2i64(i64 %x) {
   %t1 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
   %res = insertelement <2 x i64> %t1, i64 %x, i32 1
   ret <2 x i64> %res
 }
 
+; CHECK-LABEL: const_splat_v2i64:
+; SIMD128; i64x2.splat
+define <2 x i64> @const_splat_v2i64() {
+  ret <2 x i64> <i64 42, i64 42>
+}
+
 ; CHECK-LABEL: extract_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result i64{{$}}
 ; SIMD128: i64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x0e,0x01]{{$}}
 ; SIMD128: return $pop0 #
 define i64 @extract_v2i64(<2 x i64> %v) {
   %elem = extractelement <2 x i64> %v, i64 1
   ret i64 %elem
 }
 
 ; CHECK-LABEL: replace_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128, i64{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i64x2.replace_lane $push0=, $0, 0, $1 # encoding: [0xfd,0x14,0x00]{{$}}
 ; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
 define <2 x i64> @replace_v2i64(<2 x i64> %v, i64 %x) {
   %res = insertelement <2 x i64> %v, i64 %x, i32 0
   ret <2 x i64> %res
 }
 
-define <2 x i64> @const_splat_v2i64() {
-  ret <2 x i64> <i64 42, i64 42>
-}
-
 ; CHECK-LABEL: build_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param i64, i64{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i64x2.splat $push0=, $0 # encoding: [0xfd,0x06]
 ; SIMD128: i64x2.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x14,0x01]
 ; SIMD128: return $pop1 # encoding: [0x0f]