[mips][microMIPS] Implement ANDI16 instruction

[jkolek]

Summary

Implement 16-bit microMIPS instruction ANDI16.

[sstankovic]

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

797

I think the code will be more readable if you write operand values in decimal.

lib/Target/Mips/MicroMipsInstrInfo.td

150

Is isCommutable allowed to be 1 when one operand is register and the other is immediate? MipsInstrInfo.td doesn't seem to do that for MIPS32.

[sstankovic]

LGTM

Closed by commit rL221351 (authored by zjovanovic).

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

               ((Imm % 4 == 0) && Imm < 28 && Imm > 0)))
           return Error(IDLoc, "immediate operand value out of range");
         break;
+      case Mips::ANDI16_MM:
+        Opnd = Inst.getOperand(2);
+        if (!Opnd.isImm())
+          return Error(IDLoc, "expected immediate operand kind");
+        Imm = Opnd.getImm();
+        if (!(Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
+              Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
+              Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535))
+          return Error(IDLoc, "immediate operand value out of range");
+        break;
     }
   }
 

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

   unsigned getLoadImm7Value(const MCInst &MI, unsigned OpNo,
                             SmallVectorImpl<MCFixup> &Fixups,
                             const MCSubtargetInfo &STI) const;
+  unsigned getAndImm4Value(const MCInst &MI, unsigned OpNo,
+                           SmallVectorImpl<MCFixup> &Fixups,
+                           const MCSubtargetInfo &STI) const;
 
   unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
                           const MCSubtargetInfo &STI) const;

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

   return Value & 0x7f;
 }
 
+unsigned
+MipsMCCodeEmitter::getAndImm4Value(const MCInst &MI, unsigned OpNo,
+                                   SmallVectorImpl<MCFixup> &Fixups,
+                                   const MCSubtargetInfo &STI) const {
+  assert(MI.getOperand(OpNo).isImm());
+  const MCOperand &MO = MI.getOperand(OpNo);
+  unsigned Value = MO.getImm();
+  switch (Value) {
+    case 0x80:    return 0x0;
+    case 0x1:     return 0x1;
+    case 0x2:     return 0x2;
+    case 0x3:     return 0x3;
+    case 0x4:     return 0x4;
+    case 0x7:     return 0x5;
+    case 0x8:     return 0x6;
+    case 0xf:     return 0x7;
+    case 0x10:    return 0x8;
+    case 0x1f:    return 0x9;
+    case 0x20:    return 0xa;
+    case 0x3f:    return 0xb;
+    case 0x40:    return 0xc;
+    case 0xff:    return 0xd;
+    case 0x8000:  return 0xe;
+    case 0xffff:  return 0xf;
+    default:      assert(0 && "Unexpected value");
+  }
+}
+
 #include "MipsGenMCCodeEmitter.inc"

lib/Target/Mips/MicroMipsInstrFormats.td

   let Inst{0}     = funct;
 }
 
+class ANDI_FM_MM16<bits<6> funct> {
+  bits<3> rd;
+  bits<3> rs;
+  bits<4> imm;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = funct;
+  let Inst{9-7}   = rd;
+  let Inst{6-4}   = rs;
+  let Inst{3-0}   = imm;
+}
+
 class LOGIC_FM_MM16<bits<4> funct> {
   bits<3> rt;
   bits<3> rs;

lib/Target/Mips/MicroMipsInstrInfo.td

   let EncoderMethod = "getImm5Shr2Value";
 }
 
+def andi_imm4 : Operand<i32> {
+  let EncoderMethod = "getAndImm4Value";
+}
+
 def addiur1sp_imm : Operand<i32> {
   let EncoderMethod = "getAddiur1SPValue";
 }

   let isCommutable = isComm;
 }
 
+class AndImmMM16<string opstr, RegisterOperand RO,
+                 InstrItinClass Itin = NoItinerary,
+                 SDPatternOperator OpNode = null_frag> :
+  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, andi_imm4:$imm),
+                  !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI> {
+  let isCommutable = 1;
+}
+
 class LogicRMM16<string opstr, RegisterOperand RO,
                  InstrItinClass Itin = NoItinerary,
                  SDPatternOperator OpNode = null_frag> :

                 ARITH_FM_MM16<0>;
 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
                 ARITH_FM_MM16<1>;
+def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND, and>,
+               ANDI_FM_MM16<0x0b>;
 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
                LOGIC_FM_MM16<0x2>;
 def OR16_MM  : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,

lib/Target/Mips/MipsCodeEmitter.cpp

   unsigned getSimm18Lsl3Encoding(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getEncodedShiftImm(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getLoadImm7Value(const MachineInstr &MI, unsigned OpNo) const;
+  unsigned getAndImm4Value(const MachineInstr &MI, unsigned OpNo) const;
 
   /// Expand pseudo instructions with accumulator register operands.
   void expandACCInstr(MachineBasicBlock::instr_iterator MI,

   return 0;
 }
 
+unsigned MipsCodeEmitter::getAndImm4Value(const MachineInstr &MI,
+                                          unsigned OpNo) const {
+  llvm_unreachable("Unimplemented function.");
+  return 0;
+}
+
 /// getMachineOpValue - Return binary encoding of operand. If the machine
 /// operand requires relocation, record the relocation and return zero.
 unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,

test/MC/Mips/micromips-16-bit-instructions.s

 #------------------------------------------------------------------------------
 # CHECK-EL: addu16  $6, $17, $4     # encoding: [0x42,0x07]
 # CHECK-EL: subu16  $5, $16, $3     # encoding: [0xb1,0x06]
+# CHECK-EL: andi16  $16, $2, 31     # encoding: [0x29,0x2c]
 # CHECK-EL: and16   $16, $2         # encoding: [0x82,0x44]
 # CHECK-EL: not16   $17, $3         # encoding: [0x0b,0x44]
 # CHECK-EL: or16    $16, $4         # encoding: [0xc4,0x44]

 #------------------------------------------------------------------------------
 # CHECK-EB: addu16  $6, $17, $4     # encoding: [0x07,0x42]
 # CHECK-EB: subu16  $5, $16, $3     # encoding: [0x06,0xb1]
+# CHECK-EB: andi16  $16, $2, 31     # encoding: [0x2c,0x29]
 # CHECK-EB: and16   $16, $2         # encoding: [0x44,0x82]
 # CHECK-EB: not16   $17, $3         # encoding: [0x44,0x0b]
 # CHECK-EB: or16    $16, $4         # encoding: [0x44,0xc4]

 
     addu16  $6, $17, $4
     subu16  $5, $16, $3
+    andi16  $16, $2, 31
     and16   $16, $2
     not16   $17, $3
     or16    $16, $4

test/MC/Mips/micromips-invalid.s

 
   addu16  $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   subu16  $5, $16, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  andi16  $16, $10, 0x1f # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  andi16  $16, $2, 17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   and16   $16, $8   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   not16   $18, $9   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   or16    $16, $10  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction