[ARM] Tighten f64<->f16 conversion requirements

[bogden]

Summary

Some uses of FullFP16Pat and FP16Pat were missing
needed Requires field.

It seems that in practice this never caused a problem.
There is no full FP16 supporting target that does not
support the relevant instructions, so FullFP16Pat did
not introduce any bug.

ARM v8-R does not support the relevant instructions if
it does not support single-precision. In this case the
FP16Pat can match when it should not, but this does
not matter because ARMISelLowering.cpp has an Extend
that effectively enforces the requirements.

AArch64 does not come into play because 8-R is the only
target where there can be a problem.

[t.p.northover]

LGTM!

llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
   bits<5> Sm;
 
   // Encode instruction operands.
   let Inst{3-0} = Sm{4-1};
   let Inst{5}   = Sm{0};
 }
 
 def : FullFP16Pat<(f64 (fpextend HPR:$Sm)),
-                  (VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))>;
+                  (VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))>,
+                  Requires<[HasFPARMv8, HasDPVFP]>;
 def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
-              (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
+              (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
+              Requires<[HasFPARMv8, HasDPVFP]>;
 
 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
                    (outs SPR:$Sd), (ins DPR:$Dm),
                    NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
                    [/* Intentionally left blank, see patterns below */]>,
                    Requires<[HasFPARMv8, HasDPVFP]> {
   // Instruction operands.
   bits<5> Sd;
   bits<5> Dm;
 
   // Encode instruction operands.
   let Inst{3-0}     = Dm{3-0};
   let Inst{5}       = Dm{4};
   let Inst{15-12}   = Sd{4-1};
   let Inst{22}      = Sd{0};
 }
 
 def : FullFP16Pat<(f16 (fpround DPR:$Dm)),
-                  (COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>;
+                  (COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>,
+                  Requires<[HasFPARMv8, HasDPVFP]>;
 def : FP16Pat<(fp_to_f16 (f64 DPR:$a)),
-              (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
+              (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>,
+                   Requires<[HasFPARMv8, HasDPVFP]>;
 
 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
                    (outs DPR:$Dd), (ins SPR:$Sm),
                    NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
                    []>, Requires<[HasFPARMv8, HasDPVFP]> {
   // Instruction operands.
   bits<5> Sm;
 

llvm/trunk/test/CodeGen/ARM/fpconv.ll

 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
 ; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s
+; RUN: llc -mtriple=armv8r-none-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-VFP
+; RUN: llc -mtriple=armv8r-none-none-eabi -mattr=+fp-only-sp %s -o - | FileCheck %s --check-prefix=CHECK-VFP-SP
 
 define float @f1(double %x) {
 ;CHECK-VFP-LABEL: f1:
 ;CHECK-VFP: vcvt.f32.f64
+;CHECK-VFP-SP-LABEL: f1:
+;CHECK-VFP-SP: bl __aeabi_d2f
 ;CHECK-LABEL: f1:
 ;CHECK: truncdfsf2
 entry:
   %tmp1 = fptrunc double %x to float    ; <float> [#uses=1]
   ret float %tmp1
 }
 
 define double @f2(float %x) {
 ;CHECK-VFP-LABEL: f2:
 ;CHECK-VFP: vcvt.f64.f32
+;CHECK-VFP-SP-LABEL: f2:
+;CHECK-VFP-SP: bl __aeabi_f2d
 ;CHECK-LABEL: f2:
 ;CHECK: extendsfdf2
 entry:
   %tmp1 = fpext float %x to double    ; <double> [#uses=1]
   ret double %tmp1
 }
 
 define i32 @f3(float %x) {
 ;CHECK-VFP-LABEL: f3:
 ;CHECK-VFP: vcvt.s32.f32
+;CHECK-VFP-SP-LABEL: f3:
+;CHECK-VFP-SP: vcvt.s32.f32
 ;CHECK-LABEL: f3:
 ;CHECK: fixsfsi
 entry:
   %tmp = fptosi float %x to i32   ; <i32> [#uses=1]
   ret i32 %tmp
 }
 
 define i32 @f4(float %x) {
 ;CHECK-VFP-LABEL: f4:
 ;CHECK-VFP: vcvt.u32.f32
+;CHECK-VFP-SP-LABEL: f4:
+;CHECK-VFP-SP: vcvt.u32.f32
 ;CHECK-LABEL: f4:
 ;CHECK: fixunssfsi
 entry:
   %tmp = fptoui float %x to i32   ; <i32> [#uses=1]
   ret i32 %tmp
 }
 
 define i32 @f5(double %x) {
 ;CHECK-VFP-LABEL: f5:
 ;CHECK-VFP: vcvt.s32.f64
+;CHECK-VFP-SP-LABEL: f5:
+;CHECK-VFP-SP: bl __aeabi_d2iz
 ;CHECK-LABEL: f5:
 ;CHECK: fixdfsi
 entry:
   %tmp = fptosi double %x to i32    ; <i32> [#uses=1]
   ret i32 %tmp
 }
 
 define i32 @f6(double %x) {
 ;CHECK-VFP-LABEL: f6:
 ;CHECK-VFP: vcvt.u32.f64
+;CHECK-VFP-SP-LABEL: f6:
+;CHECK-VFP-SP: bl __aeabi_d2uiz
 ;CHECK-LABEL: f6:
 ;CHECK: fixunsdfsi
 entry:
   %tmp = fptoui double %x to i32    ; <i32> [#uses=1]
   ret i32 %tmp
 }
 
 define float @f7(i32 %a) {
 ;CHECK-VFP-LABEL: f7:
 ;CHECK-VFP: vcvt.f32.s32
+;CHECK-VFP-SP-LABEL: f7:
+;CHECK-VFP-SP: vcvt.f32.s32
 ;CHECK-LABEL: f7:
 ;CHECK: floatsisf
 entry:
   %tmp = sitofp i32 %a to float   ; <float> [#uses=1]
   ret float %tmp
 }
 
 define double @f8(i32 %a) {
 ;CHECK-VFP-LABEL: f8:
 ;CHECK-VFP: vcvt.f64.s32
+;CHECK-VFP-SP-LABEL: f8:
+;CHECK-VFP-SP: bl __aeabi_i2d
 ;CHECK-LABEL: f8:
 ;CHECK: floatsidf
 entry:
   %tmp = sitofp i32 %a to double    ; <double> [#uses=1]
   ret double %tmp
 }
 
 define float @f9(i32 %a) {
 ;CHECK-VFP-LABEL: f9:
 ;CHECK-VFP: vcvt.f32.u32
+;CHECK-VFP-SP-LABEL: f9:
+;CHECK-VFP-SP: vcvt.f32.u32
 ;CHECK-LABEL: f9:
 ;CHECK: floatunsisf
 entry:
   %tmp = uitofp i32 %a to float   ; <float> [#uses=1]
   ret float %tmp
 }
 
 define double @f10(i32 %a) {
 ;CHECK-VFP-LABEL: f10:
 ;CHECK-VFP: vcvt.f64.u32
+;CHECK-VFP-SP-LABEL: f10:
+;CHECK-VFP-SP: bl __aeabi_ui2d
 ;CHECK-LABEL: f10:
 ;CHECK: floatunsidf
 entry:
   %tmp = uitofp i32 %a to double    ; <double> [#uses=1]
   ret double %tmp
 }

llvm/trunk/test/CodeGen/ARM/half.ll

 ; RUN: llc < %s -mtriple=thumbv7-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-OLD
 ; RUN: llc < %s -mtriple=thumbv7s-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-F16
 ; RUN: llc < %s -mtriple=thumbv8-apple-ios7.0 | FileCheck %s --check-prefix=CHECK  --check-prefix=CHECK-V8
+; RUN: llc < %s -mtriple=armv8r-none-none-eabi | FileCheck %s --check-prefix=CHECK  --check-prefix=CHECK-V8
+; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=+fp-only-sp | FileCheck %s --check-prefix=CHECK  --check-prefix=CHECK-V8-SP
 
 define void @test_load_store(half* %in, half* %out) {
 ; CHECK-LABEL: test_load_store:
 ; CHECK: ldrh [[TMP:r[0-9]+]], [r0]
 ; CHECK: strh [[TMP]], [r1]
   %val = load half, half* %in
   store half %val, half* %out
   ret void

 }
 
 define float @test_extend32(half* %addr) {
 ; CHECK-LABEL: test_extend32:
 
 ; CHECK-OLD: b.w ___extendhfsf2
 ; CHECK-F16: vcvtb.f32.f16
 ; CHECK-V8: vcvtb.f32.f16
+; CHECK-V8-SP: vcvtb.f32.f16
   %val16 = load half, half* %addr
   %val32 = fpext half %val16 to float
   ret float %val32
 }
 
 define double @test_extend64(half* %addr) {
 ; CHECK-LABEL: test_extend64:
 
 ; CHECK-OLD: bl ___extendhfsf2
 ; CHECK-OLD: vcvt.f64.f32
 ; CHECK-F16: vcvtb.f32.f16
 ; CHECK-F16: vcvt.f64.f32
 ; CHECK-V8: vcvtb.f64.f16
+; CHECK-V8-SP: vcvtb.f32.f16
+; CHECK-V8-SP: bl __aeabi_f2d
   %val16 = load half, half* %addr
   %val32 = fpext half %val16 to double
   ret double %val32
 }
 
 define void @test_trunc32(float %in, half* %addr) {
 ; CHECK-LABEL: test_trunc32:
 
 ; CHECK-OLD: bl ___truncsfhf2
 ; CHECK-F16: vcvtb.f16.f32
 ; CHECK-V8: vcvtb.f16.f32
+; CHECK-V8-SP: vcvtb.f16.f32
   %val16 = fptrunc float %in to half
   store half %val16, half* %addr
   ret void
 }
 
 define void @test_trunc64(double %in, half* %addr) {
 ; CHECK-LABEL: test_trunc64:
 
 ; CHECK-OLD: bl ___truncdfhf2
 ; CHECK-F16: bl ___truncdfhf2
 ; CHECK-V8: vcvtb.f16.f64
+; CHECK-V8-SP: bl __aeabi_d2h
   %val16 = fptrunc double %in to half
   store half %val16, half* %addr
   ret void
 }