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author
Diogo N. Sampaio
committedSep 12, 2018
[ARM] Tighten f64<->f16 conversion requirements
Fix missing Requires fields. Patch by Bernard Ogden (bogden) Reviewers: SjoerdMeijer, javed.absar, t.p.northover Reviewed By: t.p.northover Differential Revision: https://reviews.llvm.org/D51631 llvm-svn: 342061
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3 files changed

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‎llvm/lib/Target/ARM/ARMInstrVFP.td

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -725,9 +725,11 @@ def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
725725
}
726726

727727
def : FullFP16Pat<(f64 (fpextend HPR:$Sm)),
728-
(VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))>;
728+
(VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))>,
729+
Requires<[HasFPARMv8, HasDPVFP]>;
729730
def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
730-
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
731+
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
732+
Requires<[HasFPARMv8, HasDPVFP]>;
731733

732734
def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
733735
(outs SPR:$Sd), (ins DPR:$Dm),
@@ -746,9 +748,11 @@ def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
746748
}
747749

748750
def : FullFP16Pat<(f16 (fpround DPR:$Dm)),
749-
(COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>;
751+
(COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>,
752+
Requires<[HasFPARMv8, HasDPVFP]>;
750753
def : FP16Pat<(fp_to_f16 (f64 DPR:$a)),
751-
(i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
754+
(i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>,
755+
Requires<[HasFPARMv8, HasDPVFP]>;
752756

753757
def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
754758
(outs DPR:$Dd), (ins SPR:$Sm),

‎llvm/test/CodeGen/ARM/fpconv.ll

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,13 @@
11
; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
22
; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s
3+
; RUN: llc -mtriple=armv8r-none-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-VFP
4+
; RUN: llc -mtriple=armv8r-none-none-eabi -mattr=+fp-only-sp %s -o - | FileCheck %s --check-prefix=CHECK-VFP-SP
35

46
define float @f1(double %x) {
57
;CHECK-VFP-LABEL: f1:
68
;CHECK-VFP: vcvt.f32.f64
9+
;CHECK-VFP-SP-LABEL: f1:
10+
;CHECK-VFP-SP: bl __aeabi_d2f
711
;CHECK-LABEL: f1:
812
;CHECK: truncdfsf2
913
entry:
@@ -14,6 +18,8 @@ entry:
1418
define double @f2(float %x) {
1519
;CHECK-VFP-LABEL: f2:
1620
;CHECK-VFP: vcvt.f64.f32
21+
;CHECK-VFP-SP-LABEL: f2:
22+
;CHECK-VFP-SP: bl __aeabi_f2d
1723
;CHECK-LABEL: f2:
1824
;CHECK: extendsfdf2
1925
entry:
@@ -24,6 +30,8 @@ entry:
2430
define i32 @f3(float %x) {
2531
;CHECK-VFP-LABEL: f3:
2632
;CHECK-VFP: vcvt.s32.f32
33+
;CHECK-VFP-SP-LABEL: f3:
34+
;CHECK-VFP-SP: vcvt.s32.f32
2735
;CHECK-LABEL: f3:
2836
;CHECK: fixsfsi
2937
entry:
@@ -34,6 +42,8 @@ entry:
3442
define i32 @f4(float %x) {
3543
;CHECK-VFP-LABEL: f4:
3644
;CHECK-VFP: vcvt.u32.f32
45+
;CHECK-VFP-SP-LABEL: f4:
46+
;CHECK-VFP-SP: vcvt.u32.f32
3747
;CHECK-LABEL: f4:
3848
;CHECK: fixunssfsi
3949
entry:
@@ -44,6 +54,8 @@ entry:
4454
define i32 @f5(double %x) {
4555
;CHECK-VFP-LABEL: f5:
4656
;CHECK-VFP: vcvt.s32.f64
57+
;CHECK-VFP-SP-LABEL: f5:
58+
;CHECK-VFP-SP: bl __aeabi_d2iz
4759
;CHECK-LABEL: f5:
4860
;CHECK: fixdfsi
4961
entry:
@@ -54,6 +66,8 @@ entry:
5466
define i32 @f6(double %x) {
5567
;CHECK-VFP-LABEL: f6:
5668
;CHECK-VFP: vcvt.u32.f64
69+
;CHECK-VFP-SP-LABEL: f6:
70+
;CHECK-VFP-SP: bl __aeabi_d2uiz
5771
;CHECK-LABEL: f6:
5872
;CHECK: fixunsdfsi
5973
entry:
@@ -64,6 +78,8 @@ entry:
6478
define float @f7(i32 %a) {
6579
;CHECK-VFP-LABEL: f7:
6680
;CHECK-VFP: vcvt.f32.s32
81+
;CHECK-VFP-SP-LABEL: f7:
82+
;CHECK-VFP-SP: vcvt.f32.s32
6783
;CHECK-LABEL: f7:
6884
;CHECK: floatsisf
6985
entry:
@@ -74,6 +90,8 @@ entry:
7490
define double @f8(i32 %a) {
7591
;CHECK-VFP-LABEL: f8:
7692
;CHECK-VFP: vcvt.f64.s32
93+
;CHECK-VFP-SP-LABEL: f8:
94+
;CHECK-VFP-SP: bl __aeabi_i2d
7795
;CHECK-LABEL: f8:
7896
;CHECK: floatsidf
7997
entry:
@@ -84,6 +102,8 @@ entry:
84102
define float @f9(i32 %a) {
85103
;CHECK-VFP-LABEL: f9:
86104
;CHECK-VFP: vcvt.f32.u32
105+
;CHECK-VFP-SP-LABEL: f9:
106+
;CHECK-VFP-SP: vcvt.f32.u32
87107
;CHECK-LABEL: f9:
88108
;CHECK: floatunsisf
89109
entry:
@@ -94,6 +114,8 @@ entry:
94114
define double @f10(i32 %a) {
95115
;CHECK-VFP-LABEL: f10:
96116
;CHECK-VFP: vcvt.f64.u32
117+
;CHECK-VFP-SP-LABEL: f10:
118+
;CHECK-VFP-SP: bl __aeabi_ui2d
97119
;CHECK-LABEL: f10:
98120
;CHECK: floatunsidf
99121
entry:

‎llvm/test/CodeGen/ARM/half.ll

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; RUN: llc < %s -mtriple=thumbv7-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-OLD
22
; RUN: llc < %s -mtriple=thumbv7s-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-F16
33
; RUN: llc < %s -mtriple=thumbv8-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
4+
; RUN: llc < %s -mtriple=armv8r-none-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
5+
; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=+fp-only-sp | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
46

57
define void @test_load_store(half* %in, half* %out) {
68
; CHECK-LABEL: test_load_store:
@@ -33,6 +35,7 @@ define float @test_extend32(half* %addr) {
3335
; CHECK-OLD: b.w ___extendhfsf2
3436
; CHECK-F16: vcvtb.f32.f16
3537
; CHECK-V8: vcvtb.f32.f16
38+
; CHECK-V8-SP: vcvtb.f32.f16
3639
%val16 = load half, half* %addr
3740
%val32 = fpext half %val16 to float
3841
ret float %val32
@@ -46,6 +49,8 @@ define double @test_extend64(half* %addr) {
4649
; CHECK-F16: vcvtb.f32.f16
4750
; CHECK-F16: vcvt.f64.f32
4851
; CHECK-V8: vcvtb.f64.f16
52+
; CHECK-V8-SP: vcvtb.f32.f16
53+
; CHECK-V8-SP: bl __aeabi_f2d
4954
%val16 = load half, half* %addr
5055
%val32 = fpext half %val16 to double
5156
ret double %val32
@@ -57,6 +62,7 @@ define void @test_trunc32(float %in, half* %addr) {
5762
; CHECK-OLD: bl ___truncsfhf2
5863
; CHECK-F16: vcvtb.f16.f32
5964
; CHECK-V8: vcvtb.f16.f32
65+
; CHECK-V8-SP: vcvtb.f16.f32
6066
%val16 = fptrunc float %in to half
6167
store half %val16, half* %addr
6268
ret void
@@ -68,6 +74,7 @@ define void @test_trunc64(double %in, half* %addr) {
6874
; CHECK-OLD: bl ___truncdfhf2
6975
; CHECK-F16: bl ___truncdfhf2
7076
; CHECK-V8: vcvtb.f16.f64
77+
; CHECK-V8-SP: bl __aeabi_d2h
7178
%val16 = fptrunc double %in to half
7279
store half %val16, half* %addr
7380
ret void

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