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Differential D51555

[AMDGPU] Split v32i32 loads
ClosedPublic

Authored by rampitec on Aug 31 2018, 1:07 PM.

Details

Reviewers
kzhuravl
msearles
arsenm
Commits
rG44451b3344bf: [AMDGPU] Split v32i32 loads
rL341266: [AMDGPU] Split v32i32 loads

Diff Detail

Event Timeline

rampitec created this revision.Aug 31 2018, 1:07 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptAug 31 2018, 1:07 PM
msearles accepted this revision.Aug 31 2018, 3:33 PM

LGTM

This revision is now accepted and ready to land.Aug 31 2018, 3:33 PM
Closed by commit rL341266: [AMDGPU] Split v32i32 loads (authored by rampitec). · Explain WhyAug 31 2018, 3:44 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
8 lines
test/
CodeGen/
AMDGPU/
146 lines
282 lines
10 lines

Diff 163581

lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 150 Lines • ▼ Show 20 LinesSITargetLowering::SITargetLowering(const TargetMachine &TM,
computeRegisterProperties(Subtarget->getRegisterInfo()); computeRegisterProperties(Subtarget->getRegisterInfo());
// We need to custom lower vector stores from local memory // We need to custom lower vector stores from local memory
setOperationAction(ISD::LOAD, MVT::v2i32, Custom); setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
setOperationAction(ISD::LOAD, MVT::v4i32, Custom); setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
setOperationAction(ISD::LOAD, MVT::v8i32, Custom); setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
setOperationAction(ISD::LOAD, MVT::v16i32, Custom); setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
setOperationAction(ISD::LOAD, MVT::i1, Custom); setOperationAction(ISD::LOAD, MVT::i1, Custom);
setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
setOperationAction(ISD::STORE, MVT::v2i32, Custom); setOperationAction(ISD::STORE, MVT::v2i32, Custom);
setOperationAction(ISD::STORE, MVT::v4i32, Custom); setOperationAction(ISD::STORE, MVT::v4i32, Custom);
setOperationAction(ISD::STORE, MVT::v8i32, Custom); setOperationAction(ISD::STORE, MVT::v8i32, Custom);
setOperationAction(ISD::STORE, MVT::v16i32, Custom); setOperationAction(ISD::STORE, MVT::v16i32, Custom);
setOperationAction(ISD::STORE, MVT::i1, Custom); setOperationAction(ISD::STORE, MVT::i1, Custom);
setOperationAction(ISD::STORE, MVT::v32i32, Custom);
setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand); setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand); setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand); setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand); setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand);
setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand); setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
#if 0 #if 0
setOperationAction(ISD::ADDCARRY, MVT::i64, Legal); setOperationAction(ISD::ADDCARRY, MVT::i64, Legal);
setOperationAction(ISD::SUBCARRY, MVT::i64, Legal); setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
#endif #endif
// We only support LOAD/STORE and vector manipulation ops for vectors // We only support LOAD/STORE and vector manipulation ops for vectors
// with > 4 elements. // with > 4 elements.
for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32,
MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16 }) { MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16, MVT::v32i32 }) {
for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
switch (Op) { switch (Op) {
case ISD::LOAD: case ISD::LOAD:
case ISD::STORE: case ISD::STORE:
case ISD::BUILD_VECTOR: case ISD::BUILD_VECTOR:
case ISD::BITCAST: case ISD::BITCAST:
case ISD::EXTRACT_VECTOR_ELT: case ISD::EXTRACT_VECTOR_ELT:
case ISD::INSERT_VECTOR_ELT: case ISD::INSERT_VECTOR_ELT:
▲ Show 20 Lines • Show All 5,933 Lines • ▼ Show 20 LinesSDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
if (AS == AMDGPUAS::FLAT_ADDRESS) if (AS == AMDGPUAS::FLAT_ADDRESS)
AS = MFI->hasFlatScratchInit() ? AS = MFI->hasFlatScratchInit() ?
AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS; AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
unsigned NumElements = MemVT.getVectorNumElements(); unsigned NumElements = MemVT.getVectorNumElements();
if (AS == AMDGPUAS::CONSTANT_ADDRESS || if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) { AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
if (!Op->isDivergent() && Alignment >= 4) if (!Op->isDivergent() && Alignment >= 4 && NumElements < 32)
return SDValue(); return SDValue();
// Non-uniform loads will be selected to MUBUF instructions, so they // Non-uniform loads will be selected to MUBUF instructions, so they
// have the same legalization requirements as global and private // have the same legalization requirements as global and private
// loads. // loads.
// //
} }
if (AS == AMDGPUAS::CONSTANT_ADDRESS || if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT || AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
AS == AMDGPUAS::GLOBAL_ADDRESS) { AS == AMDGPUAS::GLOBAL_ADDRESS) {
if (Subtarget->getScalarizeGlobalBehavior() && !Op->isDivergent() && if (Subtarget->getScalarizeGlobalBehavior() && !Op->isDivergent() &&
!Load->isVolatile() && isMemOpHasNoClobberedMemOperand(Load) && !Load->isVolatile() && isMemOpHasNoClobberedMemOperand(Load) &&
Alignment >= 4) Alignment >= 4 && NumElements < 32)
return SDValue(); return SDValue();
// Non-uniform loads will be selected to MUBUF instructions, so they // Non-uniform loads will be selected to MUBUF instructions, so they
// have the same legalization requirements as global and private // have the same legalization requirements as global and private
// loads. // loads.
// //
} }
if (AS == AMDGPUAS::CONSTANT_ADDRESS || if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT || AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
▲ Show 20 Lines • Show All 3,025 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/load-constant-i32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i32: ; FUNC-LABEL: {{^}}constant_load_i32:
; GCN: s_load_dword s{{[0-9]+}} ; GCN: s_load_dword s{{[0-9]+}}
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
define amdgpu_kernel void @constant_load_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) #0 { define amdgpu_kernel void @constant_load_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) #0 {
entry: entry:
%ld = load i32, i32 addrspace(4)* %in %ld = load i32, i32 addrspace(4)* %in
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
; FUNC-LABEL: {{^}}constant_zextload_v8i32_to_v8i64: ; FUNC-LABEL: {{^}}constant_zextload_v8i32_to_v8i64:
; GCN: s_load_dwordx8 ; GCN: s_load_dwordx8
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-SA-DAG: flat_store_dwordx4 ; GCN-SA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(4)* %in) #0 { define amdgpu_kernel void @constant_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(4)* %in) #0 {
%ld = load <8 x i32>, <8 x i32> addrspace(4)* %in %ld = load <8 x i32>, <8 x i32> addrspace(4)* %in
%ext = zext <8 x i32> %ld to <8 x i64> %ext = zext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v8i32_to_v8i64: ; FUNC-LABEL: {{^}}constant_sextload_v8i32_to_v8i64:
; GCN: s_load_dwordx8 ; GCN: s_load_dwordx8
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(4)* %in) #0 { define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(4)* %in) #0 {
%ld = load <8 x i32>, <8 x i32> addrspace(4)* %in %ld = load <8 x i32>, <8 x i32> addrspace(4)* %in
%ext = sext <8 x i32> %ld to <8 x i64> %ext = sext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v16i32_to_v16i64: ; FUNC-LABEL: {{^}}constant_sextload_v16i32_to_v16i64:
Show All 24 Lines
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(4)* %in) #0 { define amdgpu_kernel void @constant_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(4)* %in) #0 {
%ld = load <16 x i32>, <16 x i32> addrspace(4)* %in %ld = load <16 x i32>, <16 x i32> addrspace(4)* %in
%ext = zext <16 x i32> %ld to <16 x i64> %ext = zext <16 x i32> %ld to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v32i32_to_v32i64: ; FUNC-LABEL: {{^}}constant_sextload_v32i32_to_v32i64:
Show All 16 Lines
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(4)* %in) #0 { define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(4)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(4)* %in %ld = load <32 x i32>, <32 x i32> addrspace(4)* %in
%ext = sext <32 x i32> %ld to <32 x i64> %ext = sext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
Show All 17 Lines
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_zextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(4)* %in) #0 { define amdgpu_kernel void @constant_zextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(4)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(4)* %in %ld = load <32 x i32>, <32 x i32> addrspace(4)* %in
%ext = zext <32 x i32> %ld to <32 x i64> %ext = zext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v32i32:
; GCN: s_load_dwordx16
; GCN: s_load_dwordx16
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_load_v32i32(<32 x i32> addrspace(1)* %out, <32 x i32> addrspace(4)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(4)* %in
store <32 x i32> %ld, <32 x i32> addrspace(1)* %out
ret void
}
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/load-global-i32.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}global_load_i32: ; FUNC-LABEL: {{^}}global_load_i32:
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}} ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}
; GCN-HSA: flat_load_dword ; GCN-HSA: {{flat|global}}_load_dword
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
define amdgpu_kernel void @global_load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @global_load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
entry: entry:
%ld = load i32, i32 addrspace(1)* %in %ld = load i32, i32 addrspace(1)* %in
store i32 %ld, i32 addrspace(1)* %out store i32 %ld, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_load_v2i32: ; FUNC-LABEL: {{^}}global_load_v2i32:
; GCN-NOHSA: buffer_load_dwordx2 ; GCN-NOHSA: buffer_load_dwordx2
; GCN-HSA: flat_load_dwordx2 ; GCN-HSA: {{flat|global}}_load_dwordx2
; EG: VTX_READ_64 ; EG: VTX_READ_64
define amdgpu_kernel void @global_load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 {
entry: entry:
%ld = load <2 x i32>, <2 x i32> addrspace(1)* %in %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in
store <2 x i32> %ld, <2 x i32> addrspace(1)* %out store <2 x i32> %ld, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_load_v3i32: ; FUNC-LABEL: {{^}}global_load_v3i32:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @global_load_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_load_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %in) #0 {
entry: entry:
%ld = load <3 x i32>, <3 x i32> addrspace(1)* %in %ld = load <3 x i32>, <3 x i32> addrspace(1)* %in
store <3 x i32> %ld, <3 x i32> addrspace(1)* %out store <3 x i32> %ld, <3 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_load_v4i32: ; FUNC-LABEL: {{^}}global_load_v4i32:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @global_load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {
entry: entry:
%ld = load <4 x i32>, <4 x i32> addrspace(1)* %in %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in
store <4 x i32> %ld, <4 x i32> addrspace(1)* %out store <4 x i32> %ld, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_load_v8i32: ; FUNC-LABEL: {{^}}global_load_v8i32:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @global_load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 {
entry: entry:
%ld = load <8 x i32>, <8 x i32> addrspace(1)* %in %ld = load <8 x i32>, <8 x i32> addrspace(1)* %in
store <8 x i32> %ld, <8 x i32> addrspace(1)* %out store <8 x i32> %ld, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_load_v16i32: ; FUNC-LABEL: {{^}}global_load_v16i32:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @global_load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 {
entry: entry:
%ld = load <16 x i32>, <16 x i32> addrspace(1)* %in %ld = load <16 x i32>, <16 x i32> addrspace(1)* %in
store <16 x i32> %ld, <16 x i32> addrspace(1)* %out store <16 x i32> %ld, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_i32_to_i64: ; FUNC-LABEL: {{^}}global_zextload_i32_to_i64:
; GCN-NOHSA-DAG: buffer_load_dword v[[LO:[0-9]+]], ; GCN-NOHSA-DAG: buffer_load_dword v[[LO:[0-9]+]],
; GCN-HSA-DAG: flat_load_dword v[[LO:[0-9]+]], ; GCN-HSA-DAG: {{flat|global}}_load_dword v[[LO:[0-9]+]],
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] ; GCN-HSA: {{flat|global}}_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]]
; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
define amdgpu_kernel void @global_zextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @global_zextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%ld = load i32, i32 addrspace(1)* %in %ld = load i32, i32 addrspace(1)* %in
%ext = zext i32 %ld to i64 %ext = zext i32 %ld to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_i32_to_i64: ; FUNC-LABEL: {{^}}global_sextload_i32_to_i64:
; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] ; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]]
; GCN-HSA: flat_load_dword v[[LO:[0-9]+]] ; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]]
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-HSA: {{flat|global}}_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
; EG: MEM_RAT ; EG: MEM_RAT
; EG: VTX_READ_32 ; EG: VTX_READ_32
; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal. ; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.
; EG: 31 ; EG: 31
define amdgpu_kernel void @global_sextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
%ld = load i32, i32 addrspace(1)* %in %ld = load i32, i32 addrspace(1)* %in
%ext = sext i32 %ld to i64 %ext = sext i32 %ld to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_v1i32_to_v1i64: ; FUNC-LABEL: {{^}}global_zextload_v1i32_to_v1i64:
; GCN-NOHSA: buffer_load_dword ; GCN-NOHSA: buffer_load_dword
; GCN-NOHSA: buffer_store_dwordx2 ; GCN-NOHSA: buffer_store_dwordx2
; GCN-HSA: flat_load_dword ; GCN-HSA: {{flat|global}}_load_dword
; GCN-HSA: flat_store_dwordx2 ; GCN-HSA: {{flat|global}}_store_dwordx2
define amdgpu_kernel void @global_zextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_zextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 {
%ld = load <1 x i32>, <1 x i32> addrspace(1)* %in %ld = load <1 x i32>, <1 x i32> addrspace(1)* %in
%ext = zext <1 x i32> %ld to <1 x i64> %ext = zext <1 x i32> %ld to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_v1i32_to_v1i64: ; FUNC-LABEL: {{^}}global_sextload_v1i32_to_v1i64:
; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] ; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]]
; GCN-HSA: flat_load_dword v[[LO:[0-9]+]] ; GCN-HSA: {{flat|global}}_load_dword v[[LO:[0-9]+]]
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-HSA: {{flat|global}}_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
define amdgpu_kernel void @global_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 {
%ld = load <1 x i32>, <1 x i32> addrspace(1)* %in %ld = load <1 x i32>, <1 x i32> addrspace(1)* %in
%ext = sext <1 x i32> %ld to <1 x i64> %ext = sext <1 x i32> %ld to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_v2i32_to_v2i64: ; FUNC-LABEL: {{^}}global_zextload_v2i32_to_v2i64:
; GCN-NOHSA: buffer_load_dwordx2 ; GCN-NOHSA: buffer_load_dwordx2
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-HSA: flat_load_dwordx2 ; GCN-HSA: {{flat|global}}_load_dwordx2
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_zextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_zextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 {
%ld = load <2 x i32>, <2 x i32> addrspace(1)* %in %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in
%ext = zext <2 x i32> %ld to <2 x i64> %ext = zext <2 x i32> %ld to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_v2i32_to_v2i64: ; FUNC-LABEL: {{^}}global_sextload_v2i32_to_v2i64:
; GCN-NOHSA: buffer_load_dwordx2 ; GCN-NOHSA: buffer_load_dwordx2
; GCN-HSA: flat_load_dwordx2 ; GCN-HSA: {{flat|global}}_load_dwordx2
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_sextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 {
%ld = load <2 x i32>, <2 x i32> addrspace(1)* %in %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in
%ext = sext <2 x i32> %ld to <2 x i64> %ext = sext <2 x i32> %ld to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_v4i32_to_v4i64: ; FUNC-LABEL: {{^}}global_zextload_v4i32_to_v4i64:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_zextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_zextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {
%ld = load <4 x i32>, <4 x i32> addrspace(1)* %in %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in
%ext = zext <4 x i32> %ld to <4 x i64> %ext = zext <4 x i32> %ld to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_v4i32_to_v4i64: ; FUNC-LABEL: {{^}}global_sextload_v4i32_to_v4i64:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_sextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {
%ld = load <4 x i32>, <4 x i32> addrspace(1)* %in %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in
%ext = sext <4 x i32> %ld to <4 x i64> %ext = sext <4 x i32> %ld to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_v8i32_to_v8i64: ; FUNC-LABEL: {{^}}global_zextload_v8i32_to_v8i64:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-SA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 {
%ld = load <8 x i32>, <8 x i32> addrspace(1)* %in %ld = load <8 x i32>, <8 x i32> addrspace(1)* %in
%ext = zext <8 x i32> %ld to <8 x i64> %ext = zext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_v8i32_to_v8i64: ; FUNC-LABEL: {{^}}global_sextload_v8i32_to_v8i64:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 {
%ld = load <8 x i32>, <8 x i32> addrspace(1)* %in %ld = load <8 x i32>, <8 x i32> addrspace(1)* %in
%ext = sext <8 x i32> %ld to <8 x i64> %ext = sext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_v16i32_to_v16i64: ; FUNC-LABEL: {{^}}global_sextload_v16i32_to_v16i64:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 {
%ld = load <16 x i32>, <16 x i32> addrspace(1)* %in %ld = load <16 x i32>, <16 x i32> addrspace(1)* %in
%ext = sext <16 x i32> %ld to <16 x i64> %ext = sext <16 x i32> %ld to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_v16i32_to_v16i64 ; FUNC-LABEL: {{^}}global_zextload_v16i32_to_v16i64
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 {
%ld = load <16 x i32>, <16 x i32> addrspace(1)* %in %ld = load <16 x i32>, <16 x i32> addrspace(1)* %in
%ext = zext <16 x i32> %ld to <16 x i64> %ext = zext <16 x i32> %ld to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_sextload_v32i32_to_v32i64: ; FUNC-LABEL: {{^}}global_sextload_v32i32_to_v32i64:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA-DAG: buffer_load_dwordx4 ; GCN-NOHSA-DAG: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
; GCN-DAG: v_ashrrev_i32 ; GCN-DAG: v_ashrrev_i32
Show All 38 Lines
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(1)* %in %ld = load <32 x i32>, <32 x i32> addrspace(1)* %in
%ext = sext <32 x i32> %ld to <32 x i64> %ext = sext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_zextload_v32i32_to_v32i64: ; FUNC-LABEL: {{^}}global_zextload_v32i32_to_v32i64:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_zextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @global_zextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(1)* %in %ld = load <32 x i32>, <32 x i32> addrspace(1)* %in
%ext = zext <32 x i32> %ld to <32 x i64> %ext = zext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}global_load_v32i32:
; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-HSA: {{flat|global}}_load_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @global_load_v32i32(<32 x i32> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(1)* %in
store <32 x i32> %ld, <32 x i32> addrspace(1)* %out
ret void
}
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/load-local-i32.ll

Show First 20 Lines • Show All 259 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @local_zextload_v32i32_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i32> addrspace(3)* %in) #0 { define amdgpu_kernel void @local_zextload_v32i32_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i32> addrspace(3)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(3)* %in %ld = load <32 x i32>, <32 x i32> addrspace(3)* %in
%ext = zext <32 x i32> %ld to <32 x i64> %ext = zext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(3)* %out store <32 x i64> %ext, <32 x i64> addrspace(3)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}local_load_v32i32:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_load_v32i32(<32 x i32> addrspace(3)* %out, <32 x i32> addrspace(3)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(3)* %in
store <32 x i32> %ld, <32 x i32> addrspace(3)* %out
ret void
}
attributes #0 = { nounwind } attributes #0 = { nounwind }