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Differential D51506

[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8
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Authored by jsji on Aug 30 2018, 2:15 PM.

Details

Reviewers
hfinkel
nemanjai
stefanp
Commits
rGc2b6c547dc28: [PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some…
rL341293: [PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8
Summary

When doing some instruction scheduling work, we noticed some missing itineraries.

Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling,
because we can still get same latency due to default values.

With machine scheduler, however, itineraries will have impact to scheduling.
eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class.
And most of the instruction class with itineraries will have NumMicroOps default to 1.

This will has impact on the count of RetiredMOps, affects the Pending/Available Queue,
then causing different scheduling or suboptimal scheduling further.

This patch is for IIC_IntRotateDI first, as there are some existing testcases that can demonstrate the scheduling change.

Diff Detail

Event Timeline

jsji created this revision.Aug 30 2018, 2:15 PM
Herald added a subscriber: hiraditya. · View Herald TranscriptAug 30 2018, 2:15 PM
jsji updated this revision to Diff 163411.Aug 30 2018, 2:38 PM

Update diff to include more context.

nemanjai accepted this revision.Aug 31 2018, 4:43 AM

LGTM. Thanks on working on completing the set of itineraries.

This revision is now accepted and ready to land.Aug 31 2018, 4:43 AM
Closed by commit rL341293: [PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 (authored by • qshanz). · Explain WhySep 2 2018, 8:16 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
4 lines
4 lines
test/
CodeGen/
PowerPC/
16 lines
2 lines
58 lines
58 lines

Diff 163411

llvm/lib/Target/PowerPC/PPCScheduleP7.td

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Linesdef P7Itineraries : ProcessorItineraries<
InstrItinData<IIC_IntRotate , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_IntRotate , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>, P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>], InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<IIC_IntRotateD , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_IntRotateD , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>, P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>], InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntShift , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_IntShift , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>, P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>], InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<IIC_IntTrapW , [InstrStage<1, [P7_DU1, P7_DU2, InstrItinData<IIC_IntTrapW , [InstrStage<1, [P7_DU1, P7_DU2,
P7_DU3, P7_DU4], 0>, P7_DU3, P7_DU4], 0>,
InstrStage<1, [P7_FX1, P7_FX2]>], InstrStage<1, [P7_FX1, P7_FX2]>],
[1, 1]>, [1, 1]>,
▲ Show 20 Lines • Show All 261 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCScheduleP8.td

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Linesdef P8Itineraries : ProcessorItineraries<
InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>, P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>], InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<IIC_IntRotateD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, InstrItinData<IIC_IntRotateD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>, P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>], InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntShift , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, InstrItinData<IIC_IntShift , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>, P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>], InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<IIC_IntTrapW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, InstrItinData<IIC_IntTrapW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>, P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>], InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1]>, [1, 1]>,
▲ Show 20 Lines • Show All 294 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll

Show All 27 Lines
; CHECK: .LBB0_4: # %L.entry ; CHECK: .LBB0_4: # %L.entry
; CHECK: cmplwi 3, 33059 ; CHECK: cmplwi 3, 33059
; CHECK: lwsync ; CHECK: lwsync
; CHECK: lhz 3, 46(1) ; CHECK: lhz 3, 46(1)
; CHECK: cmplwi 3, 234 ; CHECK: cmplwi 3, 234
; ;
; CHECK-P7-LABEL: main: ; CHECK-P7-LABEL: main:
; CHECK-P7: li 3, -32477 ; CHECK-P7: li 3, -32477
; CHECK-P7: lis 4, 0 ; CHECK-P7: lis 5, 0
; CHECK-P7: li 7, 0 ; CHECK-P7: li 7, 0
; CHECK-P7: li 5, 234
; CHECK-P7: sth 3, 46(1) ; CHECK-P7: sth 3, 46(1)
; CHECK-P7: ori 4, 4, 33059 ; CHECK-P7: li 6, 234
; CHECK-P7: rlwinm 3, 6, 3, 27, 27 ; CHECK-P7: ori 5, 5, 33059
; CHECK-P7: rlwinm 3, 4, 3, 27, 27
; CHECK-P7: ori 7, 7, 65535 ; CHECK-P7: ori 7, 7, 65535
; CHECK-P7: sync ; CHECK-P7: sync
; CHECK-P7: slw 6, 6, 3
; CHECK-P7: slw 8, 5, 3 ; CHECK-P7: slw 8, 5, 3
; CHECK-P7: slw 9, 4, 3
; CHECK-P7: rldicr 4, 6, 0, 61
; CHECK-P7: slw 5, 7, 3 ; CHECK-P7: slw 5, 7, 3
; CHECK-P7: and 7, 8, 5 ; CHECK-P7: rldicr 4, 4, 0, 61
; CHECK-P7: and 8, 9, 5 ; CHECK-P7: and 7, 6, 5
; CHECK-P7: and 8, 8, 5
; CHECK-P7: .LBB0_1: # %L.entry ; CHECK-P7: .LBB0_1: # %L.entry
; CHECK-P7: lwarx 9, 0, 4 ; CHECK-P7: lwarx 9, 0, 4
; CHECK-P7: and 6, 9, 5 ; CHECK-P7: and 6, 9, 5
; CHECK-P7: cmpw 0, 6, 8 ; CHECK-P7: cmpw 0, 6, 8
; CHECK-P7: bne 0, .LBB0_3 ; CHECK-P7: bne 0, .LBB0_3
; CHECK-P7: andc 9, 9, 5 ; CHECK-P7: andc 9, 9, 5
; CHECK-P7: or 9, 9, 7 ; CHECK-P7: or 9, 9, 7
; CHECK-P7: stwcx. 9, 0, 4 ; CHECK-P7: stwcx. 9, 0, 4
Show All 37 Lines

llvm/test/CodeGen/PowerPC/funnel-shift.ll

Show All 30 Lines
; Verify that weird types are minimally supported. ; Verify that weird types are minimally supported.
declare i37 @llvm.fshl.i37(i37, i37, i37) declare i37 @llvm.fshl.i37(i37, i37, i37)
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) { define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-LABEL: fshl_i37: ; CHECK-LABEL: fshl_i37:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lis 6, -8857 ; CHECK-NEXT: lis 6, -8857
; CHECK-NEXT: clrldi 5, 5, 27 ; CHECK-NEXT: clrldi 5, 5, 27
; CHECK-NEXT: clrldi 4, 4, 27
; CHECK-NEXT: ori 6, 6, 51366 ; CHECK-NEXT: ori 6, 6, 51366
; CHECK-NEXT: clrldi 4, 4, 27
; CHECK-NEXT: sldi 6, 6, 32 ; CHECK-NEXT: sldi 6, 6, 32
; CHECK-NEXT: oris 6, 6, 3542 ; CHECK-NEXT: oris 6, 6, 3542
; CHECK-NEXT: ori 6, 6, 31883 ; CHECK-NEXT: ori 6, 6, 31883
; CHECK-NEXT: mulhdu 6, 5, 6 ; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5 ; CHECK-NEXT: rldicl 6, 6, 59, 5
; CHECK-NEXT: mulli 6, 6, 37 ; CHECK-NEXT: mulli 6, 6, 37
; CHECK-NEXT: subf. 5, 6, 5 ; CHECK-NEXT: subf. 5, 6, 5
; CHECK-NEXT: subfic 6, 5, 37 ; CHECK-NEXT: subfic 6, 5, 37
▲ Show 20 Lines • Show All 211 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pr33093.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Linesentry:
ret i32 %or22 ret i32 %or22
} }
define i64 @ReverseBits64(i64 %n) { define i64 @ReverseBits64(i64 %n) {
; CHECK-LABEL: ReverseBits64: ; CHECK-LABEL: ReverseBits64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 4, -21846
; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: lis 6, -13108 ; CHECK-NEXT: lis 7, -13108
; CHECK-NEXT: lis 7, 13107 ; CHECK-NEXT: lis 8, 13107
; CHECK-NEXT: sldi 8, 3, 1
; CHECK-NEXT: rldicl 3, 3, 63, 1
; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845 ; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: ori 6, 6, 52428 ; CHECK-NEXT: ori 7, 7, 52428
; CHECK-NEXT: ori 7, 7, 13107 ; CHECK-NEXT: ori 8, 8, 13107
; CHECK-NEXT: sldi 4, 4, 32 ; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: sldi 5, 5, 32 ; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: oris 4, 4, 43690 ; CHECK-NEXT: oris 4, 4, 43690
; CHECK-NEXT: oris 5, 5, 21845 ; CHECK-NEXT: oris 5, 5, 21845
; CHECK-NEXT: sldi 6, 3, 1
; CHECK-NEXT: rldicl 3, 3, 63, 1
; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845 ; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: and 4, 8, 4 ; CHECK-NEXT: sldi 7, 7, 32
; CHECK-NEXT: sldi 8, 8, 32
; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: sldi 5, 6, 32 ; CHECK-NEXT: lis 5, -3856
; CHECK-NEXT: sldi 6, 7, 32 ; CHECK-NEXT: oris 6, 7, 52428
; CHECK-NEXT: lis 7, 3855 ; CHECK-NEXT: oris 7, 8, 13107
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: oris 4, 5, 52428 ; CHECK-NEXT: lis 4, 3855
; CHECK-NEXT: oris 5, 6, 13107 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: lis 6, -3856 ; CHECK-NEXT: ori 6, 6, 52428
; CHECK-NEXT: ori 7, 7, 3855 ; CHECK-NEXT: ori 7, 7, 13107
; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: sldi 8, 3, 2 ; CHECK-NEXT: sldi 8, 3, 2
; CHECK-NEXT: ori 4, 4, 52428
; CHECK-NEXT: rldicl 3, 3, 62, 2 ; CHECK-NEXT: rldicl 3, 3, 62, 2
; CHECK-NEXT: ori 5, 5, 13107 ; CHECK-NEXT: and 6, 8, 6
; CHECK-NEXT: ori 6, 6, 61680 ; CHECK-NEXT: and 3, 3, 7
; CHECK-NEXT: and 4, 8, 4 ; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: sldi 5, 6, 32 ; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: sldi 6, 7, 32 ; CHECK-NEXT: oris 5, 5, 61680
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: oris 4, 4, 3855
; CHECK-NEXT: oris 4, 5, 61680
; CHECK-NEXT: oris 5, 6, 3855
; CHECK-NEXT: sldi 6, 3, 4 ; CHECK-NEXT: sldi 6, 3, 4
; CHECK-NEXT: ori 4, 4, 61680 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: rldicl 3, 3, 60, 4 ; CHECK-NEXT: rldicl 3, 3, 60, 4
; CHECK-NEXT: ori 5, 5, 3855 ; CHECK-NEXT: and 5, 6, 5
; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rldicl 4, 3, 32, 32 ; CHECK-NEXT: rldicl 4, 3, 32, 32
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 ; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 ; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 ; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 ; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 ; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 ; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
; CHECK-NEXT: sldi 3, 5, 32 ; CHECK-NEXT: sldi 3, 5, 32
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testBitReverse.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
} }
declare i64 @llvm.bitreverse.i64(i64) declare i64 @llvm.bitreverse.i64(i64)
define i64 @testBitReverseIntrinsicI64(i64 %arg) { define i64 @testBitReverseIntrinsicI64(i64 %arg) {
; CHECK-LABEL: testBitReverseIntrinsicI64: ; CHECK-LABEL: testBitReverseIntrinsicI64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 4, -21846
; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: lis 6, -13108 ; CHECK-NEXT: lis 7, -13108
; CHECK-NEXT: lis 7, 13107 ; CHECK-NEXT: lis 8, 13107
; CHECK-NEXT: sldi 8, 3, 1
; CHECK-NEXT: rldicl 3, 3, 63, 1
; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845 ; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: ori 6, 6, 52428 ; CHECK-NEXT: ori 7, 7, 52428
; CHECK-NEXT: ori 7, 7, 13107 ; CHECK-NEXT: ori 8, 8, 13107
; CHECK-NEXT: sldi 4, 4, 32 ; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: sldi 5, 5, 32 ; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: oris 4, 4, 43690 ; CHECK-NEXT: oris 4, 4, 43690
; CHECK-NEXT: oris 5, 5, 21845 ; CHECK-NEXT: oris 5, 5, 21845
; CHECK-NEXT: sldi 6, 3, 1
; CHECK-NEXT: rldicl 3, 3, 63, 1
; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845 ; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: and 4, 8, 4 ; CHECK-NEXT: sldi 7, 7, 32
; CHECK-NEXT: sldi 8, 8, 32
; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: sldi 5, 6, 32 ; CHECK-NEXT: lis 5, -3856
; CHECK-NEXT: sldi 6, 7, 32 ; CHECK-NEXT: oris 6, 7, 52428
; CHECK-NEXT: lis 7, 3855 ; CHECK-NEXT: oris 7, 8, 13107
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: oris 4, 5, 52428 ; CHECK-NEXT: lis 4, 3855
; CHECK-NEXT: oris 5, 6, 13107 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: lis 6, -3856 ; CHECK-NEXT: ori 6, 6, 52428
; CHECK-NEXT: ori 7, 7, 3855 ; CHECK-NEXT: ori 7, 7, 13107
; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: sldi 8, 3, 2 ; CHECK-NEXT: sldi 8, 3, 2
; CHECK-NEXT: ori 4, 4, 52428
; CHECK-NEXT: rldicl 3, 3, 62, 2 ; CHECK-NEXT: rldicl 3, 3, 62, 2
; CHECK-NEXT: ori 5, 5, 13107 ; CHECK-NEXT: and 6, 8, 6
; CHECK-NEXT: ori 6, 6, 61680 ; CHECK-NEXT: and 3, 3, 7
; CHECK-NEXT: and 4, 8, 4 ; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: sldi 5, 6, 32 ; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: sldi 6, 7, 32 ; CHECK-NEXT: oris 5, 5, 61680
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: oris 4, 4, 3855
; CHECK-NEXT: oris 4, 5, 61680
; CHECK-NEXT: oris 5, 6, 3855
; CHECK-NEXT: sldi 6, 3, 4 ; CHECK-NEXT: sldi 6, 3, 4
; CHECK-NEXT: ori 4, 4, 61680 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: rldicl 3, 3, 60, 4 ; CHECK-NEXT: rldicl 3, 3, 60, 4
; CHECK-NEXT: ori 5, 5, 3855 ; CHECK-NEXT: and 5, 6, 5
; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rldicl 4, 3, 32, 32 ; CHECK-NEXT: rldicl 4, 3, 32, 32
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 ; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 ; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 ; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 ; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 ; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 ; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
; CHECK-NEXT: sldi 3, 5, 32 ; CHECK-NEXT: sldi 3, 5, 32
; CHECK-NEXT: or 3, 3, 6 ; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%res = call i64 @llvm.bitreverse.i64(i64 %arg) %res = call i64 @llvm.bitreverse.i64(i64 %arg)
ret i64 %res ret i64 %res
} }