[mips][microMIPS] Implement LI16 instruction

[jkolek]

Summary

Implement 16-bit microMIPS load immediate instruction LI16.

[sstankovic]

LGTM

[sstankovic]

Just one more thing that I noticed, and it applies to the previous patches too. You check whether the immediate operand is correct in the method MipsAsmParser::processInstruction, which is called after the instruction has already been parsed. This makes the error message not quite correct because the marker in the message that marks the position where the error happened is positioned not on the operand but on the start of the instruction. I think the proper way to handle this is to create AsmOperandClass for the operand and define custom ParserMethod, which would issue the error when the operand is being parsed. Since I already gave LGTM for several patches where this happens, you should at least add a TODO comment for this.

[dsanders]

I think the proper way to handle this is to create AsmOperandClass for the operand and define custom ParserMethod, which would issue the error when the operand is being parsed.

You need a custom predicate (AsmOperandClass.PredicateMethod) rather than a custom parser. If you need to transform the number you can do this with AsmOperandClass.RenderMethod. Other targets also use the value of AsmOperandClass.DiagnosticType in the switch in MatchAndEmitInstruction to emit better diagnostics on a match failure but I haven't tried this yet.

Closed by commit rL220475 (authored by zjovanovic).

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

switch (Inst.getOpcode()) {
       case Mips::SW16_MM:
         Opnd = Inst.getOperand(2);
         if (!Opnd.isImm())
           return Error(IDLoc, "expected immediate operand kind");
         UImm = Opnd.getImm();
         if (UImm > 0x3c)
           return Error(IDLoc, "immediate operand value out of range");
         break;
+      case Mips::LI16_MM:
+        Opnd = Inst.getOperand(1);
+        if (!Opnd.isImm())
+          return Error(IDLoc, "expected immediate operand kind");
+        Imm = Opnd.getImm();
+        if (Imm < -1 || Imm > 126)
+          return Error(IDLoc, "immediate operand value out of range");
+        break;
     }
   }
 
   if (needsExpansion(Inst))
     return expandInstruction(Inst, IDLoc, Instructions);
   else
     Instructions.push_back(Inst);
 

lib/Target/Mips/MicroMipsInstrFormats.td

class MOVE_FM_MM16<bits<6> funct> {
 
   bits<16> Inst;
 
   let Inst{15-10} = funct;
   let Inst{9-5}   = rd;
   let Inst{4-0}   = rs;
 }
 
+class LI_FM_MM16 {
+  bits<3> rd;
+  bits<7> imm;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0x3b;
+  let Inst{9-7}   = rd;
+  let Inst{6-0}   = imm;
+}
+
 class JALR_FM_MM16<bits<5> op> {
   bits<5> rs;
 
   bits<16> Inst;
 
   let Inst{15-10} = 0x11;
   let Inst{9-5}   = op;
   let Inst{4-0}   = rs;

lib/Target/Mips/MicroMipsInstrInfo.td

 def addrimm4 : ComplexPattern<iPTR, 2, "selectAddrRegImm4", [frameindex]>;
 def addrimm5 : ComplexPattern<iPTR, 2, "selectAddrRegImm5", [frameindex]>;
 def addrimm6 : ComplexPattern<iPTR, 2, "selectAddrRegImm6", [frameindex]>;
 
 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
 
 def simm4 : Operand<i32>;
+def simm7 : Operand<i32>;
 
 def simm12 : Operand<i32> {
   let DecoderMethod = "DecodeSimm12";
 }
 
 def uimm5_lsl2 : Operand<OtherVT> {
   let EncoderMethod = "getUImm5Lsl2Encoding";
 }
 
 def simm9_addiusp : Operand<i32> {
   let EncoderMethod = "getSImm9AddiuspValue";
 }
 
 def uimm3_shift : Operand<i32> {
   let EncoderMethod = "getUImm3Mod8Encoding";
 }
 
 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 0 && Imm <= 8;}]>;
 
+def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
+
 class mem_mm_4_generic : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
 }
 
 def mem_mm_4 : mem_mm_4_generic {
   let EncoderMethod = "getMemEncodingMMImm4";

 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
                InstrItinClass Itin = NoItinerary> :
   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
                   !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
   let isCommutable = isComm;
   let isReMaterializable = 1;
 }
 
+class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO,
+                  SDPatternOperator imm_type = null_frag> :
+  MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
+                  !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
+  let isReMaterializable = 1;
+}
+
 // 16-bit Jump and Link (Call)
 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
            [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
   let isCall = 1;
   let hasDelaySlot = 1;
   let Defs = [RA];
 }
def SH16_MM  : StoreMM16<"sh16", GPRMM16Opnd, truncstorei16, II_SH,
                          mem_mm_4_lsl1, addrimm5>, LOAD_STORE_FM_MM16<0x2a>;
 def SW16_MM  : StoreMM16<"sw16", GPRMM16Opnd, store, II_SW, mem_mm_4_lsl2,
                          addrimm6>, LOAD_STORE_FM_MM16<0x3a>;
 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
+def LI16_MM : LoadImmMM16<"li16", simm7, GPRMM16Opnd, immLi16>,
+              LI_FM_MM16, IsAsCheapAsAMove;
 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
 
 class WaitMM<string opstr> :
   InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],

test/MC/Mips/micromips-16-bit-instructions.s

 # CHECK-EL: sll16   $3, $16, 5      # encoding: [0x8a,0x25]
 # CHECK-EL: srl16   $4, $17, 6      # encoding: [0x1d,0x26]
 # CHECK-EL: lbu16   $3, 4($17)      # encoding: [0x94,0x09]
 # CHECK-EL: lhu16   $3, 4($16)      # encoding: [0x82,0x29]
 # CHECK-EL: lw16    $4, 8($17)      # encoding: [0x12,0x6a]
 # CHECK-EL: sb16    $3, 4($16)      # encoding: [0x84,0x89]
 # CHECK-EL: sh16    $4, 8($17)      # encoding: [0x14,0xaa]
 # CHECK-EL: sw16    $4, 4($17)      # encoding: [0x11,0xea]
+# CHECK-EL: li16    $3, -1          # encoding: [0xff,0xed]
+# CHECK-EL: li16    $3, 126         # encoding: [0xfe,0xed]
 # CHECK-EL: addius5 $7, -2          # encoding: [0xfc,0x4c]
 # CHECK-EL: addiusp -16             # encoding: [0xf9,0x4f]
 # CHECK-EL: mfhi    $9              # encoding: [0x09,0x46]
 # CHECK-EL: mflo    $9              # encoding: [0x49,0x46]
 # CHECK-EL: move    $25, $1         # encoding: [0x21,0x0f]
 # CHECK-EL: jrc     $9              # encoding: [0xa9,0x45]
 # CHECK-EL: jr16    $9              # encoding: [0x89,0x45]
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]

 # CHECK-EB: sll16   $3, $16, 5      # encoding: [0x25,0x8a]
 # CHECK-EB: srl16   $4, $17, 6      # encoding: [0x26,0x1d]
 # CHECK-EB: lbu16   $3, 4($17)      # encoding: [0x09,0x94]
 # CHECK-EB: lhu16   $3, 4($16)      # encoding: [0x29,0x82]
 # CHECK-EB: lw16    $4, 8($17)      # encoding: [0x6a,0x12]
 # CHECK-EB: sb16    $3, 4($16)      # encoding: [0x89,0x84]
 # CHECK-EB: sh16    $4, 8($17)      # encoding: [0xaa,0x14]
 # CHECK-EB: sw16    $4, 4($17)      # encoding: [0xea,0x11]
+# CHECK-EB: li16    $3, -1          # encoding: [0xed,0xff]
+# CHECK-EB: li16    $3, 126         # encoding: [0xed,0xfe]
 # CHECK-EB: addius5 $7, -2          # encoding: [0x4c,0xfc]
 # CHECK-EB: addiusp -16             # encoding: [0x4f,0xf9]
 # CHECK-EB: mfhi    $9              # encoding: [0x46,0x09]
 # CHECK-EB: mflo    $9              # encoding: [0x46,0x49]
 # CHECK-EB: move    $25, $1         # encoding: [0x0f,0x21]
 # CHECK-EB: jrc     $9              # encoding: [0x45,0xa9]
 # CHECK-EB: jr16    $9              # encoding: [0x45,0x89]
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EB: move    $zero, $zero    # encoding: [0x0c,0x00]
     sll16   $3, $16, 5
     srl16   $4, $17, 6
     lbu16   $3, 4($17)
     lhu16   $3, 4($16)
     lw16    $4, 8($17)
     sb16    $3, 4($16)
     sh16    $4, 8($17)
     sw16    $4, 4($17)
+    li16    $3, -1
+    li16    $3, 126
     addius5 $7, -2
     addiusp -16
     mfhi    $9
     mflo    $9
     move    $25, $1
     jrc     $9
     jr16    $9
     jalr    $9
     jraddiusp 20
     jalrs16 $9

test/MC/Mips/micromips-invalid.s

# RUN: FileCheck %s < %t1
   sh16  $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sw16  $9, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   lw16  $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   sb16  $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   sh16  $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   sw16  $4, 64($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  li16  $8, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  li16  $4, -2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range