[WebAssembly][WIP] Vector conversions

[tlively]

Summary

This unfinished CL lowers away bitconverts between vector
types in the common case but exposes some hairy stackification issues
when v2i64 and v2f64 are not enabled.

[tlively]

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

569

@aardappel This solution for the problem described in the comment fixes my own test, but causes crashes in the stackification tests. I assume this function is doing other work besides creating a TEE that cannot be skipped. Could you suggest a more robust way to fix this problem?

[aheejin]

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

569

(We talked in person and I'm gonna summarize it here)
Giving those instructions fake opcodes (like 0) can be one solution too.

[aardappel]

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

569

Yes, we'd really want to avoid checks like this, as disabling the explicit locals is something pretty hacky we only do to keep current tests happy.

I think the easiest solution is to convert the affected test to work with explicit locals?

[tlively]

Superseded by D51498

[tlively]

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

569

Would it be useful to convert the tests to work with explicit locals or is there some other benefit to disabling them?

[aardappel]

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

569

Yes, that is generally useful, we'd like to move to a world where there is as little use of this flag (and --wasm-keep-registers) as possible, with the exception maybe of test that specifically are about the handling of locals and registers in IR.
The presence of these flags complicates matters, e.g. we are still not able to assume in MC that all instructions are the stack versions.

lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-explicit-locals"
 
 // A command-line option to disable this pass, and keep implicit locals
 // for the purpose of testing with lit/llc ONLY.
 // This produces output which is not valid WebAssembly, and is not supported
 // by assemblers/disassemblers and other MC based tools.
-static cl::opt<bool> WasmDisableExplicitLocals(
+cl::opt<bool> WasmDisableExplicitLocals(
     "wasm-disable-explicit-locals", cl::Hidden,
     cl::desc("WebAssembly: output implicit locals in"
              " instruction output for test purposes only."),
     cl::init(false));
 
 namespace {
 class WebAssemblyExplicitLocals final : public MachineFunctionPass {
   StringRef getPassName() const override {

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 }
 
 // follow convention of making implicit expansions unsigned
 def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
           (EXTRACT_LANE_v16i8_u V128:$vec, (i32 LaneIdx16:$idx))>;
 def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
           (EXTRACT_LANE_v8i16_u V128:$vec, (i32 LaneIdx8:$idx))>;
 
+// Bitcasts are nops
+// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
+foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
+foreach t2 = !foldl(
+  []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+  acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
+    acc, !listconcat(acc, [cur])
+  )
+) in
+def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
+
 // arbitrary other BUILD_VECTOR patterns
 def : Pat<(v16i8 (build_vector
             (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3),
             (i32 I32:$x4), (i32 I32:$x5), (i32 I32:$x6), (i32 I32:$x7),
             (i32 I32:$x8), (i32 I32:$x9), (i32 I32:$x10), (i32 I32:$x11),
             (i32 I32:$x12), (i32 I32:$x13), (i32 I32:$x14), (i32 I32:$x15)
           )),
           (v16i8 (REPLACE_LANE_v16i8

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

 /// with DefReg and TeeReg stackified. This eliminates a get_local from the
 /// resulting code.
 static MachineInstr *MoveAndTeeForMultiUse(
     unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB,
     MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI,
     MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) {
   LLVM_DEBUG(dbgs() << "Move and tee for multi-use:"; Def->dump());
 
+  // If explicit locals are disabled, the tee this function would produce will
+  // never be lowered to tee_local, so do not produce a tee.
+  extern cl::opt<bool> WasmDisableExplicitLocals;
+  if (WasmDisableExplicitLocals)
+    return Def;
+
   // Move Def into place.
   MBB.splice(Insert, &MBB, Def);
   LIS.handleMove(*Def);
 
   // Create the Tee and attach the registers.
   const auto *RegClass = MRI.getRegClass(Reg);
   unsigned TeeReg = MRI.createVirtualRegister(RegClass);
   unsigned DefReg = MRI.createVirtualRegister(RegClass);

lib/Target/WebAssembly/WebAssemblyUtilities.cpp

bool WebAssembly::isTee(const MachineInstr &MI) {
   case WebAssembly::TEE_I32:
   case WebAssembly::TEE_I32_S:
   case WebAssembly::TEE_I64:
   case WebAssembly::TEE_I64_S:
   case WebAssembly::TEE_F32:
   case WebAssembly::TEE_F32_S:
   case WebAssembly::TEE_F64:
   case WebAssembly::TEE_F64_S:
+  case WebAssembly::TEE_V128:
+  case WebAssembly::TEE_V128_S:
     return true;
   default:
     return false;
   }
 }
 
 /// Test whether MI is a child of some other node in an expression tree.
 bool WebAssembly::isChild(const MachineInstr &MI,

test/CodeGen/WebAssembly/simd-conversions.ll

+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+
+; Test that bitcasts between vector types are lowered to zero instructions
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: v16i8_to_v16i8:
+define <16 x i8> @v16i8_to_v16i8(<16 x i8> %v) {
+  %res = bitcast <16 x i8> %v to <16 x i8>
+  ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v16i8_to_v8i16:
+define <8 x i16> @v16i8_to_v8i16(<16 x i8> %v) {
+  %res = bitcast <16 x i8> %v to <8 x i16>
+  ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v16i8_to_v4i32:
+define <4 x i32> @v16i8_to_v4i32(<16 x i8> %v) {
+  %res = bitcast <16 x i8> %v to <4 x i32>
+  ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v16i8_to_v2i64:
+define <2 x i64> @v16i8_to_v2i64(<16 x i8> %v) {
+  %res = bitcast <16 x i8> %v to <2 x i64>
+  ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v16i8_to_v4f32:
+define <4 x float> @v16i8_to_v4f32(<16 x i8> %v) {
+  %res = bitcast <16 x i8> %v to <4 x float>
+  ret <4 x float> %res
+}
+
+; CHECK-LABEL: v16i8_to_v2f64:
+define <2 x double> @v16i8_to_v2f64(<16 x i8> %v) {
+  %res = bitcast <16 x i8> %v to <2 x double>
+  ret <2 x double> %res
+}
+
+; CHECK-LABEL: v8i16_to_v16i8:
+define <16 x i8> @v8i16_to_v16i8(<8 x i16> %v) {
+  %res = bitcast <8 x i16> %v to <16 x i8>
+  ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v8i16_to_v8i16:
+define <8 x i16> @v8i16_to_v8i16(<8 x i16> %v) {
+  %res = bitcast <8 x i16> %v to <8 x i16>
+  ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v8i16_to_v4i32:
+define <4 x i32> @v8i16_to_v4i32(<8 x i16> %v) {
+  %res = bitcast <8 x i16> %v to <4 x i32>
+  ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v8i16_to_v2i64:
+define <2 x i64> @v8i16_to_v2i64(<8 x i16> %v) {
+  %res = bitcast <8 x i16> %v to <2 x i64>
+  ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v8i16_to_v4f32:
+define <4 x float> @v8i16_to_v4f32(<8 x i16> %v) {
+  %res = bitcast <8 x i16> %v to <4 x float>
+  ret <4 x float> %res
+}
+
+; CHECK-LABEL: v8i16_to_v2f64:
+define <2 x double> @v8i16_to_v2f64(<8 x i16> %v) {
+  %res = bitcast <8 x i16> %v to <2 x double>
+  ret <2 x double> %res
+}
+
+; CHECK-LABEL: v4i32_to_v16i8:
+define <16 x i8> @v4i32_to_v16i8(<4 x i32> %v) {
+  %res = bitcast <4 x i32> %v to <16 x i8>
+  ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v4i32_to_v8i16:
+define <8 x i16> @v4i32_to_v8i16(<4 x i32> %v) {
+  %res = bitcast <4 x i32> %v to <8 x i16>
+  ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v4i32_to_v4i32:
+define <4 x i32> @v4i32_to_v4i32(<4 x i32> %v) {
+  %res = bitcast <4 x i32> %v to <4 x i32>
+  ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v4i32_to_v2i64:
+define <2 x i64> @v4i32_to_v2i64(<4 x i32> %v) {
+  %res = bitcast <4 x i32> %v to <2 x i64>
+  ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v4i32_to_v4f32:
+define <4 x float> @v4i32_to_v4f32(<4 x i32> %v) {
+  %res = bitcast <4 x i32> %v to <4 x float>
+  ret <4 x float> %res
+}
+
+; CHECK-LABEL: v4i32_to_v2f64:
+define <2 x double> @v4i32_to_v2f64(<4 x i32> %v) {
+  %res = bitcast <4 x i32> %v to <2 x double>
+  ret <2 x double> %res
+}
+
+; CHECK-LABEL: v2i64_to_v16i8:
+define <16 x i8> @v2i64_to_v16i8(<2 x i64> %v) {
+  %res = bitcast <2 x i64> %v to <16 x i8>
+  ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v2i64_to_v8i16:
+define <8 x i16> @v2i64_to_v8i16(<2 x i64> %v) {
+  %res = bitcast <2 x i64> %v to <8 x i16>
+  ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v2i64_to_v4i32:
+define <4 x i32> @v2i64_to_v4i32(<2 x i64> %v) {
+  %res = bitcast <2 x i64> %v to <4 x i32>
+  ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v2i64_to_v2i64:
+define <2 x i64> @v2i64_to_v2i64(<2 x i64> %v) {
+  %res = bitcast <2 x i64> %v to <2 x i64>
+  ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v2i64_to_v4f32:
+define <4 x float> @v2i64_to_v4f32(<2 x i64> %v) {
+  %res = bitcast <2 x i64> %v to <4 x float>
+  ret <4 x float> %res
+}
+
+; CHECK-LABEL: v2i64_to_v2f64:
+define <2 x double> @v2i64_to_v2f64(<2 x i64> %v) {
+  %res = bitcast <2 x i64> %v to <2 x double>
+  ret <2 x double> %res
+}
+
+; CHECK-LABEL: v4f32_to_v16i8:
+define <16 x i8> @v4f32_to_v16i8(<4 x float> %v) {
+  %res = bitcast <4 x float> %v to <16 x i8>
+  ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v4f32_to_v8i16:
+define <8 x i16> @v4f32_to_v8i16(<4 x float> %v) {
+  %res = bitcast <4 x float> %v to <8 x i16>
+  ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v4f32_to_v4i32:
+define <4 x i32> @v4f32_to_v4i32(<4 x float> %v) {
+  %res = bitcast <4 x float> %v to <4 x i32>
+  ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v4f32_to_v2i64:
+define <2 x i64> @v4f32_to_v2i64(<4 x float> %v) {
+  %res = bitcast <4 x float> %v to <2 x i64>
+  ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v4f32_to_v4f32:
+define <4 x float> @v4f32_to_v4f32(<4 x float> %v) {
+  %res = bitcast <4 x float> %v to <4 x float>
+  ret <4 x float> %res
+}
+
+; CHECK-LABEL: v4f32_to_v2f64:
+define <2 x double> @v4f32_to_v2f64(<4 x float> %v) {
+  %res = bitcast <4 x float> %v to <2 x double>
+  ret <2 x double> %res
+}
+
+; CHECK-LABEL: v2f64_to_v16i8:
+define <16 x i8> @v2f64_to_v16i8(<2 x double> %v) {
+  %res = bitcast <2 x double> %v to <16 x i8>
+  ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v2f64_to_v8i16:
+define <8 x i16> @v2f64_to_v8i16(<2 x double> %v) {
+  %res = bitcast <2 x double> %v to <8 x i16>
+  ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v2f64_to_v4i32:
+define <4 x i32> @v2f64_to_v4i32(<2 x double> %v) {
+  %res = bitcast <2 x double> %v to <4 x i32>
+  ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v2f64_to_v2i64:
+define <2 x i64> @v2f64_to_v2i64(<2 x double> %v) {
+  %res = bitcast <2 x double> %v to <2 x i64>
+  ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v2f64_to_v4f32:
+define <4 x float> @v2f64_to_v4f32(<2 x double> %v) {
+  %res = bitcast <2 x double> %v to <4 x float>
+  ret <4 x float> %res
+}
+
+; CHECK-LABEL: v2f64_to_v2f64:
+define <2 x double> @v2f64_to_v2f64(<2 x double> %v) {
+  %res = bitcast <2 x double> %v to <2 x double>
+  ret <2 x double> %res
+}