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Differential D51143

[WebAssembly][NFC] Move specific instruction formats to specific files
ClosedPublic

Authored by tlively on Aug 22 2018, 5:02 PM.

Details

Reviewers
aheejin
dschuff
Commits
rG914f0f20a420: [WebAssembly][NFC] Move specific instruction formats to specific files
rL340503: [WebAssembly][NFC] Move specific instruction formats to specific files
Summary

WebAssemblyInstrFormats.td retains only multiclasses that are used in
multiple other tablegen files.

Diff Detail

Event Timeline

tlively created this revision.Aug 22 2018, 5:02 PM
Herald added subscribers: llvm-commits, jfb, sunfish and 2 others. · View Herald TranscriptAug 22 2018, 5:02 PM
Harbormaster completed remote builds in B21816: Diff 162108.Aug 22 2018, 5:02 PM
tlively updated this revision to Diff 162109.Aug 22 2018, 5:04 PM
  • Add comment
Harbormaster completed remote builds in B21817: Diff 162109.Aug 22 2018, 5:05 PM
aheejin accepted this revision.Aug 22 2018, 5:08 PM
This revision is now accepted and ready to land.Aug 22 2018, 5:08 PM
tlively mentioned this in D51113: [WebAssembly][NFC] Reorganize SIMD instructions.Aug 22 2018, 5:21 PM
Closed by commit rL340503: [WebAssembly][NFC] Move specific instruction formats to specific files (authored by tlively). · Explain WhyAug 22 2018, 5:37 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 162108

lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

Show All 10 Lines
/// WebAssembly Atomic operand code-gen constructs. /// WebAssembly Atomic operand code-gen constructs.
/// ///
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Atomic loads // Atomic loads
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
list<dag> pattern_r, string asmstr_r = "",
string asmstr_s = "", bits<32> inst = -1> {
defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
inst>,
Requires<[HasAtomics]>;
}
let Defs = [ARGUMENTS] in { let Defs = [ARGUMENTS] in {
defm ATOMIC_LOAD_I32 : WebAssemblyLoad<I32, "i32.atomic.load", 0xfe10>; defm ATOMIC_LOAD_I32 : WebAssemblyLoad<I32, "i32.atomic.load", 0xfe10>;
defm ATOMIC_LOAD_I64 : WebAssemblyLoad<I64, "i64.atomic.load", 0xfe11>; defm ATOMIC_LOAD_I64 : WebAssemblyLoad<I64, "i64.atomic.load", 0xfe11>;
} // Defs = [ARGUMENTS] } // Defs = [ARGUMENTS]
// Select loads with no constant offset. // Select loads with no constant offset.
let Predicates = [HasAtomics] in { let Predicates = [HasAtomics] in {
def : LoadPatNoOffset<i32, atomic_load_32, ATOMIC_LOAD_I32>; def : LoadPatNoOffset<i32, atomic_load_32, ATOMIC_LOAD_I32>;
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lib/Target/WebAssembly/WebAssemblyInstrFloat.td

// WebAssemblyInstrFloat.td-WebAssembly Float codegen support ---*- tablegen -*- // WebAssemblyInstrFloat.td-WebAssembly Float codegen support ---*- tablegen -*-
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// ///
/// \file /// \file
/// WebAssembly Floating-point operand code-gen constructs. /// WebAssembly Floating-point operand code-gen constructs.
/// ///
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass UnaryFP<SDNode node, string name, bits<32> f32Inst,
bits<32> f64Inst> {
defm _F32 : I<(outs F32:$dst), (ins F32:$src), (outs), (ins),
[(set F32:$dst, (node F32:$src))],
!strconcat("f32.", !strconcat(name, "\t$dst, $src")),
!strconcat("f32.", name), f32Inst>;
defm _F64 : I<(outs F64:$dst), (ins F64:$src), (outs), (ins),
[(set F64:$dst, (node F64:$src))],
!strconcat("f64.", !strconcat(name, "\t$dst, $src")),
!strconcat("f64.", name), f64Inst>;
}
multiclass BinaryFP<SDNode node, string name, bits<32> f32Inst,
bits<32> f64Inst> {
defm _F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
[(set F32:$dst, (node F32:$lhs, F32:$rhs))],
!strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f32.", name), f32Inst>;
defm _F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs), (outs), (ins),
[(set F64:$dst, (node F64:$lhs, F64:$rhs))],
!strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f64.", name), f64Inst>;
}
multiclass ComparisonFP<CondCode cond, string name, bits<32> f32Inst, bits<32> f64Inst> {
defm _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
[(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
!strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f32.", name), f32Inst>;
defm _F64 : I<(outs I32:$dst), (ins F64:$lhs, F64:$rhs), (outs), (ins),
[(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))],
!strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f64.", name), f64Inst>;
}
let Defs = [ARGUMENTS] in { let Defs = [ARGUMENTS] in {
let isCommutable = 1 in let isCommutable = 1 in
defm ADD : BinaryFP<fadd, "add ", 0x92, 0xa0>; defm ADD : BinaryFP<fadd, "add ", 0x92, 0xa0>;
defm SUB : BinaryFP<fsub, "sub ", 0x93, 0xa1>; defm SUB : BinaryFP<fsub, "sub ", 0x93, 0xa1>;
let isCommutable = 1 in let isCommutable = 1 in
defm MUL : BinaryFP<fmul, "mul ", 0x94, 0xa2>; defm MUL : BinaryFP<fmul, "mul ", 0x94, 0xa2>;
defm DIV : BinaryFP<fdiv, "div ", 0x95, 0xa3>; defm DIV : BinaryFP<fdiv, "div ", 0x95, 0xa3>;
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lib/Target/WebAssembly/WebAssemblyInstrFormats.td

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Linesmulticlass I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
def _S : NI<oops_s, iops_s, [], 1, asmstr_s, inst>; def _S : NI<oops_s, iops_s, [], 1, asmstr_s, inst>;
} }
// For instructions that have no register ops, so both sets are the same. // For instructions that have no register ops, so both sets are the same.
multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "", multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
bits<32> inst = -1> { bits<32> inst = -1> {
defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>; defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
} }
multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
list<dag> pattern_r, string asmstr_r = "", list<dag> pattern_r, string asmstr_r = "",
string asmstr_s = "", bits<32> simdop = -1> { string asmstr_s = "", bits<32> simdop = -1> {
defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
!or(0xfd00, !and(0xff, simdop))>, !or(0xfd00, !and(0xff, simdop))>,
Requires<[HasSIMD128]>; Requires<[HasSIMD128]>;
} }
multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
list<dag> pattern_r, string asmstr_r = "",
string asmstr_s = "", bits<32> inst = -1> {
defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
inst>,
Requires<[HasAtomics]>;
}
// Unary and binary instructions, for the local types that WebAssembly supports.
multiclass UnaryInt<SDNode node, string name, bits<32> i32Inst,
bits<32> i64Inst> {
defm _I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
[(set I32:$dst, (node I32:$src))],
!strconcat("i32.", !strconcat(name, "\t$dst, $src")),
!strconcat("i32.", name), i32Inst>;
defm _I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
[(set I64:$dst, (node I64:$src))],
!strconcat("i64.", !strconcat(name, "\t$dst, $src")),
!strconcat("i64.", name), i64Inst>;
}
multiclass BinaryInt<SDNode node, string name, bits<32> i32Inst,
bits<32> i64Inst> {
defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
[(set I32:$dst, (node I32:$lhs, I32:$rhs))],
!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i32.", name), i32Inst>;
defm _I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins),
[(set I64:$dst, (node I64:$lhs, I64:$rhs))],
!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i64.", name), i64Inst>;
}
multiclass UnaryFP<SDNode node, string name, bits<32> f32Inst,
bits<32> f64Inst> {
defm _F32 : I<(outs F32:$dst), (ins F32:$src), (outs), (ins),
[(set F32:$dst, (node F32:$src))],
!strconcat("f32.", !strconcat(name, "\t$dst, $src")),
!strconcat("f32.", name), f32Inst>;
defm _F64 : I<(outs F64:$dst), (ins F64:$src), (outs), (ins),
[(set F64:$dst, (node F64:$src))],
!strconcat("f64.", !strconcat(name, "\t$dst, $src")),
!strconcat("f64.", name), f64Inst>;
}
multiclass BinaryFP<SDNode node, string name, bits<32> f32Inst,
bits<32> f64Inst> {
defm _F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
[(set F32:$dst, (node F32:$lhs, F32:$rhs))],
!strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f32.", name), f32Inst>;
defm _F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs), (outs), (ins),
[(set F64:$dst, (node F64:$lhs, F64:$rhs))],
!strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f64.", name), f64Inst>;
}
multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
defm _I8x16 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v16i8 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("i8x16.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i8x16.", name), baseInst>;
defm _I16x8 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v8i16 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("i16x8.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i16x8.", name), !add(baseInst, 1)>;
defm _I32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v4i32 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("i32x4.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i32x4.", name), !add(baseInst, 2)>;
}
multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
defm _I64x2 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v2i64 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("i64x2.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i64x2.", name), !add(baseInst, 3)>;
}
multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
defm _F32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v4f32 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("f32x4.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f32x4.", name), baseInst>;
defm _F64x2 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v2f64 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("f64x2.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f64x2.", name), !add(baseInst, 1)>;
}
multiclass ComparisonInt<CondCode cond, string name, bits<32> i32Inst, bits<32> i64Inst> {
defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
[(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i32.", name), i32Inst>;
defm _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins),
[(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i64.", name), i64Inst>;
}
multiclass ComparisonFP<CondCode cond, string name, bits<32> f32Inst, bits<32> f64Inst> {
defm _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
[(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
!strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f32.", name), f32Inst>;
defm _F64 : I<(outs I32:$dst), (ins F64:$lhs, F64:$rhs), (outs), (ins),
[(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))],
!strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f64.", name), f64Inst>;
}

lib/Target/WebAssembly/WebAssemblyInstrInteger.td

// WebAssemblyInstrInteger.td-WebAssembly Integer codegen -------*- tablegen -*- // WebAssemblyInstrInteger.td-WebAssembly Integer codegen -------*- tablegen -*-
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// ///
/// \file /// \file
/// WebAssembly Integer operand code-gen constructs. /// WebAssembly Integer operand code-gen constructs.
/// ///
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass UnaryInt<SDNode node, string name, bits<32> i32Inst,
bits<32> i64Inst> {
defm _I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
[(set I32:$dst, (node I32:$src))],
!strconcat("i32.", !strconcat(name, "\t$dst, $src")),
!strconcat("i32.", name), i32Inst>;
defm _I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
[(set I64:$dst, (node I64:$src))],
!strconcat("i64.", !strconcat(name, "\t$dst, $src")),
!strconcat("i64.", name), i64Inst>;
}
multiclass BinaryInt<SDNode node, string name, bits<32> i32Inst,
bits<32> i64Inst> {
defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
[(set I32:$dst, (node I32:$lhs, I32:$rhs))],
!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i32.", name), i32Inst>;
defm _I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins),
[(set I64:$dst, (node I64:$lhs, I64:$rhs))],
!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i64.", name), i64Inst>;
}
multiclass ComparisonInt<CondCode cond, string name, bits<32> i32Inst, bits<32> i64Inst> {
defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
[(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i32.", name), i32Inst>;
defm _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins),
[(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i64.", name), i64Inst>;
}
let Defs = [ARGUMENTS] in { let Defs = [ARGUMENTS] in {
// The spaces after the names are for aesthetic purposes only, to make // The spaces after the names are for aesthetic purposes only, to make
// operands line up vertically after tab expansion. // operands line up vertically after tab expansion.
let isCommutable = 1 in let isCommutable = 1 in
defm ADD : BinaryInt<add, "add ", 0x6a, 0x7c>; defm ADD : BinaryInt<add, "add ", 0x6a, 0x7c>;
defm SUB : BinaryInt<sub, "sub ", 0x6b, 0x7d>; defm SUB : BinaryInt<sub, "sub ", 0x6b, 0x7d>;
let isCommutable = 1 in let isCommutable = 1 in
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lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Show All 12 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// constrained immediate argument types // constrained immediate argument types
foreach SIZE = [8, 16] in foreach SIZE = [8, 16] in
def ImmI#SIZE : ImmLeaf<i32, "return (Imm & ((1UL << "#SIZE#") - 1)) == Imm;">; def ImmI#SIZE : ImmLeaf<i32, "return (Imm & ((1UL << "#SIZE#") - 1)) == Imm;">;
foreach SIZE = [2, 4, 8, 16, 32] in foreach SIZE = [2, 4, 8, 16, 32] in
def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
defm _F32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v4f32 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("f32x4.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f32x4.", name), baseInst>;
defm _F64x2 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v2f64 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("f64x2.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("f64x2.", name), !add(baseInst, 1)>;
}
multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
defm _I8x16 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v16i8 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("i8x16.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i8x16.", name), baseInst>;
defm _I16x8 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v8i16 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("i16x8.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i16x8.", name), !add(baseInst, 1)>;
defm _I32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v4i32 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("i32x4.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i32x4.", name), !add(baseInst, 2)>;
}
multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
defm _I64x2 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
(outs), (ins),
[(set (v2i64 V128:$dst), (node V128:$lhs, V128:$rhs))],
!strconcat("i64x2.",
!strconcat(name, "\t$dst, $lhs, $rhs")),
!strconcat("i64x2.", name), !add(baseInst, 3)>;
}
// const vectors // const vectors
multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> { multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops, defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
[(set V128:$dst, (vec_t pat))], [(set V128:$dst, (vec_t pat))],
"v128.const\t$dst, "#args, "v128.const\t$dst, "#args,
"v128.const\t"#args, 0>; "v128.const\t"#args, 0>;
} }
defm "" : ConstVec<v16i8, defm "" : ConstVec<v16i8,
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