[WebAssembly] SIMD replace_lane

[tlively]

Summary

Implement and test replace_lane instructions.

Patch by Thomas Lively

[dschuff]

also please rebase against master.

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

88 ↗

(On Diff #160728)

should this be name#?

[tlively]

• Fix instruction naming

[tlively]

In D50750#1200113, @dschuff wrote:

also please rebase against master.

Done

[dschuff]

Oops, retroactive LGTM

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 } // Defs = [ARGUMENTS]
 
 // follow convention of making implicit expansions unsigned
 def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
           (EXTRACT_LANE_U_I8x16 V128:$vec, (i32 LaneIdx16:$idx))>;
 def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
           (EXTRACT_LANE_U_I16x8 V128:$vec, (i32 LaneIdx8:$idx))>;
 
+// lane replacement
+multiclass ReplaceLane<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
+                       ValueType lane_t, ImmLeaf imm_t, bits<32> simdop> {
+  defm REPLACE_LANE_#vec_t : SIMD_I<(outs V128:$dst),
+                                    (ins V128:$vec, I32:$idx, reg_t:$x),
+                                    (outs), (ins I32:$idx),
+                                    [(set V128:$dst, (vector_insert
+                                      (vec_t V128:$vec),
+                                      (lane_t reg_t:$x),
+                                      (i32 imm_t:$idx)))],
+                                    vec#".replace_lane\t$dst, $vec, $idx, $x",
+                                    vec#".replace_lane\t$idx", simdop>;
+}
+let Defs = [ARGUMENTS] in {
+defm "" : ReplaceLane<v16i8, "i8x16", I32, i32, LaneIdx16, 17>;
+defm "" : ReplaceLane<v8i16, "i16x8", I32, i32, LaneIdx8, 18>;
+defm "" : ReplaceLane<v4i32, "i32x4", I32, i32, LaneIdx4, 19>;
+defm "" : ReplaceLane<v2i64, "i64x2", I64, i64, LaneIdx2, 20>;
+defm "" : ReplaceLane<v4f32, "f32x4", F32, f32, LaneIdx4, 21>;
+defm "" : ReplaceLane<v2f64, "f64x2", F64, f64, LaneIdx2, 22>;
+} // Defs = [ARGUMENTS]
 
 // splats
 def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
 def splat4 : PatFrag<(ops node:$x), (build_vector
                        node:$x, node:$x, node:$x, node:$x)>;
 def splat8 : PatFrag<(ops node:$x), (build_vector
                        node:$x, node:$x, node:$x, node:$x,
                        node:$x, node:$x, node:$x, node:$x)>;

 }
 let Defs = [ARGUMENTS] in {
 defm "" : Splat<v16i8, "i8x16", I32, splat16, 3>;
 defm "" : Splat<v8i16, "i16x8", I32, splat8, 4>;
 defm "" : Splat<v4i32, "i32x4", I32, splat4, 5>;
 defm "" : Splat<v2i64, "i64x2", I64, splat2, 6>;
 defm "" : Splat<v4f32, "f32x4", F32, splat4, 7>;
 defm "" : Splat<v2f64, "f64x2", F64, splat2, 8>;
-}
+} // Defs = [ARGUMENTS]
 
 // arithmetic
 let Defs = [ARGUMENTS] in {
 let isCommutable = 1 in
 defm ADD : SIMDBinaryInt<add, "add ", 24>;
 defm SUB : SIMDBinaryInt<sub, "sub ", 28>;
 let isCommutable = 1 in
 defm MUL : SIMDBinaryInt<mul, "mul ", 32>;
 let isCommutable = 1 in
 defm ADD : SIMDBinaryFP<fadd, "add ", 122>;
 defm SUB : SIMDBinaryFP<fsub, "sub ", 124>;
 defm DIV : SIMDBinaryFP<fdiv, "div ", 126>;
 let isCommutable = 1 in
 defm MUL : SIMDBinaryFP<fmul, "mul ", 128>;
 } // Defs = [ARGUMENTS]

llvm/trunk/test/CodeGen/WebAssembly/simd.ll

 ; SIMD128: .result i32{{$}}
 ; SIMD128: i8x16.extract_lane_u $push0=, $0, 13 # encoding: [0xfd,0x0a,0x0d]{{$}}
 ; SIMD128: return $pop0 #
 define i8 @extract_v16i8(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 13
   ret i8 %elem
 }
 
+; CHECK-LABEL: replace_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128: .param v128, i32{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i8x16.replace_lane $push0=, $0, 11, $1 # encoding: [0xfd,0x11,0x0b]{{$}}
+; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
+define <16 x i8> @replace_v16i8(<16 x i8> %v, i8 %x) {
+  %res = insertelement <16 x i8> %v, i8 %x, i32 11
+  ret <16 x i8> %res
+}
+
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: splat_v8i16:
 ; NO-SIMD128-NOT: i16x8
 ; SIMD128: .param i32{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i16x8.splat $push0=, $0 # encoding: [0xfd,0x04]{{$}}

 ; SIMD128: .result i32{{$}}
 ; SIMD128: i16x8.extract_lane_u $push0=, $0, 5 # encoding: [0xfd,0x0c,0x05]{{$}}
 ; SIMD128: return $pop0 #
 define i16 @extract_v8i16(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 5
   ret i16 %elem
 }
 
+; CHECK-LABEL: replace_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128: .param v128, i32{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i16x8.replace_lane $push0=, $0, 7, $1 # encoding: [0xfd,0x12,0x07]{{$}}
+; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
+define <8 x i16> @replace_v8i16(<8 x i16> %v, i16 %x) {
+  %res = insertelement <8 x i16> %v, i16 %x, i32 7
+  ret <8 x i16> %res
+}
+
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: splat_v4i32:
 ; NO-SIMD128-NOT: i32x4
 ; SIMD128: .param i32{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i32x4.splat $push0=, $0 # encoding: [0xfd,0x05]{{$}}

 ; SIMD128: .result i32{{$}}
 ; SIMD128: i32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0d,0x03]{{$}}
 ; SIMD128: return $pop0 #
 define i32 @extract_v4i32(<4 x i32> %v) {
   %elem = extractelement <4 x i32> %v, i32 3
   ret i32 %elem
 }
 
+; CHECK-LABEL: replace_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128: .param v128, i32{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i32x4.replace_lane $push0=, $0, 2, $1 # encoding: [0xfd,0x13,0x02]{{$}}
+; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
+define <4 x i32> @replace_v4i32(<4 x i32> %v, i32 %x) {
+  %res = insertelement <4 x i32> %v, i32 %x, i32 2
+  ret <4 x i32> %res
+}
+
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: splat_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param i64{{$}}
 ; SIMD128: .result v128{{$}}

 ; SIMD128: .result i64{{$}}
 ; SIMD128: i64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x0e,0x01]{{$}}
 ; SIMD128: return $pop0 #
 define i64 @extract_v2i64(<2 x i64> %v) {
   %elem = extractelement <2 x i64> %v, i64 1
   ret i64 %elem
 }
 
+; CHECK-LABEL: replace_v2i64:
+; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: i64x2
+; SIMD128: .param v128, i64{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i64x2.replace_lane $push0=, $0, 0, $1 # encoding: [0xfd,0x14,0x00]{{$}}
+; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
+define <2 x i64> @replace_v2i64(<2 x i64> %v, i64 %x) {
+  %res = insertelement <2 x i64> %v, i64 %x, i32 0
+  ret <2 x i64> %res
+}
+
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================
 ; CHECK-LABEL: splat_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128: .param f32{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: f32x4.splat $push0=, $0 # encoding: [0xfd,0x07]{{$}}

 ; SIMD128: .result f32{{$}}
 ; SIMD128: f32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0f,0x03]{{$}}
 ; SIMD128: return $pop0 #
 define float @extract_v4f32(<4 x float> %v) {
   %elem = extractelement <4 x float> %v, i32 3
   ret float %elem
 }
 
+; CHECK-LABEL: replace_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128: .param v128, f32{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: f32x4.replace_lane $push0=, $0, 2, $1 # encoding: [0xfd,0x15,0x02]{{$}}
+; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
+define <4 x float> @replace_v4f32(<4 x float> %v, float %x) {
+  %res = insertelement <4 x float> %v, float %x, i32 2
+  ret <4 x float> %res
+}
+
 ; ==============================================================================
 ; 2 x f64
 ; ==============================================================================
 ; CHECK-LABEL: splat_v2f64:
 ; NO-SIMD128-NOT: f64x2
 ; SIMD128-VM-NOT: f64x2
 ; SIMD128: .param f64{{$}}
 ; SIMD128: .result v128{{$}}

 ; SIMD128: .param v128{{$}}
 ; SIMD128: .result f64{{$}}
 ; SIMD128: f64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x10,0x01]{{$}}
 ; SIMD128: return $pop0 #
 define double @extract_v2f64(<2 x double> %v) {
   %elem = extractelement <2 x double> %v, i32 1
   ret double %elem
 }
+
+; CHECK-LABEL: replace_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128: .param v128, f64{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: f64x2.replace_lane $push0=, $0, 0, $1 # encoding: [0xfd,0x16,0x00]{{$}}
+; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
+define <2 x double> @replace_v2f64(<2 x double> %v, double %x) {
+  %res = insertelement <2 x double> %v, double %x, i32 0
+  ret <2 x double> %res
+}