[WebAssembly] Gate i64x2 and f64x2 on -wasm-enable-unimplemented

[tlively]

Summary

i64x2 and f64x2 operations are not implemented in V8, so we normally
do not want to emit them. However, they are in the SIMD spec proposal,
so we still want to be able to test them in the toolchain. This patch
adds a flag to enable their emission.

[dschuff]

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

45

Could putting this declaration in WebAssemblyTargetMachine.h avoid all these extern declarations?

[tlively]

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

45

Not all, just some.

[aheejin]

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

49

Are we planning to use this flag only for simd or also for other instructions? For example, exception handling is not currently implemented in the VM yet, but we are adding opcodes for it (under -mattr=+exception-handling flag). And in case if other stage 0~1 proposals come up, we may want to add them in the toolchain before they are implemented in the VM. Are we gonna use this flag for all these cases? If not, how about changing it to wasm-enable-unimplemented-simd?

test/CodeGen/WebAssembly/simd-arith.ll

11

How about leaving the meaning of SIMD128 as is and create another check mode for SIMD without the two opcodes? That way we can only delete that when we have the remaining two in the VM. And I think that also makes more sense if we are eventually gonna have them in the VM.

[tlively]

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

45

It also doesn't work that way because you end up with duplicate symbols.

[aheejin]

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

45

I guess what he meant is putting the definition where it is now and putting that extern declaration in the header file, but anyway.

[tlively]

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

49

It may make sense to use the same flag for all cases where ops are implemented in the toolchain but not the VM. However, I'd be happy to change the name if this will only be used for SIMD. Would you want to have a single general flag for this use case, or are other existing mechanisms sufficient?

[tlively]

• Update FileCheck prefixes

[aheejin]

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

49

I don't think we need a separate flag that handles all unimplemented opcodes because we already have feature flags for each not-fully-implemented-and-ongoing feature. If we have enough cases like this, where a feature is controlled by a feature flag but we need a separation even within it, using this flag for all those cases might make sense. But before that, I guess making it clear that this applies only for SIMD is less confusing, because currently it sounds like it encompasses all unimplemented features.

[aheejin]

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

45

Would WebAssembly.h work then?

[tlively]

• Change flag name, move extern decl to header

[tlively]

Addressed comments

[aheejin]

lib/Target/WebAssembly/WebAssembly.h

21

Hmm, I'm not sure if we want to include this big header (and all other headers included by it) into all WebAssembly cpp files. Sorry. Maybe the original way would be better..?

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

49

Nit: can you also change the variable name to include simd?

[tlively]

• Restore individual extern decls

[tlively]

• Update flag variable name

[dschuff]

lib/Target/WebAssembly/WebAssemblyFastISel.cpp

688

I don't think it's necessary to have checks at every single place where these types are used. It's enough e.g. to prevent them from reaching here with a check somewhere else, but still handle everything once the instructions get here. (Basically the same reason we have unconditional definitions and handling for simd instructions in some places, but have checks on the SIMD cpu feature in other places.

[tlively]

• Remove all redundant checks

[tlively]

Without all the checks I believe to be redundant this CL is much, much smaller. I'm concerned that it's possible the checks could save me a great deal of pain down the road, though.

[tlively]

@aheejin I think this is ready to land if it looks good to you

lib/Target/WebAssembly/WebAssembly.h

 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLY_H
 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLY_H
 
 #include "llvm/PassRegistry.h"
 #include "llvm/Support/CodeGen.h"
+#include "llvm/Support/CommandLine.h"
 
 namespace llvm {
 
+extern cl::opt<bool> EnableUnimplementedWasmInstrs;
+
 class WebAssemblyTargetMachine;
 class ModulePass;
 class FunctionPass;
 
 // LLVM IR passes.
 ModulePass *createWebAssemblyLowerEmscriptenEHSjLj(bool DoEH, bool DoSjLj);
 ModulePass *createWebAssemblyLowerGlobalDtors();
 ModulePass *createWebAssemblyAddMissingPrototypes();

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

 #include "llvm/MC/MCSymbolWasm.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
 //===----------------------------------------------------------------------===//
 // Helpers.
 //===----------------------------------------------------------------------===//
 
 MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const {
   const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
   const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
   for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
-                MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
+                MVT::v4i32, MVT::v4f32})
+    if (TRI->isTypeLegalForClass(*TRC, T))
+      return T;
+  if (EnableUnimplementedWasmInstrs)
+    for (MVT T : {MVT::v2i64, MVT::v2f64})
       if (TRI->isTypeLegalForClass(*TRC, T))
         return T;
   LLVM_DEBUG(errs() << "Unknown type for register number: " << RegNo);
   llvm_unreachable("Unknown register type");
   return MVT::Other;
 }
 
 std::string WebAssemblyAsmPrinter::regToString(const MachineOperand &MO) {
   unsigned RegNo = MO.getReg();
   assert(TargetRegisterInfo::isVirtualRegister(RegNo) &&
void WebAssemblyAsmPrinter::EmitFunctionBodyStart() {
 
   AsmPrinter::EmitFunctionBodyStart();
 }
 
 void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   LLVM_DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n');
 
   switch (MI->getOpcode()) {
+  case WebAssembly::ARGUMENT_v2i64:
+  case WebAssembly::ARGUMENT_v2f64:
+    if (!EnableUnimplementedWasmInstrs)
+      llvm_unreachable("unexpected argument type");
   case WebAssembly::ARGUMENT_I32:
   case WebAssembly::ARGUMENT_I64:
   case WebAssembly::ARGUMENT_F32:
   case WebAssembly::ARGUMENT_F64:
   case WebAssembly::ARGUMENT_v16i8:
   case WebAssembly::ARGUMENT_v8i16:
   case WebAssembly::ARGUMENT_v4i32:
-  case WebAssembly::ARGUMENT_v2i64:
   case WebAssembly::ARGUMENT_v4f32:
-  case WebAssembly::ARGUMENT_v2f64:
     // These represent values which are live into the function entry, so there's
     // no instruction to emit.
     break;
+  case WebAssembly::FALLTHROUGH_RETURN_v2i64:
+  case WebAssembly::FALLTHROUGH_RETURN_v2f64:
+    if (!EnableUnimplementedWasmInstrs)
+      llvm_unreachable("unexpected return type");
   case WebAssembly::FALLTHROUGH_RETURN_I32:
   case WebAssembly::FALLTHROUGH_RETURN_I64:
   case WebAssembly::FALLTHROUGH_RETURN_F32:
   case WebAssembly::FALLTHROUGH_RETURN_F64:
   case WebAssembly::FALLTHROUGH_RETURN_v16i8:
   case WebAssembly::FALLTHROUGH_RETURN_v8i16:
   case WebAssembly::FALLTHROUGH_RETURN_v4i32:
-  case WebAssembly::FALLTHROUGH_RETURN_v2i64:
-  case WebAssembly::FALLTHROUGH_RETURN_v4f32:
-  case WebAssembly::FALLTHROUGH_RETURN_v2f64: {
+  case WebAssembly::FALLTHROUGH_RETURN_v4f32: {
+
     // These instructions represent the implicit return at the end of a
     // function body. The operand is always a pop.
     assert(MFI->isVRegStackified(MI->getOperand(0).getReg()));
 
     if (isVerbose()) {
       OutStreamer->AddComment("fallthrough-return: $pop" +
                               Twine(MFI->getWARegStackId(
                                   MFI->getWAReg(MI->getOperand(0).getReg()))));

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

static void FixEndsAtEndOfFunction(
     DenseMap<const MachineInstr *, MachineInstr *> &LoopTops) {
   assert(MFI.getResults().size() <= 1);
 
   if (MFI.getResults().empty())
     return;
 
   WebAssembly::ExprType retType;
   switch (MFI.getResults().front().SimpleTy) {
+  case MVT::ExceptRef:
+    retType = WebAssembly::ExprType::ExceptRef;
+    break;
   case MVT::i32: retType = WebAssembly::ExprType::I32; break;
   case MVT::i64: retType = WebAssembly::ExprType::I64; break;
   case MVT::f32: retType = WebAssembly::ExprType::F32; break;
   case MVT::f64: retType = WebAssembly::ExprType::F64; break;
   case MVT::v16i8:
   case MVT::v8i16:
   case MVT::v4i32:
-  case MVT::v2i64:
   case MVT::v4f32:
+    retType = WebAssembly::ExprType::V128;
+    break;
+  case MVT::v2i64:
   case MVT::v2f64:
+    if (EnableUnimplementedWasmInstrs) {
       retType = WebAssembly::ExprType::V128;
       break;
-  case MVT::ExceptRef: retType = WebAssembly::ExprType::ExceptRef; break;
-  default: llvm_unreachable("unexpected return type");
+    }
+  default:
+    llvm_unreachable("unexpected return type");
   }
 
   for (MachineBasicBlock &MBB : reverse(MF)) {
     for (MachineInstr &MI : reverse(MBB)) {
       if (MI.isPosition() || MI.isDebugInstr())
         continue;
       if (MI.getOpcode() == WebAssembly::END_BLOCK) {
         BlockTops[&MI]->getOperand(0).setImm(int32_t(retType));

lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp

static unsigned GetNonPseudoCallIndirectOpcode(const MachineInstr &MI) {
   case PCALL_INDIRECT_VOID: return CALL_INDIRECT_VOID;
   case PCALL_INDIRECT_I32: return CALL_INDIRECT_I32;
   case PCALL_INDIRECT_I64: return CALL_INDIRECT_I64;
   case PCALL_INDIRECT_F32: return CALL_INDIRECT_F32;
   case PCALL_INDIRECT_F64: return CALL_INDIRECT_F64;
   case PCALL_INDIRECT_v16i8: return CALL_INDIRECT_v16i8;
   case PCALL_INDIRECT_v8i16: return CALL_INDIRECT_v8i16;
   case PCALL_INDIRECT_v4i32: return CALL_INDIRECT_v4i32;
-  case PCALL_INDIRECT_v2i64: return CALL_INDIRECT_v2i64;
   case PCALL_INDIRECT_v4f32: return CALL_INDIRECT_v4f32;
-  case PCALL_INDIRECT_v2f64: return CALL_INDIRECT_v2f64;
+  case PCALL_INDIRECT_v2i64:
+    if (EnableUnimplementedWasmInstrs)
+      return CALL_INDIRECT_v2i64;
+    else
+      llvm_unreachable("unexpected call type");
+  case PCALL_INDIRECT_v2f64:
+    if (EnableUnimplementedWasmInstrs)
+      return CALL_INDIRECT_v2f64;
+    else
+      llvm_unreachable("unexpected call type");
   default: return INSTRUCTION_LIST_END;
   }
 }
 
 static bool IsPseudoCallIndirect(const MachineInstr &MI) {
   return GetNonPseudoCallIndirectOpcode(MI) !=
          WebAssembly::INSTRUCTION_LIST_END;
 }

lib/Target/WebAssembly/WebAssemblyFastISel.cpp

MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
     case MVT::f64:
     case MVT::ExceptRef:
       return VT;
     case MVT::f16:
       return MVT::f32;
     case MVT::v16i8:
     case MVT::v8i16:
     case MVT::v4i32:
-    case MVT::v2i64:
     case MVT::v4f32:
-    case MVT::v2f64:
       if (Subtarget->hasSIMD128())
         return VT;
       break;
+    case MVT::v2i64:
+    case MVT::v2f64:
+      if (Subtarget->hasSIMD128() && EnableUnimplementedWasmInstrs)
+        return VT;
+      break;
     default:
       break;
     }
     return MVT::INVALID_SIMPLE_VALUE_TYPE;
   }
   bool computeAddress(const Value *Obj, Address &Addr);
   void materializeLoadStoreOperands(Address &Addr);
   void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
case MVT::v8i16:
       Opc = WebAssembly::ARGUMENT_v8i16;
       RC = &WebAssembly::V128RegClass;
       break;
     case MVT::v4i32:
       Opc = WebAssembly::ARGUMENT_v4i32;
       RC = &WebAssembly::V128RegClass;
       break;
     case MVT::v2i64:
+      if (!EnableUnimplementedWasmInstrs)
+        llvm_unreachable("unexpected argument type");
       Opc = WebAssembly::ARGUMENT_v2i64;
       RC = &WebAssembly::V128RegClass;
       break;
     case MVT::v4f32:
       Opc = WebAssembly::ARGUMENT_v4f32;
       RC = &WebAssembly::V128RegClass;
       break;
     case MVT::v2f64:
+      if (!EnableUnimplementedWasmInstrs)
+        llvm_unreachable("unexpected argument type");
       Opc = WebAssembly::ARGUMENT_v2f64;
       RC = &WebAssembly::V128RegClass;
       break;
     case MVT::ExceptRef:
       Opc = WebAssembly::ARGUMENT_EXCEPT_REF;
       RC = &WebAssembly::EXCEPT_REFRegClass;
       break;
     default:
case MVT::v8i16:
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
     case MVT::v4i32:
       Opc =
           IsDirect ? WebAssembly::CALL_v4i32 : WebAssembly::PCALL_INDIRECT_v4i32;
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
     case MVT::v2i64:
+      if (!EnableUnimplementedWasmInstrs)
+        llvm_unreachable("unexpected return type");
       Opc =
           IsDirect ? WebAssembly::CALL_v2i64 : WebAssembly::PCALL_INDIRECT_v2i64;
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
     case MVT::v4f32:
       Opc =
           IsDirect ? WebAssembly::CALL_v4f32 : WebAssembly::PCALL_INDIRECT_v4f32;
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
     case MVT::v2f64:
+      if (!EnableUnimplementedWasmInstrs)
+        llvm_unreachable("unexpected return type");
       Opc =
           IsDirect ? WebAssembly::CALL_v2f64 : WebAssembly::PCALL_INDIRECT_v2f64;
       ResultReg = createResultReg(&WebAssembly::V128RegClass);
       break;
     case MVT::ExceptRef:
       Opc = IsDirect ? WebAssembly::CALL_EXCEPT_REF
                      : WebAssembly::PCALL_INDIRECT_EXCEPT_REF;
       ResultReg = createResultReg(&WebAssembly::EXCEPT_REFRegClass);
case MVT::v16i8:
     break;
   case MVT::v8i16:
     Opc = WebAssembly::RETURN_v8i16;
     break;
   case MVT::v4i32:
     Opc = WebAssembly::RETURN_v4i32;
     break;
   case MVT::v2i64:
+    if (!EnableUnimplementedWasmInstrs)
+      llvm_unreachable("unexpected return type");
     Opc = WebAssembly::RETURN_v2i64;
     break;
   case MVT::v4f32:
     Opc = WebAssembly::RETURN_v4f32;
     break;
   case MVT::v2f64:
+    if (!EnableUnimplementedWasmInstrs)
+      llvm_unreachable("unexpected return type");
     Opc = WebAssembly::RETURN_v2f64;
     break;
   case MVT::ExceptRef:
     Opc = WebAssembly::RETURN_EXCEPT_REF;
     break;
   default: return false;
   }
 

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file implements the WebAssemblyTargetLowering class.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyISelLowering.h"
 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
+#include "WebAssembly.h"
 #include "WebAssemblyMachineFunctionInfo.h"
 #include "WebAssemblySubtarget.h"
 #include "WebAssemblyTargetMachine.h"
 #include "llvm/CodeGen/Analysis.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
   addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
   addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
   addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
   addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
   if (Subtarget->hasSIMD128()) {
     addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
-    addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
+    if (EnableUnimplementedWasmInstrs) {
+      addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
       addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
     }
+  }
   // Compute derived properties from the register classes.
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
   setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
   setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
   setOperationAction(ISD::JumpTable, MVTPtr, Custom);
   setOperationAction(ISD::BlockAddress, MVTPtr, Custom);
   setOperationAction(ISD::BRIND, MVT::Other, Custom);

lib/Target/WebAssembly/WebAssemblyPeephole.cpp

for (auto &MI : MBB)
             WebAssembly::COPY_V128);
         break;
       case WebAssembly::RETURN_v4i32:
         Changed |= MaybeRewriteToFallthrough(
             MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_v4i32,
             WebAssembly::COPY_V128);
         break;
       case WebAssembly::RETURN_v2i64:
+        if (!EnableUnimplementedWasmInstrs)
+          llvm_unreachable("unexpected return type");
         Changed |= MaybeRewriteToFallthrough(
             MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_v2i64,
             WebAssembly::COPY_V128);
         break;
       case WebAssembly::RETURN_v4f32:
         Changed |= MaybeRewriteToFallthrough(
             MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_v4f32,
             WebAssembly::COPY_V128);
         break;
       case WebAssembly::RETURN_v2f64:
+        if (!EnableUnimplementedWasmInstrs)
+          llvm_unreachable("unexpected return type");
         Changed |= MaybeRewriteToFallthrough(
             MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_v2f64,
             WebAssembly::COPY_V128);
         break;
       case WebAssembly::RETURN_VOID:
         Changed |= MaybeRewriteToFallthrough(
             MI, MBB, MF, MFI, MRI, TII, WebAssembly::FALLTHROUGH_RETURN_VOID,
             WebAssembly::INSTRUCTION_LIST_END);
         break;
       }
 
   return Changed;
 }

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

static cl::opt<bool> EnableEmException(
     cl::init(false));
 
 // Emscripten's asm.js-style setjmp/longjmp handling
 static cl::opt<bool> EnableEmSjLj(
     "enable-emscripten-sjlj",
     cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
     cl::init(false));
 
+// Emit proposed instructions that may not have been implemented in engines
+cl::opt<bool> llvm::EnableUnimplementedWasmInstrs(
+    "wasm-enable-unimplemented-simd",
+    cl::desc("Emit potentially-unimplemented WebAssembly SIMD instructions"),
+    cl::init(false));
+
 extern "C" void LLVMInitializeWebAssemblyTarget() {
   // Register the target.
   RegisterTargetMachine<WebAssemblyTargetMachine> X(
       getTheWebAssemblyTarget32());
   RegisterTargetMachine<WebAssemblyTargetMachine> Y(
       getTheWebAssemblyTarget64());
 
   // Register backend passes

lib/Target/WebAssembly/WebAssemblyUtilities.cpp

 //===-- WebAssemblyUtilities.cpp - WebAssembly Utility Functions ----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file implements several utility functions for WebAssembly.
 ///
 //===----------------------------------------------------------------------===//
 
+#include "WebAssembly.h"
 #include "WebAssemblyUtilities.h"
 #include "WebAssemblyMachineFunctionInfo.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 using namespace llvm;
 
 const char *const WebAssembly::ClangCallTerminateFn = "__clang_call_terminate";
 const char *const WebAssembly::CxaBeginCatchFn = "__cxa_begin_catch";
 const char *const WebAssembly::CxaRethrowFn = "__cxa_rethrow";
 const char *const WebAssembly::StdTerminateFn = "_ZSt9terminatev";
 const char *const WebAssembly::PersonalityWrapperFn =
     "_Unwind_Wasm_CallPersonality";
 
 bool WebAssembly::isArgument(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   case WebAssembly::ARGUMENT_I32:
   case WebAssembly::ARGUMENT_I64:
   case WebAssembly::ARGUMENT_F32:
   case WebAssembly::ARGUMENT_F64:
   case WebAssembly::ARGUMENT_v16i8:
   case WebAssembly::ARGUMENT_v8i16:
   case WebAssembly::ARGUMENT_v4i32:
-  case WebAssembly::ARGUMENT_v2i64:
   case WebAssembly::ARGUMENT_v4f32:
+    return true;
+  case WebAssembly::ARGUMENT_v2i64:
   case WebAssembly::ARGUMENT_v2f64:
+    if (EnableUnimplementedWasmInstrs) {
       return true;
+    }
   default:
     return false;
   }
 }
 
 bool WebAssembly::isCopy(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   case WebAssembly::COPY_I32:
bool WebAssembly::isCallDirect(const MachineInstr &MI) {
   case WebAssembly::CALL_VOID:
   case WebAssembly::CALL_I32:
   case WebAssembly::CALL_I64:
   case WebAssembly::CALL_F32:
   case WebAssembly::CALL_F64:
   case WebAssembly::CALL_v16i8:
   case WebAssembly::CALL_v8i16:
   case WebAssembly::CALL_v4i32:
-  case WebAssembly::CALL_v2i64:
   case WebAssembly::CALL_v4f32:
-  case WebAssembly::CALL_v2f64:
   case WebAssembly::CALL_EXCEPT_REF:
     return true;
+  case WebAssembly::CALL_v2i64:
+  case WebAssembly::CALL_v2f64:
+    if (EnableUnimplementedWasmInstrs)
+      return true;
   default:
     return false;
   }
 }
 
 bool WebAssembly::isCallIndirect(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   case WebAssembly::CALL_INDIRECT_VOID:
   case WebAssembly::CALL_INDIRECT_I32:
   case WebAssembly::CALL_INDIRECT_I64:
   case WebAssembly::CALL_INDIRECT_F32:
   case WebAssembly::CALL_INDIRECT_F64:
   case WebAssembly::CALL_INDIRECT_v16i8:
   case WebAssembly::CALL_INDIRECT_v8i16:
   case WebAssembly::CALL_INDIRECT_v4i32:
-  case WebAssembly::CALL_INDIRECT_v2i64:
   case WebAssembly::CALL_INDIRECT_v4f32:
-  case WebAssembly::CALL_INDIRECT_v2f64:
   case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
     return true;
+  case WebAssembly::CALL_INDIRECT_v2i64:
+  case WebAssembly::CALL_INDIRECT_v2f64:
+    if (EnableUnimplementedWasmInstrs)
+      return true;
   default:
     return false;
   }
 }
 
 unsigned WebAssembly::getCalleeOpNo(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   case WebAssembly::CALL_VOID:

test/CodeGen/WebAssembly/simd-arith.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that basic SIMD128 arithmetic operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; ==============================================================================
 ; 16 x i8
 ; ==============================================================================
 ; CHECK-LABEL: add_v16i8
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %a
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: add_v2i64
 ; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i64x2.add $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = add <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: sub_v2i64
 ; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i64x2.sub $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = sub <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: mul_v2i64
 ; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: i64x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: i64x2.mul $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = mul <2 x i64> %x, %y
   ret <2 x i64> %a
 }
define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %a
 }
 
 ; ==============================================================================
 ; 2 x double
 ; ==============================================================================
 ; CHECK-LABEL: add_v2f64
 ; NO-SIMD128-NOT: f64x2
+; SIMD129-VM-NOT: f62x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: f64x2.add $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fadd <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: sub_v2f64
 ; NO-SIMD128-NOT: f64x2
+; SIMD129-VM-NOT: f62x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: f64x2.sub $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fsub <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: div_v2f64
 ; NO-SIMD128-NOT: f64x2
+; SIMD129-VM-NOT: f62x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: f64x2.div $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fdiv <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: mul_v2f64
 ; NO-SIMD128-NOT: f64x2
+; SIMD129-VM-NOT: f62x2
 ; SIMD128: .param v128, v128{{$}}
 ; SIMD128: .result v128{{$}}
 ; SIMD128: f64x2.mul $push0=, $0, $1{{$}}
 ; SIMD128: return $pop0{{$}}
 define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fmul <2 x double> %x, %y
   ret <2 x double> %a
 }