Fix uninitialized read in ARM's PrintAsmOperand

[thopre]

Summary

Fix read of uninitialized RC variable in ARM's PrintAsmOperand when
hasRegClassConstraint returns false. This was causing
inline-asm-operand-implicit-cast test to fail in r338206.

[chill]

lib/Target/ARM/ARMAsmPrinter.cpp

379

Is this doing the right thing for big-endian? (re: https://reviews.llvm.org/D49778)
(arguably a slightly separate issue, indeed).

[thopre]

lib/Target/ARM/ARMAsmPrinter.cpp

379

Apparently not but this is an independent problem (ie. the patch does not touch this) and would be fixed by Jackson's patch. Do you mean that Jackson's patch should go in first and be marked as a dependency of this one?

[chill]

lib/Target/ARM/ARMAsmPrinter.cpp

379

Well, duh, apparently I didn't pay enough attention to notice these patches change the same part of the code. It would be nice to sequence them, as they would probably create a merge conflict?

[chill]

LGTM.

lib/Target/ARM/ARMAsmPrinter.cpp

case 'Q': { // The least significant register of a pair.
 
         // Later code expects OpNum to be pointing at the register rather than
         // the flags.
         OpNum += 1;
       }
 
       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
       unsigned RC;
-      InlineAsm::hasRegClassConstraint(Flags, RC);
-      if (RC == ARM::GPRPairRegClassID) {
+      const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
+      if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
+          ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
         if (NumVals != 1)
           return true;
         const MachineOperand &MO = MI->getOperand(OpNum);
         if (!MO.isReg())
           return true;
         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
             ARM::gsub_0 : ARM::gsub_1);
         O << ARMInstPrinter::getRegisterName(Reg);
         return false;
       }
       if (NumVals != 2)
         return true;
       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
       if (RegOp >= MI->getNumOperands())

test/CodeGen/ARM/inlineasm-64bit.ll

 ; we were tied to for information about register class and so on.
 define i64 @tied_64bit_lookback_test(i64 %in) nounwind {
 ; CHECK-LABEL: tied_64bit_lookback_test:
 ; CHECK: OUTLO([[LO:r[0-9]+]]) OUTHI([[HI:r[0-9]+]]) INLO([[LO]]) INHI([[HI]])
   %vars = call {i64, i32, i64} asm "OUTLO(${2:Q}) OUTHI(${2:R}) INLO(${3:Q}) INHI(${3:R})", "=r,=r,=r,2"(i64 %in)
   %res = extractvalue {i64, i32, i64} %vars, 2
   ret i64 %res
 }
+
+; Check access to low and high part with a specific register pair constraint
+define i64 @low_high_specific_reg_pair(i64 %in) nounwind {
+; CHECK-LABEL: low_high_specific_reg_pair
+; CHECK: mov r3, r2
+  %res = call i64 asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(i64 %in)
+  ret i64 %res
+}