[GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants.

[aemerson]

Summary

Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants.

[rtereshin]

Besides a nitpick, LGTM

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

952

If this is evident from the operand type I'd drop the comment. Could a BlockAddress be something else, not "an IR block address value"?
Just a nitpick, not blocking.

[aemerson]

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

952

True, it's a bit redundant.

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

public:
   /// \pre \p OldValRes must be a generic virtual register.
   /// \pre \p Addr must be a generic virtual register with pointer type.
   /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
   ///      same type.
   ///
   /// \return a MachineInstrBuilder for the newly created instruction.
   MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
                                          unsigned Val, MachineMemOperand &MMO);
+
+  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
+  ///
+  /// G_BLOCK_ADDR computes the address of a basic block.
+  ///
+  /// \pre setBasicBlock or setMI must have been called.
+  /// \pre \p Res must be a generic virtual register of a pointer type.
+  /// \pre \p BA must be an IR block address value.
+  ///
+  /// \return The newly created instruction.
+  MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
 };
 
 /// A CRTP class that contains methods for building instructions that can
 /// be constant folded. MachineIRBuilders that want to inherit from this will
 /// need to implement buildBinaryOp (for constant folding binary ops).
 /// Alternatively, they can implement buildInstr(Opc, Dst, Uses...) to perform
 /// additional folding for Opc.
 template <typename Base>

include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
 
 /// Generic byte swap.
 HANDLE_TARGET_OPCODE(G_BSWAP)
 
 /// Generic AddressSpaceCast.
 HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST)
 
+/// Generic block address
+HANDLE_TARGET_OPCODE(G_BLOCK_ADDR)
+
 // TODO: Add more generic opcodes as we move along.
 
 /// Marker for the end of the generic opcode.
 /// This is used to check if an opcode is in the range of the
 /// generic opcodes.
-HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_ADDRSPACE_CAST)
+HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_BLOCK_ADDR)
 
 /// BUILTIN_OP_END - This must be the last enum value in this list.
 /// The target-specific post-isel opcode values start here.
 HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END)

include/llvm/Target/GenericOpcodes.td

def G_BSWAP : GenericInstruction {
   let hasSideEffects = 0;
 }
 
 def G_ADDRSPACE_CAST : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$src);
   let hasSideEffects = 0;
 }
+
+def G_BLOCK_ADDR : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins unknown:$ba);
+  let hasSideEffects = 0;
+}
+
 //------------------------------------------------------------------------------
 // Binary ops.
 //------------------------------------------------------------------------------
 
 // Generic addition.
 def G_ADD : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1, type0:$src2);

lib/CodeGen/GlobalISel/IRTranslator.cpp

#include "llvm/IR/Instruction.def"
   } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
     if (CV->getNumOperands() == 1)
       return translate(*CV->getOperand(0), Reg);
     SmallVector<unsigned, 4> Ops;
     for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
       Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
     }
     EntryBuilder.buildMerge(Reg, Ops);
+  } else if (auto *BA = dyn_cast<BlockAddress>(&C)) {
+    EntryBuilder.buildBlockAddress(Reg, BA);
   } else
     return false;
 
   return true;
 }
 
 void IRTranslator::finalizeFunction() {
   // Release the memory used by the different maps we

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

 }
 MachineInstrBuilder
 MachineIRBuilderBase::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
                                          unsigned Val, MachineMemOperand &MMO) {
   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
                         MMO);
 }
 
+MachineInstrBuilder
+MachineIRBuilderBase::buildBlockAddress(unsigned Res, const BlockAddress *BA) {
+#ifndef NDEBUG
+  assert(getType(Res).isPointer() && "invalid res type");
+#endif
+
+  return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
+}
+
 void MachineIRBuilderBase::validateTruncExt(unsigned Dst, unsigned Src,
                                             bool IsExtend) {
 #ifndef NDEBUG
   LLT SrcTy = getMRI()->getType(Src);
   LLT DstTy = getMRI()->getType(Dst);
 
   if (DstTy.isVector()) {
     assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 ; CHECK-NEXT:    [[OLDVALRES:%[0-9]+]]:_(s256) = G_ATOMICRMW_UMAX [[ADDR]](p0), [[VAL]] :: (load store seq_cst 32 on %ir.addr)
 ; CHECK-NEXT:    [[RES:%[0-9]+]]:_(s32) = G_TRUNC [[OLDVALRES]]
   %oldval = atomicrmw umax i256* %addr, i256 1 seq_cst
   ; FIXME: We currently can't lower 'ret i256' and it's not the purpose of this
   ;        test so work around it by truncating to i32 for now.
   %oldval.trunc = trunc i256 %oldval to i32
   ret i32 %oldval.trunc
 }
+
+@addr = global i8* null
+
+define void @test_blockaddress() {
+; CHECK-LABEL: name: test_blockaddress
+; CHECK: [[BADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block)
+; CHECK: G_STORE [[BADDR]](p0)
+  store i8* blockaddress(@test_blockaddress, %block), i8** @addr
+  indirectbr i8* blockaddress(@test_blockaddress, %block), [label %block]
+block:
+  ret void
+}