[AArch64][ARM] Armv8.2-A: Add the Floating Point Multiplication Variants

[SjoerdMeijer]

Fixed typo

[bogden]

Until we define a separate feature for these instructions, they should be predicated on HasV8_4a rather than HasV8_2A. Until v8.4-A they're optional even for CPUs that have HasFullFP16. Current v8.2-A Cortex CPUs, for example, do not support these instructions.

With that change it's probably fine as a part of the v8.4-A support, but I haven't reviewed the rest of it yet.

[SjoerdMeijer]

Ah, good point, thanks. But I will create a new target feature for this like we normally do (such as e.g. dotprod).

[SjoerdMeijer]

This work is continued in D50228.

lib/Target/AArch64/AArch64InstrFormats.td

class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<3> size, bits<5> opcode,
   let Inst{23-21} = size;
   let Inst{20-16} = Rm;
   let Inst{15-11} = opcode;
   let Inst{10}    = 1;
   let Inst{9-5}   = Rn;
   let Inst{4-0}   = Rd;
 }
 
+let Predicates = [HasV8_2a, HasNEON, HasFullFP16] in
+class BaseSIMDThreeSameMult<bit Q, bit U, bit b13, bits<3> size, string asm, string kind1,
+                                 string kind2> :
+        BaseSIMDThreeSameVector<Q, U, size, 0b11101, V128, asm, kind1, [] > {
+  let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");
+  let Inst{13} = b13;
+}
+
 class BaseSIMDThreeSameVectorDot<bit Q, bit U, string asm, string kind1,
                                  string kind2, RegisterOperand RegType,
                                  ValueType AccumType, ValueType InputType,
                                  SDPatternOperator OpNode> :
         BaseSIMDThreeSameVectorTied<Q, U, 0b100, 0b10010, RegType, asm, kind1,
         [(set (AccumType RegType:$dst),
               (OpNode (AccumType RegType:$Rd),
                       (InputType RegType:$Rn),
class BaseSIMDThreeSameVectorDotIndex<bit Q, bit U, string asm, string dst_kind,
                                  (InputType (bitconvert (AccumType
                                     (AArch64duplane32 (v4i32 V128:$Rm),
                                         VectorIndexS:$idx)))))))]> {
   bits<2> idx;
   let Inst{21}    = idx{0};  // L
   let Inst{11}    = idx{1};  // H
 }
 
+let Predicates = [HasV8_2a, HasNEON, HasFullFP16] in
+class BaseSIMDThreeSameMultIndex<bit Q, bit U, bits<4> opc, string asm,
+                                 string dst_kind, string lhs_kind,
+                                 string rhs_kind> :
+        BaseSIMDIndexedTied<Q, U, 0, 0b10, opc, V128, V128, V128,
+                            VectorIndexH, asm, "", dst_kind, lhs_kind,
+                            rhs_kind, []> {
+  //idx = H:L:M
+  bits<3> idx;
+  let Inst{11} = idx{2}; // H
+  let Inst{21} = idx{1}; // L
+  let Inst{20} = idx{0}; // M
+}
+
 multiclass SIMDThreeSameVectorDotIndex<bit U, string asm,
                                        SDPatternOperator OpNode> {
   def v8i8  : BaseSIMDThreeSameVectorDotIndex<0, U, asm, ".2s", ".8b", ".4b", V64,
                                               v2i32, v8i8, OpNode>;
   def v16i8 : BaseSIMDThreeSameVectorDotIndex<1, U, asm, ".4s", ".16b", ".4b", V128,
                                               v4i32, v16i8, OpNode>;
 }
 

lib/Target/AArch64/AArch64InstrInfo.td

 defm URHADD   : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
 defm URSHL    : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
 defm USHL     : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
                                                   int_aarch64_neon_sqadd>;
 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
                                                     int_aarch64_neon_sqsub>;
 
+// Armv8.2-A Floating Point Multiplication Variants
+def FMLAL_2S   : BaseSIMDThreeSameMult<0, 0, 1, 0b001, "fmlal", ".2s", ".2h">;
+def FMLSL_2S   : BaseSIMDThreeSameMult<0, 0, 1, 0b101, "fmlsl", ".2s", ".2h">;
+def FMLAL_4S   : BaseSIMDThreeSameMult<1, 0, 1, 0b001, "fmlal", ".4s", ".4h">;
+def FMLSL_4S   : BaseSIMDThreeSameMult<1, 0, 1, 0b101, "fmlsl", ".4s", ".4h">;
+def FMLAL2_2S  : BaseSIMDThreeSameMult<0, 1, 0, 0b001, "fmlal2", ".2s", ".2h">;
+def FMLSL2_2S  : BaseSIMDThreeSameMult<0, 1, 0, 0b101, "fmlsl2", ".2s", ".2h">;
+def FMLAL2_4S  : BaseSIMDThreeSameMult<1, 1, 0, 0b001, "fmlal2", ".4s", ".4h">;
+def FMLSL2_4S  : BaseSIMDThreeSameMult<1, 1, 0, 0b101, "fmlsl2", ".4s", ".4h">;
+def FMLALI_2s  : BaseSIMDThreeSameMultIndex<0, 0, 0b0000, "fmlal", ".2s", ".2h", ".h">;
+def FMLSLI_2s  : BaseSIMDThreeSameMultIndex<0, 0, 0b0100, "fmlsl", ".2s", ".2h", ".h">;
+def FMLALI_4s  : BaseSIMDThreeSameMultIndex<1, 0, 0b0000, "fmlal", ".4s", ".4h", ".h">;
+def FMLSLI_4s  : BaseSIMDThreeSameMultIndex<1, 0, 0b0100, "fmlsl", ".4s", ".4h", ".h">;
+def FMLALI2_2s : BaseSIMDThreeSameMultIndex<0, 1, 0b1000, "fmlal2", ".2s", ".2h", ".h">;
+def FMLSLI2_2s : BaseSIMDThreeSameMultIndex<0, 1, 0b1100, "fmlsl2", ".2s", ".2h", ".h">;
+def FMLALI2_4s : BaseSIMDThreeSameMultIndex<1, 1, 0b1000, "fmlal2", ".4s", ".4h", ".h">;
+def FMLSLI2_4s : BaseSIMDThreeSameMultIndex<1, 1, 0b1100, "fmlsl2", ".4s", ".4h", ".h">;
+
 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
                                   BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
     TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;

lib/Target/ARM/ARMInstrFormats.td

class N3VLaneCP8<bit op23, bits<2> op21_20, bit op6, bit op4,
   let Inst{11-8}  = 0b1000;
   let Inst{7}     = Vn{4};
   let Inst{6}     = op6;
   // Bit 5 set by sub-classes
   let Inst{4}     = op4;
   let Inst{3-0}   = Vm{3-0};
 }
 
+// In Armv8.2-A, some NEON instructions are added that encode Vn and Vm
+// differently:
+//    if Q == ‘1’ then UInt(N:Vn) else UInt(Vn:N);
+//    if Q == ‘1’ then UInt(M:Vm) else UInt(Vm:M);
+// Class N3VCP8 above describes the Q=1 case, and this class the Q=0 case.
+class N3VCP8Q0<bits<2> op24_23, bits<2> op21_20, bit op6, bit op4,
+             dag oops, dag iops, InstrItinClass itin,
+             string opc, string dt, string asm, string cstr, list<dag> pattern>
+  : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N3RegCplxFrm, itin, opc, dt, asm, cstr, pattern> {
+  bits<5> Vd;
+  bits<5> Vn;
+  bits<5> Vm;
+
+  let DecoderNamespace = "VFPV8";
+  // These have the same encodings in ARM and Thumb2
+  let PostEncoderMethod = "";
+
+  let Inst{31-25} = 0b1111110;
+  let Inst{24-23} = op24_23;
+  let Inst{22}    = Vd{4};
+  let Inst{21-20} = op21_20;
+  let Inst{19-16} = Vn{4-1};
+  let Inst{15-12} = Vd{3-0};
+  let Inst{11-8}  = 0b1000;
+  let Inst{7}     = Vn{0};
+  let Inst{6}     = op6;
+  let Inst{5}     = Vm{0};
+  let Inst{4}     = op4;
+  let Inst{3-0}   = Vm{4-1};
+}
+
 // Operand types for complex instructions
 class ComplexRotationOperand<int Angle, int Remainder, string Type, string Diag>
   : AsmOperandClass {
   let PredicateMethod = "isComplexRotation<" # Angle # ", " # Remainder # ">";
   let DiagnosticString = "complex rotation must be " # Diag;
   let Name = "ComplexRotation" # Type;
 }
 def complexrotateop : Operand<i32> {

lib/Target/ARM/ARMInstrNEON.td

 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm",
                    (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
                    (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
                    (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
 }
 
+// Armv8.2-A Floating Point Multiplication Variants
+let Predicates = [HasNEON, HasV8_2a, HasFullFP16], DecoderNamespace= "VFPV8" in {
+
+class N3VCP8F16Q1<string asm, RegisterClass Td, RegisterClass Tn,
+                RegisterClass Tm, bits<2> op1, bits<2> op2, bit op3>
+  : N3VCP8<op1, op2, 1, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
+           asm, "f16", "$Vd, $Vn, $Vm", "", []>;
+
+class N3VCP8F16Q0<string asm, RegisterClass Td, RegisterClass Tn,
+                RegisterClass Tm, bits<2> op1, bits<2> op2, bit op3>
+  : N3VCP8Q0<op1, op2, 0, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
+           asm, "f16", "$Vd, $Vn, $Vm", "", []>;
+
+class VFMQ0<string opc, bits<2> S>
+  : N3VLaneCP8<0, S, 0, 1, (outs DPR:$Vd),
+               (ins SPR:$Vn, SPR:$Vm, VectorIndex32:$idx),
+               IIC_VMACD, opc, "f16", "$Vd, $Vn, $Vm$idx", "", []> {
+  bit idx;
+  let Inst{3} = idx;
+  let Inst{19-16} = Vn{4-1};
+  let Inst{7}     = Vn{0};
+  let Inst{5}     = Vm{0};
+  let Inst{2-0}   = Vm{3-1};
+}
+
+class VFMQ1<string opc, bits<2> S>
+  : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd),
+               (ins DPR:$Vn, DPR:$Vm, VectorIndex16:$idx),
+               IIC_VMACD, opc, "f16", "$Vd, $Vn, $Vm$idx", "", []> {
+  bits<2> idx;
+  let Inst{5} = idx{1};
+  let Inst{3} = idx{0};
+}
+
+let hasNoSchedulingInfo = 1 in {
+//                                                op1   op2   op3
+def VFMALD  : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>;
+def VFMSLD  : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>;
+def VFMALQ  : N3VCP8F16Q1<"vfmal", QPR, DPR, DPR, 0b00, 0b10, 1>;
+def VFMSLQ  : N3VCP8F16Q1<"vfmsl", QPR, DPR, DPR, 0b01, 0b10, 1>;
+def VFMALDI : VFMQ0<"vfmal", 0b00>;
+def VFMSLDI : VFMQ0<"vfmsl", 0b01>;
+def VFMALQI : VFMQ1<"vfmal", 0b00>;
+def VFMSLQI : VFMQ1<"vfmsl", 0b01>;
+}
+} // HasNEON, HasV8_2a, HasFullFP16
+
+
 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
                    (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
                    (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
                    (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
                    (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if ((Mnemonic == "movs" && isThumb()) ||
       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
       Mnemonic == "bxns"  || Mnemonic == "blxns" ||
       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
-      Mnemonic == "vcmla" || Mnemonic == "vcadd")
+      Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
+      Mnemonic == "vfmal" || Mnemonic == "vfmsl")
     return Mnemonic;
 
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
       Mnemonic != "sbcs" && Mnemonic != "rscs") {
if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
       Mnemonic == "vmovx" || Mnemonic == "vins" ||
       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
-      Mnemonic == "vcmla" || Mnemonic == "vcadd") {
+      Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
+      Mnemonic == "vfmal" || Mnemonic == "vfmsl") {
     // These mnemonics are never predicable
     CanAcceptPredicationCode = false;
   } else if (!isThumb()) {
     // Some instructions are only predicable in Thumb mode
     CanAcceptPredicationCode =
         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
         Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&

test/MC/AArch64/armv8.2a-fpmul-error.s

+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=CHECK
+
+//------------------------------------------------------------------------------
+// Armv8.4-A Floating Point Multiplication Variants
+//------------------------------------------------------------------------------
+
+fmlal  V0.2s, v1.2h, v2.h[8]
+fmlsl  V0.2s, v1.2h, v2.h[8]
+fmlal  V0.4s, v1.4h, v2.h[8]
+fmlsl  V0.4s, v1.4h, v2.h[8]
+
+fmlal2  V0.2s, v1.2h, v2.h[8]
+fmlsl2  V0.2s, v1.2h, v2.h[8]
+fmlal2  V0.4s, v1.4h, v2.h[8]
+fmlsl2  V0.4s, v1.4h, v2.h[8]
+
+fmlal  V0.2s, v1.2h, v2.h[-1]
+fmlsl2  V0.2s, v1.2h, v2.h[-1]
+
+//CHECK: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlal  V0.2s, v1.2h, v2.h[8]
+//CHECK-NEXT:                          ^
+//CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlsl  V0.2s, v1.2h, v2.h[8]
+//CHECK-NEXT:                          ^
+//CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlal  V0.4s, v1.4h, v2.h[8]
+//CHECK-NEXT:                          ^
+//CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlsl  V0.4s, v1.4h, v2.h[8]
+//CHECK-NEXT:                          ^
+
+//CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlal2  V0.2s, v1.2h, v2.h[8]
+//CHECK-NEXT:                           ^
+//CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlsl2  V0.2s, v1.2h, v2.h[8]
+//CHECK-NEXT:                           ^
+//CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlal2  V0.4s, v1.4h, v2.h[8]
+//CHECK-NEXT:                           ^
+//CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlsl2  V0.4s, v1.4h, v2.h[8]
+//CHECK-NEXT:                           ^
+
+//CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlal  V0.2s, v1.2h, v2.h[-1]
+//CHECK-NEXT:                          ^
+//CHECK-NEXT: error: vector lane must be an integer in range [0, 7].
+//CHECK-NEXT: fmlsl2  V0.2s, v1.2h, v2.h[-1]
+//CHECK-NEXT:                           ^

test/MC/AArch64/armv8.2a-fpmul.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,+fullfp16 < %s | FileCheck %s --check-prefix=CHECK
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR-NOV82
+
+//------------------------------------------------------------------------------
+// ARMV8.4-A Floating Point Multiplication
+//------------------------------------------------------------------------------
+
+FMLAL  V0.2S, V1.2H, V2.2H
+FMLSL  V0.2S, V1.2H, V2.2H
+FMLAL  V0.4S, V1.4H, V2.4H
+FMLSL  V0.4S, V1.4H, V2.4H
+FMLAL2  V0.2S, V1.2H, V2.2H
+FMLSL2  V0.2S, V1.2H, V2.2H
+FMLAL2  V0.4S, V1.4H, V2.4H
+FMLSL2  V0.4S, V1.4H, V2.4H
+
+//CHECK:  fmlal v0.2s, v1.2h, v2.2h     // encoding: [0x20,0xec,0x22,0x0e]
+//CHECK:  fmlsl v0.2s, v1.2h, v2.2h     // encoding: [0x20,0xec,0xa2,0x0e]
+//CHECK:  fmlal v0.4s, v1.4h, v2.4h     // encoding: [0x20,0xec,0x22,0x4e]
+//CHECK:  fmlsl v0.4s, v1.4h, v2.4h     // encoding: [0x20,0xec,0xa2,0x4e]
+//CHECK:  fmlal2  v0.2s, v1.2h, v2.2h     // encoding: [0x20,0xcc,0x22,0x2e]
+//CHECK:  fmlsl2  v0.2s, v1.2h, v2.2h     // encoding: [0x20,0xcc,0xa2,0x2e]
+//CHECK:  fmlal2  v0.4s, v1.4h, v2.4h     // encoding: [0x20,0xcc,0x22,0x6e]
+//CHECK:  fmlsl2  v0.4s, v1.4h, v2.4h     // encoding: [0x20,0xcc,0xa2,0x6e]
+
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+
+# Checks with the maximum index value 7:
+fmlal  V0.2s, v1.2h, v2.h[7]
+fmlsl  V0.2s, v1.2h, v2.h[7]
+fmlal  V0.4s, v1.4h, v2.h[7]
+fmlsl  V0.4s, v1.4h, v2.h[7]
+fmlal2  V0.2s, v1.2h, v2.h[7]
+fmlsl2  V0.2s, v1.2h, v2.h[7]
+fmlal2  V0.4s, v1.4h, v2.h[7]
+fmlsl2  V0.4s, v1.4h, v2.h[7]
+
+# Some more checks with a different index bit pattern to catch
+# incorrect permutations of the index (decimal 7 is 0b111):
+fmlal  V0.2s, v1.2h, v2.h[5]
+fmlsl  V0.2s, v1.2h, v2.h[5]
+fmlal  V0.4s, v1.4h, v2.h[5]
+fmlsl  V0.4s, v1.4h, v2.h[5]
+fmlal2  V0.2s, v1.2h, v2.h[5]
+fmlsl2  V0.2s, v1.2h, v2.h[5]
+fmlal2  V0.4s, v1.4h, v2.h[5]
+fmlsl2  V0.4s, v1.4h, v2.h[5]
+
+//CHECK: fmlal v0.2s, v1.2h, v2.h[7]   // encoding: [0x20,0x08,0xb2,0x0f]
+//CHECK: fmlsl v0.2s, v1.2h, v2.h[7]   // encoding: [0x20,0x48,0xb2,0x0f]
+//CHECK: fmlal v0.4s, v1.4h, v2.h[7]   // encoding: [0x20,0x08,0xb2,0x4f]
+//CHECK: fmlsl v0.4s, v1.4h, v2.h[7]   // encoding: [0x20,0x48,0xb2,0x4f]
+//CHECK: fmlal2  v0.2s, v1.2h, v2.h[7]   // encoding: [0x20,0x88,0xb2,0x2f]
+//CHECK: fmlsl2  v0.2s, v1.2h, v2.h[7]   // encoding: [0x20,0xc8,0xb2,0x2f]
+//CHECK: fmlal2  v0.4s, v1.4h, v2.h[7]   // encoding: [0x20,0x88,0xb2,0x6f]
+//CHECK: fmlsl2  v0.4s, v1.4h, v2.h[7]   // encoding: [0x20,0xc8,0xb2,0x6f]
+
+//CHECK:  fmlal v0.2s, v1.2h, v2.h[5]   // encoding: [0x20,0x08,0x92,0x0f]
+//CHECK:  fmlsl v0.2s, v1.2h, v2.h[5]   // encoding: [0x20,0x48,0x92,0x0f]
+//CHECK:  fmlal v0.4s, v1.4h, v2.h[5]   // encoding: [0x20,0x08,0x92,0x4f]
+//CHECK:  fmlsl v0.4s, v1.4h, v2.h[5]   // encoding: [0x20,0x48,0x92,0x4f]
+//CHECK:  fmlal2  v0.2s, v1.2h, v2.h[5]   // encoding: [0x20,0x88,0x92,0x2f]
+//CHECK:  fmlsl2  v0.2s, v1.2h, v2.h[5]   // encoding: [0x20,0xc8,0x92,0x2f]
+//CHECK:  fmlal2  v0.4s, v1.4h, v2.h[5]   // encoding: [0x20,0x88,0x92,0x6f]
+//CHECK:  fmlsl2  v0.4s, v1.4h, v2.h[5]   // encoding: [0x20,0xc8,0x92,0x6f]
+
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+//CHECK-ERROR: error: instruction requires: fullfp16
+
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a
+//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a

test/MC/ARM/armv8.2a-fpmul-error.s

+// RUN: not llvm-mc -triple arm -mattr=+v8.2a,+fullfp16,+neon -show-encoding < %s 2>&1 | FileCheck %s  --check-prefix=CHECK-ERROR
+
+VFMAL.F16 D0, S1, S2[2]
+vfmsl.f16 d0, s1, s2[2]
+vfmsl.f16 d0, s1, s2[-1]
+vfmal.f16 q0, d1, d2[4]
+VFMSL.F16 Q0, D1, D2[4]
+vfmal.f16 q0, d1, d2[-1]
+
+//CHECK-ERROR:      error: invalid operand for instruction
+//CHECK-ERROR-NEXT: VFMAL.F16 D0, S1, S2[2]
+//CHECK-ERROR-NEXT:                     ^
+//CHECK-ERROR-NEXT: error: invalid operand for instruction
+//CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[2]
+//CHECK-ERROR-NEXT:                     ^
+//CHECK-ERROR-NEXT: error: invalid operand for instruction
+//CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[-1]
+//CHECK-ERROR-NEXT:                     ^
+//CHECK-ERROR-NEXT: error: invalid operand for instruction
+//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[4]
+//CHECK-ERROR-NEXT:                     ^
+//CHECK-ERROR-NEXT: error: invalid operand for instruction
+//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D2[4]
+//CHECK-ERROR-NEXT:                     ^
+//CHECK-ERROR-NEXT: error: invalid operand for instruction
+//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[-1]
+//CHECK-ERROR-NEXT:                     ^

test/MC/ARM/armv8.2a-fpmul.s

+// RUN: llvm-mc -triple arm -mattr=+v8.2a,+fullfp16,+neon -show-encoding < %s | FileCheck %s  --check-prefix=CHECK
+// RUN: llvm-mc -triple thumb -mattr=+v8.2a,+fullfp16,+neon -show-encoding < %s | FileCheck %s  --check-prefix=CHECK-T32
+
+// RUN: not llvm-mc -triple arm -mattr=-v8.2a,+fullfp16,+neon -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-84 < %t %s
+
+// RUN: not llvm-mc -triple arm -mattr=+v8.2a,-fullfp16,+neon -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-FP16 < %t %s
+
+// RUN: not llvm-mc -triple arm -mattr=+v8.2a,+fullfp16,-neon -show-encoding < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-NEON < %t %s
+
+VFMAL.F16 D0, S1, S2
+vfmsl.f16 d0, s1, s2
+vfmal.f16 q0, d1, d2
+VFMSL.F16 Q0, D1, D2
+
+VFMAL.F16 D0, S1, S2[1]
+vfmsl.f16 d0, s1, s2[1]
+vfmal.f16 q0, d1, d2[3]
+VFMSL.F16 Q0, D1, D2[3]
+
+//CHECK: vfmal.f16 d0, s1, s2      @ encoding: [0x91,0x08,0x20,0xfc]
+//CHECK: vfmsl.f16 d0, s1, s2      @ encoding: [0x91,0x08,0xa0,0xfc]
+//CHECK: vfmal.f16 q0, d1, d2      @ encoding: [0x52,0x08,0x21,0xfc]
+//CHECK: vfmsl.f16 q0, d1, d2      @ encoding: [0x52,0x08,0xa1,0xfc]
+
+//CHECK:  vfmal.f16 d0, s1, s2[1]   @ encoding: [0x99,0x08,0x00,0xfe]
+//CHECK:  vfmsl.f16 d0, s1, s2[1]   @ encoding: [0x99,0x08,0x10,0xfe]
+//CHECK:  vfmal.f16 q0, d1, d2[3]   @ encoding: [0x7a,0x08,0x01,0xfe]
+//CHECK:  vfmsl.f16 q0, d1, d2[3]   @ encoding: [0x7a,0x08,0x11,0xfe]
+
+//CHECK-T32:  vfmal.f16 d0, s1, s2      @ encoding: [0x20,0xfc,0x91,0x08]
+//CHECK-T32:  vfmsl.f16 d0, s1, s2      @ encoding: [0xa0,0xfc,0x91,0x08]
+//CHECK-T32:  vfmal.f16 q0, d1, d2      @ encoding: [0x21,0xfc,0x52,0x08]
+//CHECK-T32:  vfmsl.f16 q0, d1, d2      @ encoding: [0xa1,0xfc,0x52,0x08]
+
+//CHECK-T32:  vfmal.f16 d0, s1, s2[1]   @ encoding: [0x00,0xfe,0x99,0x08]
+//CHECK-T32:  vfmsl.f16 d0, s1, s2[1]   @ encoding: [0x10,0xfe,0x99,0x08]
+//CHECK-T32:  vfmal.f16 q0, d1, d2[3]   @ encoding: [0x01,0xfe,0x7a,0x08]
+//CHECK-T32:  vfmsl.f16 q0, d1, d2[3]   @ encoding: [0x11,0xfe,0x7a,0x08]
+
+//CHECK-NO-84: error: instruction requires: armv8.2a
+//CHECK-NO-84: error: instruction requires: armv8.2a
+//CHECK-NO-84: error: instruction requires: armv8.2a
+//CHECK-NO-84: error: instruction requires: armv8.2a
+//CHECK-NO-84: error: instruction requires: armv8.2a
+//CHECK-NO-84: error: instruction requires: armv8.2a
+//CHECK-NO-84: error: instruction requires: armv8.2a
+//CHECK-NO-84: error: instruction requires: armv8.2a
+
+//CHECK-NO-FP16: instruction requires: full half-float
+//CHECK-NO-FP16: instruction requires: full half-float
+//CHECK-NO-FP16: instruction requires: full half-float
+//CHECK-NO-FP16: instruction requires: full half-float
+//CHECK-NO-FP16: instruction requires: full half-float
+//CHECK-NO-FP16: instruction requires: full half-float
+//CHECK-NO-FP16: instruction requires: full half-float
+//CHECK-NO-FP16: instruction requires: full half-float
+
+//CHECK-NO-NEON: instruction requires: NEON
+//CHECK-NO-NEON: instruction requires: NEON
+//CHECK-NO-NEON: instruction requires: NEON
+//CHECK-NO-NEON: instruction requires: NEON
+//CHECK-NO-NEON: instruction requires: NEON
+//CHECK-NO-NEON: instruction requires: NEON
+//CHECK-NO-NEON: instruction requires: NEON
+//CHECK-NO-NEON: instruction requires: NEON

test/MC/Disassembler/AArch64/armv8.2a-fpmul.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 --disassemble < %s | FileCheck %s
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.2a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a,-fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+[0x20,0xec,0x22,0x0e]
+[0x20,0xec,0xa2,0x0e]
+[0x20,0xec,0x22,0x4e]
+[0x20,0xec,0xa2,0x4e]
+[0x20,0xcc,0x22,0x2e]
+[0x20,0xcc,0xa2,0x2e]
+[0x20,0xcc,0x22,0x6e]
+[0x20,0xcc,0xa2,0x6e]
+
+#indexed variants:
+
+[0x20,0x08,0xb2,0x0f]
+[0x20,0x48,0xb2,0x0f]
+[0x20,0x08,0xb2,0x4f]
+[0x20,0x48,0xb2,0x4f]
+[0x20,0x88,0xb2,0x2f]
+[0x20,0xc8,0xb2,0x2f]
+[0x20,0x88,0xb2,0x6f]
+[0x20,0xc8,0xb2,0x6f]
+
+[0x20,0x08,0x92,0x0f]
+[0x20,0x48,0x92,0x0f]
+[0x20,0x08,0x92,0x4f]
+[0x20,0x48,0x92,0x4f]
+[0x20,0x88,0x92,0x2f]
+[0x20,0xc8,0x92,0x2f]
+[0x20,0x88,0x92,0x6f]
+[0x20,0xc8,0x92,0x6f]
+
+#CHECK:  fmlal v0.2s, v1.2h, v2.2h
+#CHECK:  fmlsl v0.2s, v1.2h, v2.2h
+#CHECK:  fmlal v0.4s, v1.4h, v2.4h
+#CHECK:  fmlsl v0.4s, v1.4h, v2.4h
+#CHECK:  fmlal2  v0.2s, v1.2h, v2.2h
+#CHECK:  fmlsl2  v0.2s, v1.2h, v2.2h
+#CHECK:  fmlal2  v0.4s, v1.4h, v2.4h
+#CHECK:  fmlsl2  v0.4s, v1.4h, v2.4h
+
+#CHECK:  fmlal v0.2s, v1.2h, v2.h[7]
+#CHECK:  fmlsl v0.2s, v1.2h, v2.h[7]
+#CHECK:  fmlal v0.4s, v1.4h, v2.h[7]
+#CHECK:  fmlsl v0.4s, v1.4h, v2.h[7]
+#CHECK:  fmlal2  v0.2s, v1.2h, v2.h[7]
+#CHECK:  fmlsl2  v0.2s, v1.2h, v2.h[7]
+#CHECK:  fmlal2  v0.4s, v1.4h, v2.h[7]
+#CHECK:  fmlsl2  v0.4s, v1.4h, v2.h[7]
+
+#CHECK:  fmlal v0.2s, v1.2h, v2.h[5]
+#CHECK:  fmlsl v0.2s, v1.2h, v2.h[5]
+#CHECK:  fmlal v0.4s, v1.4h, v2.h[5]
+#CHECK:  fmlsl v0.4s, v1.4h, v2.h[5]
+#CHECK:  fmlal2  v0.2s, v1.2h, v2.h[5]
+#CHECK:  fmlsl2  v0.2s, v1.2h, v2.h[5]
+#CHECK:  fmlal2  v0.4s, v1.4h, v2.h[5]
+#CHECK:  fmlsl2  v0.4s, v1.4h, v2.h[5]
+
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xec,0x22,0x0e]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xec,0xa2,0x0e]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xec,0x22,0x4e]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xec,0xa2,0x4e]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xcc,0x22,0x2e]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xcc,0xa2,0x2e]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xcc,0x22,0x6e]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xcc,0xa2,0x6e]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x08,0xb2,0x0f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x48,0xb2,0x0f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x08,0xb2,0x4f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x48,0xb2,0x4f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x88,0xb2,0x2f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xc8,0xb2,0x2f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x88,0xb2,0x6f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xc8,0xb2,0x6f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x08,0x92,0x0f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x48,0x92,0x0f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x08,0x92,0x4f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x48,0x92,0x4f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x88,0x92,0x2f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xc8,0x92,0x2f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0x88,0x92,0x6f]
+#CHECK-ERROR:  ^
+#CHECK-ERROR: warning: invalid instruction encoding
+#CHECK-ERROR: [0x20,0xc8,0x92,0x6f]
+#CHECK-ERROR:  ^

test/MC/Disassembler/ARM/armv8.2a-fpmul-a32.txt

+# RUN: llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+fullfp16,+neon --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple arm-none-linux-gnu -mattr=-v8.2a,+fullfp16,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-82
+# RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,-fullfp16,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
+# RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+fullfp16,-neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
+
+[0x91,0x08,0x20,0xfc]
+[0x91,0x08,0xa0,0xfc]
+[0x52,0x08,0x21,0xfc]
+[0x52,0x08,0xa1,0xfc]
+[0x99,0x08,0x00,0xfe]
+[0x99,0x08,0x10,0xfe]
+[0x7a,0x08,0x01,0xfe]
+[0x7a,0x08,0x11,0xfe]
+
+#CHECK: vfmal.f16 d0, s1, s2
+#CHECK: vfmsl.f16 d0, s1, s2
+#CHECK: vfmal.f16 q0, d1, d2
+#CHECK: vfmsl.f16 q0, d1, d2
+#CHECK: vfmal.f16 d0, s1, s2[1]
+#CHECK: vfmsl.f16 d0, s1, s2[1]
+#CHECK: vfmal.f16 q0, d1, d2[3]
+#CHECK: vfmsl.f16 q0, d1, d2[3]
+
+#CHECK-NO-82:  stc2  p8, c0, [r0], #-580
+#CHECK-NO-82:  stc2  p8, c0, [r0], #580
+#CHECK-NO-82:  stc2  p8, c0, [r1], #-328
+#CHECK-NO-82:  stc2  p8, c0, [r1], #328
+#CHECK-NO-82:  mcr2  p8, #0, r0, c0, c9, #4
+#CHECK-NO-82:  mrc2  p8, #0, r0, c0, c9, #4
+#CHECK-NO-82:  mcr2  p8, #0, r0, c1, c10, #3
+#CHECK-NO-82:  mrc2  p8, #0, r0, c1, c10, #3
+
+#CHECK-INVALID:  warning: invalid instruction encoding
+#CHECK-INVALID: [0x91,0x08,0x20,0xfc]
+#CHECK-INVALID:  ^
+#CHECK-INVALID:  warning: invalid instruction encoding
+#CHECK-INVALID: [0x91,0x08,0xa0,0xfc]
+#CHECK-INVALID:  ^
+#CHECK-INVALID:  warning: invalid instruction encoding
+#CHECK-INVALID: [0x52,0x08,0x21,0xfc]
+#CHECK-INVALID:  ^
+#CHECK-INVALID:  warning: invalid instruction encoding
+#CHECK-INVALID: [0x52,0x08,0xa1,0xfc]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x99,0x08,0x00,0xfe]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x99,0x08,0x10,0xfe]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x7a,0x08,0x01,0xfe]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x7a,0x08,0x11,0xfe]
+#CHECK-INVALID:  ^

test/MC/Disassembler/ARM/armv8.2a-fpmul-t32.txt

+# RUN: llvm-mc -triple thumb -mattr=+v8.2a,+fullfp16,+neon --disassemble < %s | FileCheck %s
+# RUN: not llvm-mc -triple thumb -mattr=-v8.2a,+fullfp16,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
+# RUN: not llvm-mc -triple thumb -mattr=+v8.2a,-fullfp16,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
+# RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+fullfp16,-neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
+
+[0x20,0xfc,0x91,0x08]
+[0xa0,0xfc,0x91,0x08]
+[0x21,0xfc,0x52,0x08]
+[0xa1,0xfc,0x52,0x08]
+[0x00,0xfe,0x99,0x08]
+[0x10,0xfe,0x99,0x08]
+[0x01,0xfe,0x7a,0x08]
+[0x11,0xfe,0x7a,0x08]
+
+#CHECK: vfmal.f16 d0, s1, s2
+#CHECK: vfmsl.f16 d0, s1, s2
+#CHECK: vfmal.f16 q0, d1, d2
+#CHECK: vfmsl.f16 q0, d1, d2
+#CHECK: vfmal.f16 d0, s1, s2[1]
+#CHECK: vfmsl.f16 d0, s1, s2[1]
+#CHECK: vfmal.f16 q0, d1, d2[3]
+#CHECK: vfmsl.f16 q0, d1, d2[3]
+
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x20,0xfc,0x91,0x08]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0xa0,0xfc,0x91,0x08]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x21,0xfc,0x52,0x08]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0xa1,0xfc,0x52,0x08]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x00,0xfe,0x99,0x08]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x10,0xfe,0x99,0x08]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x01,0xfe,0x7a,0x08]
+#CHECK-INVALID:  ^
+#CHECK-INVALID: warning: invalid instruction encoding
+#CHECK-INVALID: [0x11,0xfe,0x7a,0x08]
+#CHECK-INVALID:  ^