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[X86] Improved sched models for X86 BSWAP* instructions.
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Authored by avt77 on Jul 18 2018, 5:34 AM.

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Summary

This patch improves sched models for BSWAP* X86 instrs removing unnecessary redefinitions of instr infos. This patch is based on results of D48222.

Diff Detail

Repository
rL LLVM

Event Timeline

avt77 created this revision.Jul 18 2018, 5:34 AM
lebedev.ri added inline comments.Jul 18 2018, 5:53 AM
lib/Target/X86/X86Schedule.td
120–121 ↗(On Diff #156054)

// Byte Order (Endiannes) Swap

RKSimon added inline comments.Jul 18 2018, 7:36 AM
lib/Target/X86/X86SchedHaswell.td
123 ↗(On Diff #156054)

Really minor, but please can you be consistent with where you're adding these to the sched lists?

avt77 updated this revision to Diff 156227.Jul 19 2018, 3:41 AM

Comments from Simon and Roman were resolved.

lebedev.ri accepted this revision.Jul 19 2018, 3:49 AM

I don't think you wanted to include the utils/TableGen/CodeGenSchedule.* changes here.
Other than that, no further comments, looks ok to me, but probably wait for @RKSimon.

This revision is now accepted and ready to land.Jul 19 2018, 3:49 AM
RKSimon requested changes to this revision.Jul 19 2018, 4:21 AM

Drop the tablegen CodeGenSchedule changes

This revision now requires changes to proceed.Jul 19 2018, 4:21 AM
avt77 added a comment.Jul 19 2018, 5:24 AM

Drop the tablegen CodeGenSchedule changes

Could you LGTM D48222? It's really boring to drop this part every time when...

avt77 updated this revision to Diff 156245.Jul 19 2018, 5:29 AM

I removed the changes from D48222.

RKSimon accepted this revision.Jul 19 2018, 5:46 AM

LGTM - cheers

This revision is now accepted and ready to land.Jul 19 2018, 5:46 AM
This revision was automatically updated to reflect the committed changes.