[ARM] Add new feature to enable optimizing the VFP registers

[evandro]

Summary

Enable the optimization of operations on DPR and SPR via a feature instead of checking the target.

[sbaranga]

If this is no longer only used by Cortex-A15, I think the regression tests need to be updated to use the new feature instead of the passing the cpu.

Otherwise, I have no objections to turning this on for other cores if that's beneficial.

llvm/lib/Target/ARM/ARM.td

200

I think the description/name is somewhat confusing.

This enables using vdup instructions to move from the vfp execution domain to neon, which on some cores (at least Cortex-A15) is faster.

[evandro]

Update the test case to use the feature attribute.

llvm/lib/Target/ARM/ARM.td

200

What do you suggest?

[sbaranga]

llvm/lib/Target/ARM/ARM.td

200

Something like FeatureUseVDUPForFPToNEON? Ideally something shorter, but that's the best that I can come up with at the moment.

The comment should say something along the lines that it's profitable for the target to use a VDUP instruction when performing a transition from the VFP to NEON execution domain.

[evandro]

llvm/lib/Target/ARM/ARM.td

200

How about FeatureSplatVFPToNeon?

[sbaranga]

llvm/lib/Target/ARM/ARM.td

200

Yes, that works as well.

[sbaranga]

LGTM

llvm/lib/Target/ARM/A15SDOptimizer.cpp

 
 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
   if (skipFunction(Fn.getFunction()))
     return false;
 
   const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
   // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
   // enabled when NEON is available.
-  if (!(STI.isCortexA15() && STI.hasNEON()))
+  if (!(STI.useSplatVFPToNeon() && STI.hasNEON()))
     return false;
+
   TII = STI.getInstrInfo();
   TRI = STI.getRegisterInfo();
   MRI = &Fn.getRegInfo();
   bool Modified = false;
 
   LLVM_DEBUG(dbgs() << "Running on function " << Fn.getName() << "\n");
 
   DeadInstr.clear();

llvm/lib/Target/ARM/ARM.td

def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
                                               "SlowLoadDSubregister", "true",
                                               "Loading into D subregs is slow">;
 
 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
                                              "DontWidenVMOVS", "true",
                                              "Don't widen VMOVS to VMOVD">;
 
+// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
+// VFP register widths.
+def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",
+                                             "SplatVFPToNeon", "true",
+                                             "Splat register from VFP to NEON",
+                                             [FeatureDontWidenVMOVS]>;
+
 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
                                              "ExpandMLx", "true",
                                              "Expand VFP/NEON MLA/MLS instructions">;
 
 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
                                              "true", "Has VMLx hazards">;
def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
                                                          FeatureVMLxForwarding,
                                                          FeatureVFP4,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureVirtualization,
                                                          FeatureMP]>;
 
 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
                                                          FeatureDontWidenVMOVS,
+                                                         FeatureSplatVFPToNeon,
                                                          FeatureHasRetAddrStack,
                                                          FeatureMuxedUnits,
                                                          FeatureTrustZone,
                                                          FeatureVFP4,
                                                          FeatureMP,
                                                          FeatureCheckVLDnAlign,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureVirtualization]>;
def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
                                                          FeatureAvoidMOVsShOp,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureCrypto,
                                                          FeatureUseMISched,
                                                          FeatureZCZeroing,
                                                          FeatureNoPostRASched]>;
 
 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
+                                                         FeatureSplatVFPToNeon,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynosM1,
+                                                         FeatureSplatVFPToNeon,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynosM1,
+                                                         FeatureSplatVFPToNeon,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"exynos-m4",                           [ARMv8a, ProcExynosM1,
+                                                         FeatureSplatVFPToNeon,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,

llvm/lib/Target/ARM/ARMSubtarget.h

protected:
   bool SlowOddRegister = false;
 
   /// If true, loading into a D subregister will be penalized.
   bool SlowLoadDSubregister = false;
 
   /// If true, the AGU and NEON/FPU units are multiplexed.
   bool HasMuxedUnits = false;
 
-  /// If true, VMOVS will never be widened to VMOVD
+  /// If true, VMOVS will never be widened to VMOVD.
   bool DontWidenVMOVS = false;
 
+  /// If true, splat a register between VFP and NEON instructions.
+  bool SplatVFPToNeon = false;
+
   /// If true, run the MLx expansion pass.
   bool ExpandMLx = false;
 
   /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
   bool HasVMLxHazards = false;
 
   // If true, read thread pointer from coprocessor register.
   bool ReadTPHard = false;
public:
   bool preferVMOVSR() const { return PreferVMOVSR; }
   bool preferISHSTBarriers() const { return PreferISHST; }
   bool expandMLx() const { return ExpandMLx; }
   bool hasVMLxHazards() const { return HasVMLxHazards; }
   bool hasSlowOddRegister() const { return SlowOddRegister; }
   bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
   bool hasMuxedUnits() const { return HasMuxedUnits; }
   bool dontWidenVMOVS() const { return DontWidenVMOVS; }
+  bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
   bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
   bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
   bool nonpipelinedVFP() const { return NonpipelinedVFP; }
   bool prefers32BitThumb() const { return Pref32BitThumb; }
   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
   bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; }
   bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
   bool hasRetAddrStack() const { return HasRetAddrStack; }

llvm/test/CodeGen/ARM/a15-SD-dep.ll

-; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s  | FileCheck -check-prefix=CHECK-DISABLED %s
-; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-ENABLED %s
+; RUN: llc -O1 -mattr=+splat-vfp-neon -mtriple=armv7-linux-gnueabi -verify-machineinstrs -disable-a15-sd-optimization < %s | FileCheck -check-prefixes=CHECK,CHECK-DISABLED %s
+; RUN: llc -O1 -mattr=-splat-vfp-neon -mtriple=armv7-linux-gnueabi -verify-machineinstrs                              < %s | FileCheck -check-prefixes=CHECK,CHECK-DISABLED %s
+; RUN: llc -O1 -mattr=+splat-vfp-neon -mtriple=armv7-linux-gnueabi -verify-machineinstrs                              < %s | FileCheck -check-prefixes=CHECK,CHECK-ENABLED  %s
 
-; CHECK-ENABLED-LABEL: t1:
-; CHECK-DISABLED-LABEL: t1:
+; CHECK-LABEL: t1:
 define <2 x float> @t1(float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
   ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
   %i1 = insertelement <2 x float> undef, float %f, i32 1
   %i2 = fadd <2 x float> %i1, %i1
   ret <2 x float> %i2
 }
 
-; CHECK-ENABLED-LABEL: t2:
-; CHECK-DISABLED-LABEL: t2:
+; CHECK-LABEL: t2:
 define <4 x float> @t2(float %g, float %f) {
   ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0]
   ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
   %i1 = insertelement <4 x float> undef, float %f, i32 1
   %i2 = fadd <4 x float> %i1, %i1
   ret <4 x float> %i2
 }
 
-; CHECK-ENABLED-LABEL: t3:
-; CHECK-DISABLED-LABEL: t3:
+; CHECK-LABEL: t3:
 define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] 
   ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
   %i1 = insertelement <2 x float> undef, float %f, i32 1
   %i2 = fadd <2 x float> %i1, %i1
   ret <2 x float> %i2
 }
 
-; CHECK-ENABLED-LABEL: t4:
-; CHECK-DISABLED-LABEL: t4:
+; CHECK-LABEL: t4:
 define <2 x float> @t4(float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
   ; CHECK-DISABLED-NOT: vdup
   %i1 = insertelement <2 x float> undef, float %f, i32 1
   br label %b
 
   ; Block %b has an S-reg as live-in.
 b:
   %i2 = fadd <2 x float> %i1, %i1
   ret <2 x float> %i2
 }
 
-; CHECK-ENABLED-LABEL: t5:
-; CHECK-DISABLED-LABEL: t5:
+; CHECK-LABEL: t5:
 define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
   ; CHECK-ENABLED: vadd.f32
   ; CHECK-ENABLED-NEXT: bx lr
   ; CHECK-DISABLED-NOT: vdup
   %i1 = insertelement <4 x float> %q, float %f, i32 1
   %i2 = fadd <4 x float> %i1, %i1
   ret <4 x float> %i2
 }
 
 ; Test that DPair can be successfully passed as QPR.
-; CHECK-ENABLED-LABEL: test_DPair1:
-; CHECK-DISABLED-LABEL: test_DPair1:
+; CHECK-LABEL: test_DPair1:
 define void @test_DPair1(i32 %vsout, i8* nocapture %out, float %x, float %y) {
 entry:
   %0 = insertelement <4 x float> undef, float %x, i32 1
   %1 = insertelement <4 x float> %0, float %y, i32 0
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[1]
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[1]
sw.bb6:                                           ; preds = %sw.bb, %entry
   %conv = fptoui float %3 to i8
   store i8 %conv, i8* %out, align 1
   ret void
 
 sw.epilog:                                        ; preds = %entry
   ret void
 }
 
-; CHECK-ENABLED-LABEL: test_DPair2:
-; CHECK-DISABLED-LABEL: test_DPair2:
+; CHECK-LABEL: test_DPair2:
 define void @test_DPair2(i32 %vsout, i8* nocapture %out, float %x) {
 entry:
   %0 = insertelement <4 x float> undef, float %x, i32 0
   ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d{{[0-9]*}}[0]
   ; CHECK-DISABLED-NOT: vdup
   switch i32 %vsout, label %sw.epilog [
     i32 1, label %sw.bb
     i32 0, label %sw.bb1