[WebAssembly] Support for atomic.wait / atomic.wake instructions

[aheejin]

Summary

This adds support for [[ https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md#wait | atomic.wait ]] / [[ https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md#wake | atomic.wake ]] instructions in the wasm thread proposal.

[aheejin]

• Type fix

[aheejin]

Should've included all sorts of other memargs.

[aheejin]

• Add support for various memargs

[aheejin]

clang-format

[aheejin]

Does atomic.wake possibly load the given address? It is marked as such for now to be safe. Would it have any problems, or would it be unnecessary?

[aheejin]

Should make it return true on isAtomic() I guess

[aheejin]

I guess there's no sane way to make MachineMemOperand of wait and wake instructions return true on isAtomic() anyway. First, LLVM currently does not seem to provide atomic memory intrinsic other than few predefined target-independent intrinsics, and there's no code that depends on MachineMemOperand::isAtomic() in the backend passes anyway.

[dschuff]

Note that in JS, atomics.wake is now atomics.notify (https://github.com/tc39/ecma262/pull/1220). So we should use the new terminology for new and internal stuff. Since there's no legacy yet (except maybe in Binaryen's and WABT's text parser) hopefully LLVM can just use "notify" everywhere.

I think wake does not load the given address. the list of waiters is outside of the memory and invisible to LLVM, it just happens to share the same index space. So I think hasSideEffects is the right way to model that.

include/llvm/IR/IntrinsicsWebAssembly.td

75

Same signature adjustments as suggested in the clang CL.

[aheejin]

• wake -> notify / etc

[aheejin]

Do you think we should also suggest to change wake to notify in the thread proposal?

include/llvm/IR/IntrinsicsWebAssembly.td

75

I added some comments in that CL, PTAL.

[aheejin]

rebase

[dschuff]

I would imagine that's already on Ben's plate to do sometime, but yes it should be changed to match JS.

include/llvm/IR/IntrinsicsWebAssembly.td

75

Yeah, so this signature would be unchanged then, since there's no signed/unsigned distinction in the IR either.

[aheejin]

Added MOVolatile flags to instructions and added comments

[aheejin]

I added MOVolatile flags to instructions, because, currently LLVM atomic instructions are marked as such. References: 1 2
I also added some comments on why wake is marked as MOLoad. PTAL

[dschuff]

Still looks good 👍

include/llvm/IR/IntrinsicsWebAssembly.td

 
 // WebAssembly EH must maintain the landingpads in the order assigned to them
 // by WasmEHPrepare pass to generate landingpad table in EHStreamer. This is
 // used in order to give them the indices in WasmEHPrepare.
 def int_wasm_landingpad_index: Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>;
 
 // Returns LSDA address of the current function.
 def int_wasm_lsda : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
+
+//===----------------------------------------------------------------------===//
+// Atomic intrinsics
+//===----------------------------------------------------------------------===//
+
+// wait / wake
+def int_wasm_atomic_wait_i32 :
+  Intrinsic<[llvm_i32_ty],
+            [LLVMPointerType<llvm_i32_ty>, llvm_i32_ty, llvm_i64_ty],
+            [IntrInaccessibleMemOrArgMemOnly, ReadOnly<0>, NoCapture<0>,
+             IntrHasSideEffects]>;
+def int_wasm_atomic_wait_i64 :
+  Intrinsic<[llvm_i32_ty],
+            [LLVMPointerType<llvm_i64_ty>, llvm_i64_ty, llvm_i64_ty],
+            [IntrInaccessibleMemOrArgMemOnly, ReadOnly<0>, NoCapture<0>,
+             IntrHasSideEffects]>;
+def int_wasm_atomic_wake :
+  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty],
+            [IntrInaccessibleMemOnly, NoCapture<0>, IntrHasSideEffects]>;
+
 }

lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

defm : BinRMWTruncExtPattern<
   atomic_load_xor_8, atomic_load_xor_16, atomic_load_xor_32, atomic_load_xor_64,
   ATOMIC_RMW8_U_XOR_I32, ATOMIC_RMW16_U_XOR_I32,
   ATOMIC_RMW8_U_XOR_I64, ATOMIC_RMW16_U_XOR_I64, ATOMIC_RMW32_U_XOR_I64>;
 defm : BinRMWTruncExtPattern<
   atomic_swap_8, atomic_swap_16, atomic_swap_32, atomic_swap_64,
   ATOMIC_RMW8_U_XCHG_I32, ATOMIC_RMW16_U_XCHG_I32,
   ATOMIC_RMW8_U_XCHG_I64, ATOMIC_RMW16_U_XCHG_I64, ATOMIC_RMW32_U_XCHG_I64>;
 } // Predicates = [HasAtomics]
+
+//===----------------------------------------------------------------------===//
+// Atomic wait / wake
+//===----------------------------------------------------------------------===//
+
+let Defs = [ARGUMENTS] in {
+
+let Predicates = [HasAtomics] in {
+let hasSideEffects = 1 in {
+defm ATOMIC_WAKE :
+  I<(outs I64:$dst), (ins I32:$addr, I64:$wake_count), (outs), (ins),
+    [(set I64:$dst, (int_wasm_atomic_wake I32:$addr, I64:$wake_count))],
+    "atomic.wake \t$dst, $addr, $wake_count", "atomic.wake", 0xfe00>;
+let mayLoad = 1 in {
+defm ATOMIC_WAIT_I32 :
+  I<(outs I32:$dst), (ins I32:$addr, I32:$exp, I64:$timeout), (outs), (ins),
+    [(set I32:$dst,
+          (int_wasm_atomic_wait_i32 I32:$addr, I32:$exp, I64:$timeout))],
+    "i32.atomic.wait \t$dst, $addr, $exp, $timeout", "i32.atomic.wait", 0xfe01>;
+defm ATOMIC_WAIT_I64 :
+  I<(outs I32:$dst), (ins I32:$addr, I64:$exp, I64:$timeout), (outs), (ins),
+    [(set I32:$dst,
+          (int_wasm_atomic_wait_i64 I32:$addr, I64:$exp, I64:$timeout))],
+    "i64.atomic.wait \t$dst, $addr, $exp, $timeout", "i64.atomic.wait", 0xfe02>;
+} // mayLoad = 1
+} // hasSideEffects = 1
+} // Predicates = [HasAtomics]
+
+} // Defs = [ARGUMENTS]

test/CodeGen/WebAssembly/atomic-wait-wake.ll

+; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+atomics | FileCheck --match-full-lines %s
+
+; Test atomic wait / wake instructions.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+declare i32 @llvm.wasm.atomic.wait.i32(i32*, i32, i64)
+declare i32 @llvm.wasm.atomic.wait.i64(i64*, i64, i64)
+declare i64 @llvm.wasm.atomic.wake(i8*, i64)
+
+; CHECK-LABEL: test_atomic_wait_i32:
+; CHECK-NEXT: .param i32, i32, i64
+; CHECK-NEXT: .result i32
+; CHECK-NEXT: i32.atomic.wait $push0=, $0, $1, $2
+; CHECK-NEXT: return $pop0
+define i32 @test_atomic_wait_i32(i32* %addr, i32 %exp, i64 %timeout) {
+  %ret = call i32 @llvm.wasm.atomic.wait.i32(i32* %addr, i32 %exp, i64 %timeout)
+  ret i32 %ret
+}
+
+; CHECK-LABEL: test_atomic_wait_i64:
+; CHECK-NEXT: .param i32, i64, i64
+; CHECK-NEXT: .result i32
+; CHECK-NEXT: i64.atomic.wait $push0=, $0, $1, $2
+; CHECK-NEXT: return $pop0
+define i32 @test_atomic_wait_i64(i64* %addr, i64 %exp, i64 %timeout) {
+  %ret = call i32 @llvm.wasm.atomic.wait.i64(i64* %addr, i64 %exp, i64 %timeout)
+  ret i32 %ret
+}
+
+; CHECK-LABEL: test_atomic_wake:
+; CHECK-NEXT: .param i32, i64
+; CHECK-NEXT: .result i64
+; CHECK-NEXT: atomic.wake $push0=, $0, $1
+; CHECK-NEXT: return $pop0
+define i64 @test_atomic_wake(i8* %addr, i64 %wake_count) {
+  %ret = call i64 @llvm.wasm.atomic.wake(i8* %addr, i64 %wake_count)
+  ret i64 %ret
+}