[WebAssembly] Added default stack-only instruction mode for MC.

[aardappel]

Summary

Moved Explicit Locals pass to last.
Made that pass obligatory.
Made it convert from register to stack based instructions, and removed the registers.
Fixes to related code that was expecting register based instructions.
Added the correct testing flag to all tests, depending on what the
format they were expecting so far.
Translated one test to stack format as example: reg-stackify-stack.ll

tested:
llvm-lit -v find test -name WebAssembly
unittests/MC/*

[jgravelle-google]

I kinda like the use of two separate testing mode flags, to avoid needing to refactor every test to the explicit local form right away.

test/CodeGen/WebAssembly/reg-stackify-stack.ll

5

This is probably better merged with reg-stackify.ll, with two RUN commands and a --check-prefix arg passed to FileCheck. See test/CodeGen/WebAssembly/signext-inreg.ll for an example of the prefixing

16

Probably worth the {{$}} on these two returns?

[aheejin]

test/CodeGen/WebAssembly/reg-stackify-stack.ll

16

FileCheck has --match-full-lines option that forces to match full lines, so maybe we can use that instead for new tests..?

[aheejin]

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

130

_S opcodes for atomic stores have been added in D48992.

[aardappel]

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

130

Thanks, rebased against that.

test/CodeGen/WebAssembly/reg-stackify-stack.ll

16

Agreed, that would be simpler, especially since {{$}} is whitespace sensitive, and we have instructions that have whitespace in their output.

[aardappel]

Addressed code review, in particular merged two versions of reg-stackify.ll
into one.

[dschuff]

\o/

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-asm-parser"
 
 namespace {
 
-// We store register types as SimpleValueType to retain SIMD layout
-// information, but must also be able to supply them as the (unnamed)
-// register enum from WebAssemblyRegisterInfo.td/.inc.
-static unsigned MVTToWasmReg(MVT::SimpleValueType Type) {
-  switch(Type) {
-    case MVT::i32: return WebAssembly::I32_0;
-    case MVT::i64: return WebAssembly::I64_0;
-    case MVT::f32: return WebAssembly::F32_0;
-    case MVT::f64: return WebAssembly::F64_0;
-    case MVT::v16i8: return WebAssembly::V128_0;
-    case MVT::v8i16: return WebAssembly::V128_0;
-    case MVT::v4i32: return WebAssembly::V128_0;
-    case MVT::v4f32: return WebAssembly::V128_0;
-    default: return MVT::INVALID_SIMPLE_VALUE_TYPE;
-  }
-}
-
 /// WebAssemblyOperand - Instances of this class represent the operands in a
 /// parsed WASM machine instruction.
 struct WebAssemblyOperand : public MCParsedAsmOperand {
-  enum KindTy { Token, Local, Stack, Integer, Float, Symbol } Kind;
+  enum KindTy { Token, Integer, Float, Symbol } Kind;
 
   SMLoc StartLoc, EndLoc;
 
   struct TokOp {
     StringRef Tok;
   };
 
-  struct RegOp {
-    // This is a (virtual) local or stack register represented as 0..
-    unsigned RegNo;
-    // In most targets, the register number also encodes the type, but for
-    // wasm we have to track that seperately since we have an unbounded
-    // number of registers.
-    // This has the unfortunate side effect that we supply a different value
-    // to the table-gen matcher at different times in the process (when it
-    // calls getReg() or addRegOperands().
-    // TODO: While this works, it feels brittle. and would be nice to clean up.
-    MVT::SimpleValueType Type;
-  };
-
   struct IntOp {
     int64_t Val;
   };
 
   struct FltOp {
     double Val;
   };
 
   struct SymOp {
     const MCExpr *Exp;
   };
 
   union {
     struct TokOp Tok;
-    struct RegOp Reg;
     struct IntOp Int;
     struct FltOp Flt;
     struct SymOp Sym;
   };
 
   WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, TokOp T)
     : Kind(K), StartLoc(Start), EndLoc(End), Tok(T) {}
-  WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, RegOp R)
-    : Kind(K), StartLoc(Start), EndLoc(End), Reg(R) {}
   WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I)
     : Kind(K), StartLoc(Start), EndLoc(End), Int(I) {}
   WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, FltOp F)
     : Kind(K), StartLoc(Start), EndLoc(End), Flt(F) {}
   WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, SymOp S)
     : Kind(K), StartLoc(Start), EndLoc(End), Sym(S) {}
 
   bool isToken() const override { return Kind == Token; }
   bool isImm() const override { return Kind == Integer ||
                                        Kind == Float ||
                                        Kind == Symbol; }
-  bool isReg() const override { return Kind == Local || Kind == Stack; }
   bool isMem() const override { return false; }
+  bool isReg() const override { return false; }
 
   unsigned getReg() const override {
-    assert(isReg());
-    // This is called from the tablegen matcher (MatchInstructionImpl)
-    // where it expects to match the type of register, see RegOp above.
-    return MVTToWasmReg(Reg.Type);
+    llvm_unreachable("Assembly inspects a register operand");
+    return 0;
   }
 
   StringRef getToken() const {
     assert(isToken());
     return Tok.Tok;
   }
 
   SMLoc getStartLoc() const override { return StartLoc; }
   SMLoc getEndLoc() const override { return EndLoc; }
 
-  void addRegOperands(MCInst &Inst, unsigned N) const {
-    assert(N == 1 && "Invalid number of operands!");
-    assert(isReg() && "Not a register operand!");
-    // This is called from the tablegen matcher (MatchInstructionImpl)
-    // where it expects to output the actual register index, see RegOp above.
-    unsigned R = Reg.RegNo;
-    if (Kind == Stack) {
-      // A stack register is represented as a large negative number.
-      // See WebAssemblyRegNumbering::runOnMachineFunction and
-      // getWARegStackId for why this | is needed.
-      R |= INT32_MIN;
-    }
-    Inst.addOperand(MCOperand::createReg(R));
+  void addRegOperands(MCInst &, unsigned) const {
+    // Required by the assembly matcher.
+    llvm_unreachable("Assembly matcher creates register operands");
   }
 
   void addImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     if (Kind == Integer)
       Inst.addOperand(MCOperand::createImm(Int.Val));
     else if (Kind == Float)
       Inst.addOperand(MCOperand::createFPImm(Flt.Val));
     else if (Kind == Symbol)
       Inst.addOperand(MCOperand::createExpr(Sym.Exp));
     else
       llvm_unreachable("Should be immediate or symbol!");
   }
 
   void print(raw_ostream &OS) const override {
     switch (Kind) {
     case Token:
       OS << "Tok:" << Tok.Tok;
       break;
-    case Local:
-      OS << "Loc:" << Reg.RegNo << ":" << static_cast<int>(Reg.Type);
-      break;
-    case Stack:
-      OS << "Stk:" << Reg.RegNo << ":" << static_cast<int>(Reg.Type);
-      break;
     case Integer:
       OS << "Int:" << Int.Val;
       break;
     case Float:
       OS << "Flt:" << Flt.Val;
       break;
     case Symbol:
       OS << "Sym:" << Sym.Exp;
       break;
     }
   }
 };
 
 class WebAssemblyAsmParser final : public MCTargetAsmParser {
   MCAsmParser &Parser;
   MCAsmLexer &Lexer;
-  // These are for the current function being parsed:
-  // These are vectors since register assignments are so far non-sparse.
-  // Replace by map if necessary.
-  std::vector<MVT::SimpleValueType> LocalTypes;
-  std::vector<MVT::SimpleValueType> StackTypes;
   MCSymbol *LastLabel;
 
 public:
   WebAssemblyAsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
                        const MCInstrInfo &mii, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, sti, mii), Parser(Parser),
         Lexer(Parser.getLexer()), LastLabel(nullptr) {
   }
return StringSwitch<MVT::SimpleValueType>(RegType)
         .Case("f64", MVT::f64)
         .Case("i8x16", MVT::v16i8)
         .Case("i16x8", MVT::v8i16)
         .Case("i32x4", MVT::v4i32)
         .Case("f32x4", MVT::v4f32)
         .Default(MVT::INVALID_SIMPLE_VALUE_TYPE);
   }
 
-  MVT::SimpleValueType &GetType(
-      std::vector<MVT::SimpleValueType> &Types, size_t i) {
-    Types.resize(std::max(i + 1, Types.size()), MVT::INVALID_SIMPLE_VALUE_TYPE);
-    return Types[i];
-  }
-
-  bool ParseReg(OperandVector &Operands, StringRef TypePrefix) {
-    if (Lexer.is(AsmToken::Integer)) {
-      auto &Local = Lexer.getTok();
-      // This is a reference to a local, turn it into a virtual register.
-      auto LocalNo = static_cast<unsigned>(Local.getIntVal());
-      Operands.push_back(make_unique<WebAssemblyOperand>(
-                           WebAssemblyOperand::Local, Local.getLoc(),
-                           Local.getEndLoc(),
-                           WebAssemblyOperand::RegOp{LocalNo,
-                               GetType(LocalTypes, LocalNo)}));
-      Parser.Lex();
-    } else if (Lexer.is(AsmToken::Identifier)) {
-      auto &StackRegTok = Lexer.getTok();
-      // These are push/pop/drop pseudo stack registers, which we turn
-      // into virtual registers also. The stackify pass will later turn them
-      // back into implicit stack references if possible.
-      auto StackReg = StackRegTok.getString();
-      auto StackOp = StackReg.take_while([](char c) { return isalpha(c); });
-      auto Reg = StackReg.drop_front(StackOp.size());
-      unsigned long long ParsedRegNo = 0;
-      if (!Reg.empty() && getAsUnsignedInteger(Reg, 10, ParsedRegNo))
-        return Error("Cannot parse stack register index: ", StackRegTok);
-      unsigned RegNo = static_cast<unsigned>(ParsedRegNo);
-      if (StackOp == "push") {
-        // This defines a result, record register type.
-        auto RegType = ParseRegType(TypePrefix);
-        GetType(StackTypes, RegNo) = RegType;
-        Operands.push_back(make_unique<WebAssemblyOperand>(
-                             WebAssemblyOperand::Stack,
-                             StackRegTok.getLoc(),
-                             StackRegTok.getEndLoc(),
-                             WebAssemblyOperand::RegOp{RegNo, RegType}));
-      } else if (StackOp == "pop") {
-        // This uses a previously defined stack value.
-        auto RegType = GetType(StackTypes, RegNo);
-        Operands.push_back(make_unique<WebAssemblyOperand>(
-                             WebAssemblyOperand::Stack,
-                             StackRegTok.getLoc(),
-                             StackRegTok.getEndLoc(),
-                             WebAssemblyOperand::RegOp{RegNo, RegType}));
-      } else if (StackOp == "drop") {
-        // This operand will be dropped, since it is part of an instruction
-        // whose result is void.
-      } else {
-        return Error("Unknown stack register prefix: ", StackRegTok);
-      }
-      Parser.Lex();
-    } else {
-      return Error(
-            "Expected identifier/integer following $, instead got: ",
-            Lexer.getTok());
-    }
-    IsNext(AsmToken::Equal);
-    return false;
-  }
-
   void ParseSingleInteger(bool IsNegative, OperandVector &Operands) {
     auto &Int = Lexer.getTok();
     int64_t Val = Int.getIntVal();
     if (IsNegative) Val = -Val;
     Operands.push_back(make_unique<WebAssemblyOperand>(
                          WebAssemblyOperand::Integer, Int.getLoc(),
                          Int.getEndLoc(), WebAssemblyOperand::IntOp{Val}));
     Parser.Lex();
   }
 
   bool ParseOperandStartingWithInteger(bool IsNegative,
                                        OperandVector &Operands,
-                                       StringRef InstType) {
+                                       StringRef InstName) {
     ParseSingleInteger(IsNegative, Operands);
-    if (Lexer.is(AsmToken::LParen)) {
-      // Parse load/store operands of the form: offset($reg)align
-      auto &LParen = Lexer.getTok();
-      Operands.push_back(
-            make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token,
-                                            LParen.getLoc(),
-                                            LParen.getEndLoc(),
-                                            WebAssemblyOperand::TokOp{
-                                              LParen.getString()}));
-      Parser.Lex();
-      if (Expect(AsmToken::Dollar, "register")) return true;
-      if (ParseReg(Operands, InstType)) return true;
-      auto &RParen = Lexer.getTok();
-      Operands.push_back(
-            make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token,
-                                            RParen.getLoc(),
-                                            RParen.getEndLoc(),
-                                            WebAssemblyOperand::TokOp{
-                                              RParen.getString()}));
-      if (Expect(AsmToken::RParen, ")")) return true;
-      if (Lexer.is(AsmToken::Integer)) {
+    // FIXME: there is probably a cleaner way to do this.
+    auto IsLoadStore = InstName.startswith("load") ||
+                       InstName.startswith("store") ||
+                       InstName.startswith("atomic_load") ||
+                       InstName.startswith("atomic_store");
+    if (IsLoadStore) {
+      // Parse load/store operands of the form: offset align
+      auto &Offset = Lexer.getTok();
+      if (Offset.is(AsmToken::Integer)) {
         ParseSingleInteger(false, Operands);
       } else {
         // Alignment not specified.
         // FIXME: correctly derive a default from the instruction.
+        // We can't just call WebAssembly::GetDefaultP2Align since we don't have
+        // an opcode until after the assembly matcher.
         Operands.push_back(make_unique<WebAssemblyOperand>(
-                             WebAssemblyOperand::Integer, RParen.getLoc(),
-                             RParen.getEndLoc(), WebAssemblyOperand::IntOp{0}));
+                             WebAssemblyOperand::Integer, Offset.getLoc(),
+                             Offset.getEndLoc(), WebAssemblyOperand::IntOp{0}));
       }
     }
     return false;
   }
 
   bool ParseInstruction(ParseInstructionInfo &/*Info*/, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override {
     Operands.push_back(
           make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token, NameLoc,
                                           SMLoc::getFromPointer(
                                             NameLoc.getPointer() + Name.size()),
                                           WebAssemblyOperand::TokOp{
                                             StringRef(NameLoc.getPointer(),
                                                     Name.size())}));
     auto NamePair = Name.split('.');
     // If no '.', there is no type prefix.
     if (NamePair.second.empty()) std::swap(NamePair.first, NamePair.second);
     while (Lexer.isNot(AsmToken::EndOfStatement)) {
       auto &Tok = Lexer.getTok();
       switch (Tok.getKind()) {
-      case AsmToken::Dollar: {
-        Parser.Lex();
-        if (ParseReg(Operands, NamePair.first)) return true;
-        break;
-      }
       case AsmToken::Identifier: {
         auto &Id = Lexer.getTok();
         const MCExpr *Val;
         SMLoc End;
         if (Parser.parsePrimaryExpr(Val, End))
           return Error("Cannot parse symbol: ", Lexer.getTok());
         Operands.push_back(make_unique<WebAssemblyOperand>(
                              WebAssemblyOperand::Symbol, Id.getLoc(),
                              Id.getEndLoc(), WebAssemblyOperand::SymOp{Val}));
         break;
       }
       case AsmToken::Minus:
         Parser.Lex();
         if (Lexer.isNot(AsmToken::Integer))
           return Error("Expected integer instead got: ", Lexer.getTok());
-        if (ParseOperandStartingWithInteger(true, Operands, NamePair.first))
+        if (ParseOperandStartingWithInteger(true, Operands, NamePair.second))
           return true;
         break;
       case AsmToken::Integer:
-        if (ParseOperandStartingWithInteger(false, Operands, NamePair.first))
+        if (ParseOperandStartingWithInteger(false, Operands, NamePair.second))
           return true;
         break;
       case AsmToken::Real: {
         double Val;
         if (Tok.getString().getAsDouble(Val, false))
           return Error("Cannot parse real: ", Tok);
         Operands.push_back(make_unique<WebAssemblyOperand>(
                              WebAssemblyOperand::Float, Tok.getLoc(),
                              Tok.getEndLoc(), WebAssemblyOperand::FltOp{Val}));
         Parser.Lex();
         break;
       }
       default:
         return Error("Unexpected token in operand: ", Tok);
       }
       if (Lexer.isNot(AsmToken::EndOfStatement)) {
         if (Expect(AsmToken::Comma, ",")) return true;
       }
     }
     Parser.Lex();
-    // Call instructions are vararg, but the tablegen matcher doesn't seem to
-    // support that, so for now we strip these extra operands.
-    // This is problematic if these arguments are not simple $pop stack
-    // registers, since e.g. a local register would get lost, so we check for
-    // this. This can be the case when using -disable-wasm-explicit-locals
-    // which currently s2wasm requires.
-    // TODO: Instead, we can move this code to MatchAndEmitInstruction below and
-    // actually generate get_local instructions on the fly.
-    // Or even better, improve the matcher to support vararg?
-    auto IsIndirect = NamePair.second == "call_indirect";
-    if (IsIndirect || NamePair.second == "call") {
-      // Figure out number of fixed operands from the instruction.
-      size_t CallOperands = 1;  // The name token.
-      if (!IsIndirect) CallOperands++;  // The function index.
-      if (!NamePair.first.empty()) CallOperands++;  // The result register.
-      if (Operands.size() > CallOperands) {
-        // Ensure operands we drop are all $pop.
-        for (size_t I = CallOperands; I < Operands.size(); I++) {
-          auto Operand =
-              reinterpret_cast<WebAssemblyOperand *>(Operands[I].get());
-          if (Operand->Kind != WebAssemblyOperand::Stack)
-            Parser.Error(NameLoc,
-              "Call instruction has non-stack arguments, if this code was "
-              "generated with -disable-wasm-explicit-locals please remove it");
-        }
-        // Drop unneeded operands.
-        Operands.resize(CallOperands);
-      }
-    }
     // Block instructions require a signature index, but these are missing in
     // assembly, so we add a dummy one explicitly (since we have no control
     // over signature tables here, we assume these will be regenerated when
     // the wasm module is generated).
     if (NamePair.second == "block" || NamePair.second == "loop") {
       Operands.push_back(make_unique<WebAssemblyOperand>(
                            WebAssemblyOperand::Integer, NameLoc,
                            NameLoc, WebAssemblyOperand::IntOp{-1}));
     }
-    // These don't specify the type, which has to derived from the local index.
-    if (NamePair.second == "get_local" || NamePair.second == "tee_local") {
-      if (Operands.size() >= 3 && Operands[1]->isReg() &&
-          Operands[2]->isImm()) {
-        auto Op1 = reinterpret_cast<WebAssemblyOperand *>(Operands[1].get());
-        auto Op2 = reinterpret_cast<WebAssemblyOperand *>(Operands[2].get());
-        auto Type = GetType(LocalTypes, static_cast<size_t>(Op2->Int.Val));
-        Op1->Reg.Type = Type;
-        GetType(StackTypes, Op1->Reg.RegNo) = Type;
-      }
-    }
     return false;
   }
 
   void onLabelParsed(MCSymbol *Symbol) override {
     LastLabel = Symbol;
   }
 
   bool ParseDirective(AsmToken DirectiveID) override {
     assert(DirectiveID.getKind() == AsmToken::Identifier);
     auto &Out = getStreamer();
     auto &TOut = reinterpret_cast<WebAssemblyTargetStreamer &>(
                    *Out.getTargetStreamer());
     // TODO: we're just parsing the subset of directives we're interested in,
     // and ignoring ones we don't recognise. We should ideally verify
     // all directives here.
     if (DirectiveID.getString() == ".type") {
       // This could be the start of a function, check if followed by
       // "label,@function"
       if (!(IsNext(AsmToken::Identifier) &&
             IsNext(AsmToken::Comma) &&
             IsNext(AsmToken::At) &&
             Lexer.is(AsmToken::Identifier)))
         return Error("Expected label,@type declaration, got: ", Lexer.getTok());
-      if (Lexer.getTok().getString() == "function") {
-        // Track locals from start of function.
-        LocalTypes.clear();
-        StackTypes.clear();
-      }
       Parser.Lex();
       //Out.EmitSymbolAttribute(??, MCSA_ELF_TypeFunction);
     } else if (DirectiveID.getString() == ".param" ||
                DirectiveID.getString() == ".local") {
       // Track the number of locals, needed for correct virtual register
       // assignment elsewhere.
       // Also output a directive to the streamer.
       std::vector<MVT> Params;
       std::vector<MVT> Locals;
       while (Lexer.is(AsmToken::Identifier)) {
         auto RegType = ParseRegType(Lexer.getTok().getString());
         if (RegType == MVT::INVALID_SIMPLE_VALUE_TYPE) return true;
-        LocalTypes.push_back(RegType);
         if (DirectiveID.getString() == ".param") {
           Params.push_back(RegType);
         } else {
           Locals.push_back(RegType);
         }
         Parser.Lex();
         if (!IsNext(AsmToken::Comma)) break;
       }

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

inline unsigned GetDefaultP2Align(unsigned Opcode) {
   case WebAssembly::ATOMIC_LOAD8_U_I32_S:
   case WebAssembly::ATOMIC_LOAD8_U_I64:
   case WebAssembly::ATOMIC_LOAD8_U_I64_S:
   case WebAssembly::STORE8_I32:
   case WebAssembly::STORE8_I32_S:
   case WebAssembly::STORE8_I64:
   case WebAssembly::STORE8_I64_S:
   case WebAssembly::ATOMIC_STORE8_I32:
+  case WebAssembly::ATOMIC_STORE8_I32_S:
   case WebAssembly::ATOMIC_STORE8_I64:
+  case WebAssembly::ATOMIC_STORE8_I64_S:
     return 0;
   case WebAssembly::LOAD16_S_I32:
   case WebAssembly::LOAD16_S_I32_S:
   case WebAssembly::LOAD16_U_I32:
   case WebAssembly::LOAD16_U_I32_S:
   case WebAssembly::LOAD16_S_I64:
   case WebAssembly::LOAD16_S_I64_S:
   case WebAssembly::LOAD16_U_I64:
   case WebAssembly::LOAD16_U_I64_S:
   case WebAssembly::ATOMIC_LOAD16_U_I32:
   case WebAssembly::ATOMIC_LOAD16_U_I32_S:
   case WebAssembly::ATOMIC_LOAD16_U_I64:
   case WebAssembly::ATOMIC_LOAD16_U_I64_S:
   case WebAssembly::STORE16_I32:
   case WebAssembly::STORE16_I32_S:
   case WebAssembly::STORE16_I64:
   case WebAssembly::STORE16_I64_S:
   case WebAssembly::ATOMIC_STORE16_I32:
+  case WebAssembly::ATOMIC_STORE16_I32_S:
   case WebAssembly::ATOMIC_STORE16_I64:
+  case WebAssembly::ATOMIC_STORE16_I64_S:
     return 1;
   case WebAssembly::LOAD_I32:
   case WebAssembly::LOAD_I32_S:
   case WebAssembly::LOAD_F32:
   case WebAssembly::LOAD_F32_S:
   case WebAssembly::STORE_I32:
   case WebAssembly::STORE_I32_S:
   case WebAssembly::STORE_F32:
   case WebAssembly::STORE_F32_S:
   case WebAssembly::LOAD32_S_I64:
   case WebAssembly::LOAD32_S_I64_S:
   case WebAssembly::LOAD32_U_I64:
   case WebAssembly::LOAD32_U_I64_S:
   case WebAssembly::STORE32_I64:
   case WebAssembly::STORE32_I64_S:
   case WebAssembly::ATOMIC_LOAD_I32:
   case WebAssembly::ATOMIC_LOAD_I32_S:
   case WebAssembly::ATOMIC_LOAD32_U_I64:
   case WebAssembly::ATOMIC_LOAD32_U_I64_S:
   case WebAssembly::ATOMIC_STORE_I32:
+  case WebAssembly::ATOMIC_STORE_I32_S:
   case WebAssembly::ATOMIC_STORE32_I64:
+  case WebAssembly::ATOMIC_STORE32_I64_S:
     return 2;
   case WebAssembly::LOAD_I64:
   case WebAssembly::LOAD_I64_S:
   case WebAssembly::LOAD_F64:
   case WebAssembly::LOAD_F64_S:
   case WebAssembly::STORE_I64:
   case WebAssembly::STORE_I64_S:
   case WebAssembly::STORE_F64:
   case WebAssembly::STORE_F64_S:
   case WebAssembly::ATOMIC_LOAD_I64:
   case WebAssembly::ATOMIC_LOAD_I64_S:
   case WebAssembly::ATOMIC_STORE_I64:
+  case WebAssembly::ATOMIC_STORE_I64_S:
     return 3;
   default:
     llvm_unreachable("Only loads and stores have p2align values");
   }
 }
 
 /// The operand number of the load or store address in load/store instructions.
 static const unsigned LoadAddressOperandNo = 3;

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

if (TM.getTargetTriple().isOSBinFormatELF())
     getTargetStreamer()->emitEndFunc();
 }
 
 void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   LLVM_DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n');
 
   switch (MI->getOpcode()) {
   case WebAssembly::ARGUMENT_I32:
+  case WebAssembly::ARGUMENT_I32_S:
   case WebAssembly::ARGUMENT_I64:
+  case WebAssembly::ARGUMENT_I64_S:
   case WebAssembly::ARGUMENT_F32:
+  case WebAssembly::ARGUMENT_F32_S:
   case WebAssembly::ARGUMENT_F64:
+  case WebAssembly::ARGUMENT_F64_S:
   case WebAssembly::ARGUMENT_v16i8:
+  case WebAssembly::ARGUMENT_v16i8_S:
   case WebAssembly::ARGUMENT_v8i16:
+  case WebAssembly::ARGUMENT_v8i16_S:
   case WebAssembly::ARGUMENT_v4i32:
+  case WebAssembly::ARGUMENT_v4i32_S:
   case WebAssembly::ARGUMENT_v4f32:
+  case WebAssembly::ARGUMENT_v4f32_S:
     // These represent values which are live into the function entry, so there's
     // no instruction to emit.
     break;
   case WebAssembly::FALLTHROUGH_RETURN_I32:
+  case WebAssembly::FALLTHROUGH_RETURN_I32_S:
   case WebAssembly::FALLTHROUGH_RETURN_I64:
+  case WebAssembly::FALLTHROUGH_RETURN_I64_S:
   case WebAssembly::FALLTHROUGH_RETURN_F32:
+  case WebAssembly::FALLTHROUGH_RETURN_F32_S:
   case WebAssembly::FALLTHROUGH_RETURN_F64:
+  case WebAssembly::FALLTHROUGH_RETURN_F64_S:
   case WebAssembly::FALLTHROUGH_RETURN_v16i8:
+  case WebAssembly::FALLTHROUGH_RETURN_v16i8_S:
   case WebAssembly::FALLTHROUGH_RETURN_v8i16:
+  case WebAssembly::FALLTHROUGH_RETURN_v8i16_S:
   case WebAssembly::FALLTHROUGH_RETURN_v4i32:
-  case WebAssembly::FALLTHROUGH_RETURN_v4f32: {
+  case WebAssembly::FALLTHROUGH_RETURN_v4i32_S:
+  case WebAssembly::FALLTHROUGH_RETURN_v4f32:
+  case WebAssembly::FALLTHROUGH_RETURN_v4f32_S: {
     // These instructions represent the implicit return at the end of a
-    // function body. The operand is always a pop.
-    assert(MFI->isVRegStackified(MI->getOperand(0).getReg()));
-
+    // function body. Always pops one value off the stack.
     if (isVerbose()) {
-      OutStreamer->AddComment("fallthrough-return: $pop" +
-                              Twine(MFI->getWARegStackId(
-                                  MFI->getWAReg(MI->getOperand(0).getReg()))));
+      OutStreamer->AddComment("fallthrough-return-value");
       OutStreamer->AddBlankLine();
     }
     break;
   }
   case WebAssembly::FALLTHROUGH_RETURN_VOID:
+  case WebAssembly::FALLTHROUGH_RETURN_VOID_S:
     // This instruction represents the implicit return at the end of a
     // function body with no return value.
     if (isVerbose()) {
-      OutStreamer->AddComment("fallthrough-return");
+      OutStreamer->AddComment("fallthrough-return-void");
       OutStreamer->AddBlankLine();
     }
     break;
   default: {
     WebAssemblyMCInstLower MCInstLowering(OutContext, *this);
     MCInst TmpInst;
     MCInstLowering.Lower(MI, TmpInst);
     EmitToStreamer(*OutStreamer, TmpInst);
bool WebAssemblyAsmPrinter::PrintAsmOperand(const MachineInstr *MI,
 
   if (!ExtraCode) {
     const MachineOperand &MO = MI->getOperand(OpNo);
     switch (MO.getType()) {
     case MachineOperand::MO_Immediate:
       OS << MO.getImm();
       return false;
     case MachineOperand::MO_Register:
+      // FIXME: only opcode that still contains registers, as required by
+      // MachineInstr::getDebugVariable().
+      assert(MI->getOpcode() == WebAssembly::INLINEASM);
       OS << regToString(MO);
       return false;
     case MachineOperand::MO_GlobalAddress:
       getSymbol(MO.getGlobal())->print(OS, MAI);
       printOffset(MO.getOffset(), OS);
       return false;
     case MachineOperand::MO_ExternalSymbol:
       GetExternalSymbolSymbol(MO.getSymbolName())->print(OS, MAI);

lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-explicit-locals"
 
-// A command-line option to disable this pass. Note that this produces output
-// which is not valid WebAssembly, though it may be more convenient for writing
-// LLVM unit tests with.
-static cl::opt<bool> DisableWebAssemblyExplicitLocals(
-    "disable-wasm-explicit-locals", cl::ReallyHidden,
-    cl::desc("WebAssembly: Disable emission of get_local/set_local."),
+// A command-line option to disable this pass, and keep implicit locals and
+// stackified registers for the purpose of testing with lit/llc ONLY.
+// This produces output which is not valid WebAssembly, and is not supported
+// by assemblers/disassemblers and other MC based tools.
+static cl::opt<bool> RegisterCodeGenTestMode(
+    "wasm-register-codegen-test-mode", cl::Hidden,
+    cl::desc("WebAssembly: output stack registers and implicit locals in"
+             " instruction output for test purposes only."),
+    cl::init(false));
+// This one does explicit locals but keeps stackified registers, as required
+// by some current tests.
+static cl::opt<bool> ExplicitLocalsCodeGenTestMode(
+    "wasm-explicit-locals-codegen-test-mode", cl::Hidden,
+    cl::desc("WebAssembly: output stack registers and explicit locals in"
+             " instruction output for test purposes only."),
     cl::init(false));
 
 namespace {
 class WebAssemblyExplicitLocals final : public MachineFunctionPass {
   StringRef getPassName() const override {
     return "WebAssembly Explicit Locals";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addPreserved<MachineBlockFrequencyInfo>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 public:
   static char ID; // Pass identification, replacement for typeid
   WebAssemblyExplicitLocals() : MachineFunctionPass(ID) {}
 };
 } // end anonymous namespace
 
+unsigned regInstructionToStackInstruction(unsigned OpCode);
+
 char WebAssemblyExplicitLocals::ID = 0;
 INITIALIZE_PASS(WebAssemblyExplicitLocals, DEBUG_TYPE,
                 "Convert registers to WebAssembly locals", false, false)
 
 FunctionPass *llvm::createWebAssemblyExplicitLocals() {
   return new WebAssemblyExplicitLocals();
 }
 
if (RC == &WebAssembly::F64RegClass)
     return MVT::f64;
   if (RC == &WebAssembly::EXCEPT_REFRegClass)
     return MVT::ExceptRef;
   llvm_unreachable("unrecognized register class");
 }
 
 /// Given a MachineOperand of a stackified vreg, return the instruction at the
 /// start of the expression tree.
-static MachineInstr *FindStartOfTree(MachineOperand &MO,
+static MachineInstr *findStartOfTree(MachineOperand &MO,
                                      MachineRegisterInfo &MRI,
                                      WebAssemblyFunctionInfo &MFI) {
   unsigned Reg = MO.getReg();
   assert(MFI.isVRegStackified(Reg));
   MachineInstr *Def = MRI.getVRegDef(Reg);
 
   // Find the first stackified use and proceed from there.
   for (MachineOperand &DefMO : Def->explicit_uses()) {
     if (!DefMO.isReg())
       continue;
-    return FindStartOfTree(DefMO, MRI, MFI);
+    return findStartOfTree(DefMO, MRI, MFI);
   }
 
   // If there were no stackified uses, we've reached the start.
   return Def;
 }
 
 bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) {
   LLVM_DEBUG(dbgs() << "********** Make Locals Explicit **********\n"
                        "********** Function: "
                     << MF.getName() << '\n');
 
   // Disable this pass if directed to do so.
-  if (DisableWebAssemblyExplicitLocals)
-    return false;
-
-  // Disable this pass if we aren't doing direct wasm object emission.
-  if (MF.getSubtarget<WebAssemblySubtarget>()
-        .getTargetTriple().isOSBinFormatELF())
+  if (RegisterCodeGenTestMode)
     return false;
 
   bool Changed = false;
   MachineRegisterInfo &MRI = MF.getRegInfo();
   WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
   const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
 
   // Map non-stackified virtual registers to their local ids.
   DenseMap<unsigned, unsigned> Reg2Local;
 
   // Handle ARGUMENTS first to ensure that they get the designated numbers.
   for (MachineBasicBlock::iterator I = MF.begin()->begin(),
                                    E = MF.begin()->end();
        I != E;) {
     MachineInstr &MI = *I++;
     if (!WebAssembly::isArgument(MI))
       break;
     unsigned Reg = MI.getOperand(0).getReg();
     assert(!MFI.isVRegStackified(Reg));
-    Reg2Local[Reg] = MI.getOperand(1).getImm();
+    Reg2Local[Reg] = static_cast<unsigned>(MI.getOperand(1).getImm());
     MI.eraseFromParent();
     Changed = true;
   }
 
   // Start assigning local numbers after the last parameter.
-  unsigned CurLocal = MFI.getParams().size();
+  unsigned CurLocal = static_cast<unsigned>(MFI.getParams().size());
 
   // Precompute the set of registers that are unused, so that we can insert
   // drops to their defs.
   BitVector UseEmpty(MRI.getNumVirtRegs());
-  for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i)
-    UseEmpty[i] = MRI.use_empty(TargetRegisterInfo::index2VirtReg(i));
+  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I)
+    UseEmpty[I] = MRI.use_empty(TargetRegisterInfo::index2VirtReg(I));
 
   // Visit each instruction in the function.
   for (MachineBasicBlock &MBB : MF) {
     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
       MachineInstr &MI = *I++;
       assert(!WebAssembly::isArgument(MI));
 
       if (MI.isDebugInstr() || MI.isLabel())
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
           MRI.removeRegOperandFromUseList(&MO);
           MO = MachineOperand::CreateImm(LocalId);
           continue;
         }
 
         // If we see a stackified register, prepare to insert subsequent
         // get_locals before the start of its tree.
         if (MFI.isVRegStackified(OldReg)) {
-          InsertPt = FindStartOfTree(MO, MRI, MFI);
+          InsertPt = findStartOfTree(MO, MRI, MFI);
           continue;
         }
 
         // Our contract with inline asm register operands is to provide local
         // indices as immediates.
         if (MI.getOpcode() == TargetOpcode::INLINEASM) {
           unsigned LocalId = getLocalId(Reg2Local, CurLocal, OldReg);
           MRI.removeRegOperandFromUseList(&MO);
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
       // Coalesce and eliminate COPY instructions.
       if (WebAssembly::isCopy(MI)) {
         MRI.replaceRegWith(MI.getOperand(1).getReg(),
                            MI.getOperand(0).getReg());
         MI.eraseFromParent();
         Changed = true;
       }
     }
+
+    if (!ExplicitLocalsCodeGenTestMode) {
+      // Remove all uses of stackified registers to bring the instruction format
+      // into its final stack form, and transition opcodes to their _S variant.
+      // We do this in a seperate loop, since the previous loop adds/removes
+      // instructions.
+      // See comments in lib/Target/WebAssembly/WebAssemblyInstrFormats.td for
+      // details.
+      // TODO: the code above creates new registers which are then removed here.
+      // That code could be slightly simplified by not doing that, though maybe
+      // it is simpler conceptually to keep the code above in "register mode"
+      // until this transition point.
+      for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
+           I != E;) {
+        MachineInstr &MI = *I++;
+        // FIXME: we are not processing inline assembly, which contains register
+        // operands, because it is used by later target generic code.
+        if (MI.isDebugInstr() || MI.isLabel() || MI.isInlineAsm())
+          continue;
+        auto RegOpcode = MI.getOpcode();
+        auto StackOpcode = regInstructionToStackInstruction(RegOpcode);
+        MI.setDesc(TII->get(StackOpcode));
+        // Now remove all register operands.
+        for (auto I = MI.getNumOperands(); I; --I) {
+          auto &MO = MI.getOperand(I - 1);
+          if (MO.isReg()) {
+            MI.RemoveOperand(I - 1);
+            // TODO: we should also update the MFI here or below to reflect the
+            // removed registers? The MFI is about to be deleted anyway, so
+            // maybe that is not worth it?
+          }
+        }
+      }
+    }
   }
 
   // Define the locals.
   // TODO: Sort the locals for better compression.
   MFI.setNumLocals(CurLocal - MFI.getParams().size());
-  for (size_t i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) {
-    unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
-    auto I = Reg2Local.find(Reg);
-    if (I == Reg2Local.end() || I->second < MFI.getParams().size())
+  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I) {
+    unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
+    auto RL = Reg2Local.find(Reg);
+    if (RL == Reg2Local.end() || RL->second < MFI.getParams().size())
       continue;
 
-    MFI.setLocal(I->second - MFI.getParams().size(),
+    MFI.setLocal(RL->second - MFI.getParams().size(),
                  typeForRegClass(MRI.getRegClass(Reg)));
     Changed = true;
   }
 
-#ifndef NDEBUG
-  // Assert that all registers have been stackified at this point.
-  for (const MachineBasicBlock &MBB : MF) {
-    for (const MachineInstr &MI : MBB) {
-      if (MI.isDebugInstr() || MI.isLabel())
-        continue;
-      for (const MachineOperand &MO : MI.explicit_operands()) {
-        assert(
-            (!MO.isReg() || MRI.use_empty(MO.getReg()) ||
-             MFI.isVRegStackified(MO.getReg())) &&
-            "WebAssemblyExplicitLocals failed to stackify a register operand");
-      }
-    }
-  }
-#endif
+  return Changed;
 
-  return Changed;
+unsigned regInstructionToStackInstruction(unsigned OpCode) {
+  switch (OpCode) {
+  default:
+    // You may hit this if you add new instructions, please add them below.
+    // For most of these opcodes, this function could have been implemented
+    // as "return OpCode + 1", but since table-gen alphabetically sorts them,
+    // this cannot be guaranteed (see e.g. BR and BR_IF).
+    // The approach below is the same as what the x87 backend does.
+    // TODO(wvo): to make this code cleaner, create a custom tablegen
+    // code generator that emits the table below automatically.
+    llvm_unreachable(
+          "unknown WebAssembly instruction in Explicit Locals pass");
+  case WebAssembly::ABS_F32: return WebAssembly::ABS_F32_S;
+  case WebAssembly::ABS_F64: return WebAssembly::ABS_F64_S;
+  case WebAssembly::ADD_F32: return WebAssembly::ADD_F32_S;
+  case WebAssembly::ADD_F32x4: return WebAssembly::ADD_F32x4_S;
+  case WebAssembly::ADD_F64: return WebAssembly::ADD_F64_S;
+  case WebAssembly::ADD_I16x8: return WebAssembly::ADD_I16x8_S;
+  case WebAssembly::ADD_I32: return WebAssembly::ADD_I32_S;
+  case WebAssembly::ADD_I32x4: return WebAssembly::ADD_I32x4_S;
+  case WebAssembly::ADD_I64: return WebAssembly::ADD_I64_S;
+  case WebAssembly::ADD_I8x16: return WebAssembly::ADD_I8x16_S;
+  case WebAssembly::ADJCALLSTACKDOWN: return WebAssembly::ADJCALLSTACKDOWN_S;
+  case WebAssembly::ADJCALLSTACKUP: return WebAssembly::ADJCALLSTACKUP_S;
+  case WebAssembly::AND_I32: return WebAssembly::AND_I32_S;
+  case WebAssembly::AND_I64: return WebAssembly::AND_I64_S;
+  case WebAssembly::ARGUMENT_EXCEPT_REF: return WebAssembly::ARGUMENT_EXCEPT_REF_S;
+  case WebAssembly::ARGUMENT_F32: return WebAssembly::ARGUMENT_F32_S;
+  case WebAssembly::ARGUMENT_F64: return WebAssembly::ARGUMENT_F64_S;
+  case WebAssembly::ARGUMENT_I32: return WebAssembly::ARGUMENT_I32_S;
+  case WebAssembly::ARGUMENT_I64: return WebAssembly::ARGUMENT_I64_S;
+  case WebAssembly::ARGUMENT_v16i8: return WebAssembly::ARGUMENT_v16i8_S;
+  case WebAssembly::ARGUMENT_v4f32: return WebAssembly::ARGUMENT_v4f32_S;
+  case WebAssembly::ARGUMENT_v4i32: return WebAssembly::ARGUMENT_v4i32_S;
+  case WebAssembly::ARGUMENT_v8i16: return WebAssembly::ARGUMENT_v8i16_S;
+  case WebAssembly::ATOMIC_LOAD16_U_I32: return WebAssembly::ATOMIC_LOAD16_U_I32_S;
+  case WebAssembly::ATOMIC_LOAD16_U_I64: return WebAssembly::ATOMIC_LOAD16_U_I64_S;
+  case WebAssembly::ATOMIC_LOAD32_U_I64: return WebAssembly::ATOMIC_LOAD32_U_I64_S;
+  case WebAssembly::ATOMIC_LOAD8_U_I32: return WebAssembly::ATOMIC_LOAD8_U_I32_S;
+  case WebAssembly::ATOMIC_LOAD8_U_I64: return WebAssembly::ATOMIC_LOAD8_U_I64_S;
+  case WebAssembly::ATOMIC_LOAD_I32: return WebAssembly::ATOMIC_LOAD_I32_S;
+  case WebAssembly::ATOMIC_LOAD_I64: return WebAssembly::ATOMIC_LOAD_I64_S;
+  case WebAssembly::ATOMIC_STORE16_I32: return WebAssembly::ATOMIC_STORE16_I32_S;
+  case WebAssembly::ATOMIC_STORE16_I64: return WebAssembly::ATOMIC_STORE16_I64_S;
+  case WebAssembly::ATOMIC_STORE32_I64: return WebAssembly::ATOMIC_STORE32_I64_S;
+  case WebAssembly::ATOMIC_STORE8_I32: return WebAssembly::ATOMIC_STORE8_I32_S;
+  case WebAssembly::ATOMIC_STORE8_I64: return WebAssembly::ATOMIC_STORE8_I64_S;
+  case WebAssembly::ATOMIC_STORE_I32: return WebAssembly::ATOMIC_STORE_I32_S;
+  case WebAssembly::ATOMIC_STORE_I64: return WebAssembly::ATOMIC_STORE_I64_S;
+  case WebAssembly::BLOCK: return WebAssembly::BLOCK_S;
+  case WebAssembly::BR: return WebAssembly::BR_S;
+  case WebAssembly::BR_IF: return WebAssembly::BR_IF_S;
+  case WebAssembly::BR_TABLE_I32: return WebAssembly::BR_TABLE_I32_S;
+  case WebAssembly::BR_TABLE_I64: return WebAssembly::BR_TABLE_I64_S;
+  case WebAssembly::BR_UNLESS: return WebAssembly::BR_UNLESS_S;
+  case WebAssembly::CALL_EXCEPT_REF: return WebAssembly::CALL_EXCEPT_REF_S;
+  case WebAssembly::CALL_F32: return WebAssembly::CALL_F32_S;
+  case WebAssembly::CALL_F64: return WebAssembly::CALL_F64_S;
+  case WebAssembly::CALL_I32: return WebAssembly::CALL_I32_S;
+  case WebAssembly::CALL_I64: return WebAssembly::CALL_I64_S;
+  case WebAssembly::CALL_INDIRECT_EXCEPT_REF: return WebAssembly::CALL_INDIRECT_EXCEPT_REF_S;
+  case WebAssembly::CALL_INDIRECT_F32: return WebAssembly::CALL_INDIRECT_F32_S;
+  case WebAssembly::CALL_INDIRECT_F64: return WebAssembly::CALL_INDIRECT_F64_S;
+  case WebAssembly::CALL_INDIRECT_I32: return WebAssembly::CALL_INDIRECT_I32_S;
+  case WebAssembly::CALL_INDIRECT_I64: return WebAssembly::CALL_INDIRECT_I64_S;
+  case WebAssembly::CALL_INDIRECT_VOID: return WebAssembly::CALL_INDIRECT_VOID_S;
+  case WebAssembly::CALL_INDIRECT_v16i8: return WebAssembly::CALL_INDIRECT_v16i8_S;
+  case WebAssembly::CALL_INDIRECT_v4f32: return WebAssembly::CALL_INDIRECT_v4f32_S;
+  case WebAssembly::CALL_INDIRECT_v4i32: return WebAssembly::CALL_INDIRECT_v4i32_S;
+  case WebAssembly::CALL_INDIRECT_v8i16: return WebAssembly::CALL_INDIRECT_v8i16_S;
+  case WebAssembly::CALL_VOID: return WebAssembly::CALL_VOID_S;
+  case WebAssembly::CALL_v16i8: return WebAssembly::CALL_v16i8_S;
+  case WebAssembly::CALL_v4f32: return WebAssembly::CALL_v4f32_S;
+  case WebAssembly::CALL_v4i32: return WebAssembly::CALL_v4i32_S;
+  case WebAssembly::CALL_v8i16: return WebAssembly::CALL_v8i16_S;
+  case WebAssembly::CATCHRET: return WebAssembly::CATCHRET_S;
+  case WebAssembly::CATCH_ALL: return WebAssembly::CATCH_ALL_S;
+  case WebAssembly::CATCH_I32: return WebAssembly::CATCH_I32_S;
+  case WebAssembly::CATCH_I64: return WebAssembly::CATCH_I64_S;
+  case WebAssembly::CEIL_F32: return WebAssembly::CEIL_F32_S;
+  case WebAssembly::CEIL_F64: return WebAssembly::CEIL_F64_S;
+  case WebAssembly::CLEANUPRET: return WebAssembly::CLEANUPRET_S;
+  case WebAssembly::CLZ_I32: return WebAssembly::CLZ_I32_S;
+  case WebAssembly::CLZ_I64: return WebAssembly::CLZ_I64_S;
+  case WebAssembly::CONST_F32: return WebAssembly::CONST_F32_S;
+  case WebAssembly::CONST_F64: return WebAssembly::CONST_F64_S;
+  case WebAssembly::CONST_I32: return WebAssembly::CONST_I32_S;
+  case WebAssembly::CONST_I64: return WebAssembly::CONST_I64_S;
+  case WebAssembly::COPYSIGN_F32: return WebAssembly::COPYSIGN_F32_S;
+  case WebAssembly::COPYSIGN_F64: return WebAssembly::COPYSIGN_F64_S;
+  case WebAssembly::COPY_EXCEPT_REF: return WebAssembly::COPY_EXCEPT_REF_S;
+  case WebAssembly::COPY_F32: return WebAssembly::COPY_F32_S;
+  case WebAssembly::COPY_F64: return WebAssembly::COPY_F64_S;
+  case WebAssembly::COPY_I32: return WebAssembly::COPY_I32_S;
+  case WebAssembly::COPY_I64: return WebAssembly::COPY_I64_S;
+  case WebAssembly::COPY_V128: return WebAssembly::COPY_V128_S;
+  case WebAssembly::CTZ_I32: return WebAssembly::CTZ_I32_S;
+  case WebAssembly::CTZ_I64: return WebAssembly::CTZ_I64_S;
+  case WebAssembly::CURRENT_MEMORY_I32: return WebAssembly::CURRENT_MEMORY_I32_S;
+  case WebAssembly::DIV_F32: return WebAssembly::DIV_F32_S;
+  case WebAssembly::DIV_F64: return WebAssembly::DIV_F64_S;
+  case WebAssembly::DIV_S_I32: return WebAssembly::DIV_S_I32_S;
+  case WebAssembly::DIV_S_I64: return WebAssembly::DIV_S_I64_S;
+  case WebAssembly::DIV_U_I32: return WebAssembly::DIV_U_I32_S;
+  case WebAssembly::DIV_U_I64: return WebAssembly::DIV_U_I64_S;
+  case WebAssembly::DROP_EXCEPT_REF: return WebAssembly::DROP_EXCEPT_REF_S;
+  case WebAssembly::DROP_F32: return WebAssembly::DROP_F32_S;
+  case WebAssembly::DROP_F64: return WebAssembly::DROP_F64_S;
+  case WebAssembly::DROP_I32: return WebAssembly::DROP_I32_S;
+  case WebAssembly::DROP_I64: return WebAssembly::DROP_I64_S;
+  case WebAssembly::DROP_V128: return WebAssembly::DROP_V128_S;
+  case WebAssembly::END_BLOCK: return WebAssembly::END_BLOCK_S;
+  case WebAssembly::END_FUNCTION: return WebAssembly::END_FUNCTION_S;
+  case WebAssembly::END_LOOP: return WebAssembly::END_LOOP_S;
+  case WebAssembly::END_TRY: return WebAssembly::END_TRY_S;
+  case WebAssembly::EQZ_I32: return WebAssembly::EQZ_I32_S;
+  case WebAssembly::EQZ_I64: return WebAssembly::EQZ_I64_S;
+  case WebAssembly::EQ_F32: return WebAssembly::EQ_F32_S;
+  case WebAssembly::EQ_F64: return WebAssembly::EQ_F64_S;
+  case WebAssembly::EQ_I32: return WebAssembly::EQ_I32_S;
+  case WebAssembly::EQ_I64: return WebAssembly::EQ_I64_S;
+  case WebAssembly::F32_CONVERT_S_I32: return WebAssembly::F32_CONVERT_S_I32_S;
+  case WebAssembly::F32_CONVERT_S_I64: return WebAssembly::F32_CONVERT_S_I64_S;
+  case WebAssembly::F32_CONVERT_U_I32: return WebAssembly::F32_CONVERT_U_I32_S;
+  case WebAssembly::F32_CONVERT_U_I64: return WebAssembly::F32_CONVERT_U_I64_S;
+  case WebAssembly::F32_DEMOTE_F64: return WebAssembly::F32_DEMOTE_F64_S;
+  case WebAssembly::F32_REINTERPRET_I32: return WebAssembly::F32_REINTERPRET_I32_S;
+  case WebAssembly::F64_CONVERT_S_I32: return WebAssembly::F64_CONVERT_S_I32_S;
+  case WebAssembly::F64_CONVERT_S_I64: return WebAssembly::F64_CONVERT_S_I64_S;
+  case WebAssembly::F64_CONVERT_U_I32: return WebAssembly::F64_CONVERT_U_I32_S;
+  case WebAssembly::F64_CONVERT_U_I64: return WebAssembly::F64_CONVERT_U_I64_S;
+  case WebAssembly::F64_PROMOTE_F32: return WebAssembly::F64_PROMOTE_F32_S;
+  case WebAssembly::F64_REINTERPRET_I64: return WebAssembly::F64_REINTERPRET_I64_S;
+  case WebAssembly::FALLTHROUGH_RETURN_EXCEPT_REF: return WebAssembly::FALLTHROUGH_RETURN_EXCEPT_REF_S;
+  case WebAssembly::FALLTHROUGH_RETURN_F32: return WebAssembly::FALLTHROUGH_RETURN_F32_S;
+  case WebAssembly::FALLTHROUGH_RETURN_F64: return WebAssembly::FALLTHROUGH_RETURN_F64_S;
+  case WebAssembly::FALLTHROUGH_RETURN_I32: return WebAssembly::FALLTHROUGH_RETURN_I32_S;
+  case WebAssembly::FALLTHROUGH_RETURN_I64: return WebAssembly::FALLTHROUGH_RETURN_I64_S;
+  case WebAssembly::FALLTHROUGH_RETURN_VOID: return WebAssembly::FALLTHROUGH_RETURN_VOID_S;
+  case WebAssembly::FALLTHROUGH_RETURN_v16i8: return WebAssembly::FALLTHROUGH_RETURN_v16i8_S;
+  case WebAssembly::FALLTHROUGH_RETURN_v4f32: return WebAssembly::FALLTHROUGH_RETURN_v4f32_S;
+  case WebAssembly::FALLTHROUGH_RETURN_v4i32: return WebAssembly::FALLTHROUGH_RETURN_v4i32_S;
+  case WebAssembly::FALLTHROUGH_RETURN_v8i16: return WebAssembly::FALLTHROUGH_RETURN_v8i16_S;
+  case WebAssembly::FLOOR_F32: return WebAssembly::FLOOR_F32_S;
+  case WebAssembly::FLOOR_F64: return WebAssembly::FLOOR_F64_S;
+  case WebAssembly::FP_TO_SINT_I32_F32: return WebAssembly::FP_TO_SINT_I32_F32_S;
+  case WebAssembly::FP_TO_SINT_I32_F64: return WebAssembly::FP_TO_SINT_I32_F64_S;
+  case WebAssembly::FP_TO_SINT_I64_F32: return WebAssembly::FP_TO_SINT_I64_F32_S;
+  case WebAssembly::FP_TO_SINT_I64_F64: return WebAssembly::FP_TO_SINT_I64_F64_S;
+  case WebAssembly::FP_TO_UINT_I32_F32: return WebAssembly::FP_TO_UINT_I32_F32_S;
+  case WebAssembly::FP_TO_UINT_I32_F64: return WebAssembly::FP_TO_UINT_I32_F64_S;
+  case WebAssembly::FP_TO_UINT_I64_F32: return WebAssembly::FP_TO_UINT_I64_F32_S;
+  case WebAssembly::FP_TO_UINT_I64_F64: return WebAssembly::FP_TO_UINT_I64_F64_S;
+  case WebAssembly::GET_GLOBAL_EXCEPT_REF: return WebAssembly::GET_GLOBAL_EXCEPT_REF_S;
+  case WebAssembly::GET_GLOBAL_F32: return WebAssembly::GET_GLOBAL_F32_S;
+  case WebAssembly::GET_GLOBAL_F64: return WebAssembly::GET_GLOBAL_F64_S;
+  case WebAssembly::GET_GLOBAL_I32: return WebAssembly::GET_GLOBAL_I32_S;
+  case WebAssembly::GET_GLOBAL_I64: return WebAssembly::GET_GLOBAL_I64_S;
+  case WebAssembly::GET_GLOBAL_V128: return WebAssembly::GET_GLOBAL_V128_S;
+  case WebAssembly::GET_LOCAL_EXCEPT_REF: return WebAssembly::GET_LOCAL_EXCEPT_REF_S;
+  case WebAssembly::GET_LOCAL_F32: return WebAssembly::GET_LOCAL_F32_S;
+  case WebAssembly::GET_LOCAL_F64: return WebAssembly::GET_LOCAL_F64_S;
+  case WebAssembly::GET_LOCAL_I32: return WebAssembly::GET_LOCAL_I32_S;
+  case WebAssembly::GET_LOCAL_I64: return WebAssembly::GET_LOCAL_I64_S;
+  case WebAssembly::GET_LOCAL_V128: return WebAssembly::GET_LOCAL_V128_S;
+  case WebAssembly::GE_F32: return WebAssembly::GE_F32_S;
+  case WebAssembly::GE_F64: return WebAssembly::GE_F64_S;
+  case WebAssembly::GE_S_I32: return WebAssembly::GE_S_I32_S;
+  case WebAssembly::GE_S_I64: return WebAssembly::GE_S_I64_S;
+  case WebAssembly::GE_U_I32: return WebAssembly::GE_U_I32_S;
+  case WebAssembly::GE_U_I64: return WebAssembly::GE_U_I64_S;
+  case WebAssembly::GROW_MEMORY_I32: return WebAssembly::GROW_MEMORY_I32_S;
+  case WebAssembly::GT_F32: return WebAssembly::GT_F32_S;
+  case WebAssembly::GT_F64: return WebAssembly::GT_F64_S;
+  case WebAssembly::GT_S_I32: return WebAssembly::GT_S_I32_S;
+  case WebAssembly::GT_S_I64: return WebAssembly::GT_S_I64_S;
+  case WebAssembly::GT_U_I32: return WebAssembly::GT_U_I32_S;
+  case WebAssembly::GT_U_I64: return WebAssembly::GT_U_I64_S;
+  case WebAssembly::I32_EXTEND16_S_I32: return WebAssembly::I32_EXTEND16_S_I32_S;
+  case WebAssembly::I32_EXTEND8_S_I32: return WebAssembly::I32_EXTEND8_S_I32_S;
+  case WebAssembly::I32_REINTERPRET_F32: return WebAssembly::I32_REINTERPRET_F32_S;
+  case WebAssembly::I32_TRUNC_S_F32: return WebAssembly::I32_TRUNC_S_F32_S;
+  case WebAssembly::I32_TRUNC_S_F64: return WebAssembly::I32_TRUNC_S_F64_S;
+  case WebAssembly::I32_TRUNC_S_SAT_F32: return WebAssembly::I32_TRUNC_S_SAT_F32_S;
+  case WebAssembly::I32_TRUNC_S_SAT_F64: return WebAssembly::I32_TRUNC_S_SAT_F64_S;
+  case WebAssembly::I32_TRUNC_U_F32: return WebAssembly::I32_TRUNC_U_F32_S;
+  case WebAssembly::I32_TRUNC_U_F64: return WebAssembly::I32_TRUNC_U_F64_S;
+  case WebAssembly::I32_TRUNC_U_SAT_F32: return WebAssembly::I32_TRUNC_U_SAT_F32_S;
+  case WebAssembly::I32_TRUNC_U_SAT_F64: return WebAssembly::I32_TRUNC_U_SAT_F64_S;
+  case WebAssembly::I32_WRAP_I64: return WebAssembly::I32_WRAP_I64_S;
+  case WebAssembly::I64_EXTEND16_S_I64: return WebAssembly::I64_EXTEND16_S_I64_S;
+  case WebAssembly::I64_EXTEND32_S_I64: return WebAssembly::I64_EXTEND32_S_I64_S;
+  case WebAssembly::I64_EXTEND8_S_I64: return WebAssembly::I64_EXTEND8_S_I64_S;
+  case WebAssembly::I64_EXTEND_S_I32: return WebAssembly::I64_EXTEND_S_I32_S;
+  case WebAssembly::I64_EXTEND_U_I32: return WebAssembly::I64_EXTEND_U_I32_S;
+  case WebAssembly::I64_REINTERPRET_F64: return WebAssembly::I64_REINTERPRET_F64_S;
+  case WebAssembly::I64_TRUNC_S_F32: return WebAssembly::I64_TRUNC_S_F32_S;
+  case WebAssembly::I64_TRUNC_S_F64: return WebAssembly::I64_TRUNC_S_F64_S;
+  case WebAssembly::I64_TRUNC_S_SAT_F32: return WebAssembly::I64_TRUNC_S_SAT_F32_S;
+  case WebAssembly::I64_TRUNC_S_SAT_F64: return WebAssembly::I64_TRUNC_S_SAT_F64_S;
+  case WebAssembly::I64_TRUNC_U_F32: return WebAssembly::I64_TRUNC_U_F32_S;
+  case WebAssembly::I64_TRUNC_U_F64: return WebAssembly::I64_TRUNC_U_F64_S;
+  case WebAssembly::I64_TRUNC_U_SAT_F32: return WebAssembly::I64_TRUNC_U_SAT_F32_S;
+  case WebAssembly::I64_TRUNC_U_SAT_F64: return WebAssembly::I64_TRUNC_U_SAT_F64_S;
+  case WebAssembly::LE_F32: return WebAssembly::LE_F32_S;
+  case WebAssembly::LE_F64: return WebAssembly::LE_F64_S;
+  case WebAssembly::LE_S_I32: return WebAssembly::LE_S_I32_S;
+  case WebAssembly::LE_S_I64: return WebAssembly::LE_S_I64_S;
+  case WebAssembly::LE_U_I32: return WebAssembly::LE_U_I32_S;
+  case WebAssembly::LE_U_I64: return WebAssembly::LE_U_I64_S;
+  case WebAssembly::LOAD16_S_I32: return WebAssembly::LOAD16_S_I32_S;
+  case WebAssembly::LOAD16_S_I64: return WebAssembly::LOAD16_S_I64_S;
+  case WebAssembly::LOAD16_U_I32: return WebAssembly::LOAD16_U_I32_S;
+  case WebAssembly::LOAD16_U_I64: return WebAssembly::LOAD16_U_I64_S;
+  case WebAssembly::LOAD32_S_I64: return WebAssembly::LOAD32_S_I64_S;
+  case WebAssembly::LOAD32_U_I64: return WebAssembly::LOAD32_U_I64_S;
+  case WebAssembly::LOAD8_S_I32: return WebAssembly::LOAD8_S_I32_S;
+  case WebAssembly::LOAD8_S_I64: return WebAssembly::LOAD8_S_I64_S;
+  case WebAssembly::LOAD8_U_I32: return WebAssembly::LOAD8_U_I32_S;
+  case WebAssembly::LOAD8_U_I64: return WebAssembly::LOAD8_U_I64_S;
+  case WebAssembly::LOAD_F32: return WebAssembly::LOAD_F32_S;
+  case WebAssembly::LOAD_F64: return WebAssembly::LOAD_F64_S;
+  case WebAssembly::LOAD_I32: return WebAssembly::LOAD_I32_S;
+  case WebAssembly::LOAD_I64: return WebAssembly::LOAD_I64_S;
+  case WebAssembly::LOOP: return WebAssembly::LOOP_S;
+  case WebAssembly::LT_F32: return WebAssembly::LT_F32_S;
+  case WebAssembly::LT_F64: return WebAssembly::LT_F64_S;
+  case WebAssembly::LT_S_I32: return WebAssembly::LT_S_I32_S;
+  case WebAssembly::LT_S_I64: return WebAssembly::LT_S_I64_S;
+  case WebAssembly::LT_U_I32: return WebAssembly::LT_U_I32_S;
+  case WebAssembly::LT_U_I64: return WebAssembly::LT_U_I64_S;
+  case WebAssembly::MAX_F32: return WebAssembly::MAX_F32_S;
+  case WebAssembly::MAX_F64: return WebAssembly::MAX_F64_S;
+  case WebAssembly::MEMORY_GROW_I32: return WebAssembly::MEMORY_GROW_I32_S;
+  case WebAssembly::MEMORY_SIZE_I32: return WebAssembly::MEMORY_SIZE_I32_S;
+  case WebAssembly::MEM_GROW_I32: return WebAssembly::MEM_GROW_I32_S;
+  case WebAssembly::MEM_SIZE_I32: return WebAssembly::MEM_SIZE_I32_S;
+  case WebAssembly::MIN_F32: return WebAssembly::MIN_F32_S;
+  case WebAssembly::MIN_F64: return WebAssembly::MIN_F64_S;
+  case WebAssembly::MUL_F32: return WebAssembly::MUL_F32_S;
+  case WebAssembly::MUL_F32x4: return WebAssembly::MUL_F32x4_S;
+  case WebAssembly::MUL_F64: return WebAssembly::MUL_F64_S;
+  case WebAssembly::MUL_I16x8: return WebAssembly::MUL_I16x8_S;
+  case WebAssembly::MUL_I32: return WebAssembly::MUL_I32_S;
+  case WebAssembly::MUL_I32x4: return WebAssembly::MUL_I32x4_S;
+  case WebAssembly::MUL_I64: return WebAssembly::MUL_I64_S;
+  case WebAssembly::MUL_I8x16: return WebAssembly::MUL_I8x16_S;
+  case WebAssembly::NEAREST_F32: return WebAssembly::NEAREST_F32_S;
+  case WebAssembly::NEAREST_F64: return WebAssembly::NEAREST_F64_S;
+  case WebAssembly::NEG_F32: return WebAssembly::NEG_F32_S;
+  case WebAssembly::NEG_F64: return WebAssembly::NEG_F64_S;
+  case WebAssembly::NE_F32: return WebAssembly::NE_F32_S;
+  case WebAssembly::NE_F64: return WebAssembly::NE_F64_S;
+  case WebAssembly::NE_I32: return WebAssembly::NE_I32_S;
+  case WebAssembly::NE_I64: return WebAssembly::NE_I64_S;
+  case WebAssembly::NOP: return WebAssembly::NOP_S;
+  case WebAssembly::OR_I32: return WebAssembly::OR_I32_S;
+  case WebAssembly::OR_I64: return WebAssembly::OR_I64_S;
+  case WebAssembly::PCALL_INDIRECT_EXCEPT_REF: return WebAssembly::PCALL_INDIRECT_EXCEPT_REF_S;
+  case WebAssembly::PCALL_INDIRECT_F32: return WebAssembly::PCALL_INDIRECT_F32_S;
+  case WebAssembly::PCALL_INDIRECT_F64: return WebAssembly::PCALL_INDIRECT_F64_S;
+  case WebAssembly::PCALL_INDIRECT_I32: return WebAssembly::PCALL_INDIRECT_I32_S;
+  case WebAssembly::PCALL_INDIRECT_I64: return WebAssembly::PCALL_INDIRECT_I64_S;
+  case WebAssembly::PCALL_INDIRECT_VOID: return WebAssembly::PCALL_INDIRECT_VOID_S;
+  case WebAssembly::PCALL_INDIRECT_v16i8: return WebAssembly::PCALL_INDIRECT_v16i8_S;
+  case WebAssembly::PCALL_INDIRECT_v4f32: return WebAssembly::PCALL_INDIRECT_v4f32_S;
+  case WebAssembly::PCALL_INDIRECT_v4i32: return WebAssembly::PCALL_INDIRECT_v4i32_S;
+  case WebAssembly::PCALL_INDIRECT_v8i16: return WebAssembly::PCALL_INDIRECT_v8i16_S;
+  case WebAssembly::POPCNT_I32: return WebAssembly::POPCNT_I32_S;
+  case WebAssembly::POPCNT_I64: return WebAssembly::POPCNT_I64_S;
+  case WebAssembly::REM_S_I32: return WebAssembly::REM_S_I32_S;
+  case WebAssembly::REM_S_I64: return WebAssembly::REM_S_I64_S;
+  case WebAssembly::REM_U_I32: return WebAssembly::REM_U_I32_S;
+  case WebAssembly::REM_U_I64: return WebAssembly::REM_U_I64_S;
+  case WebAssembly::RETHROW: return WebAssembly::RETHROW_S;
+  case WebAssembly::RETHROW_TO_CALLER: return WebAssembly::RETHROW_TO_CALLER_S;
+  case WebAssembly::RETURN_EXCEPT_REF: return WebAssembly::RETURN_EXCEPT_REF_S;
+  case WebAssembly::RETURN_F32: return WebAssembly::RETURN_F32_S;
+  case WebAssembly::RETURN_F64: return WebAssembly::RETURN_F64_S;
+  case WebAssembly::RETURN_I32: return WebAssembly::RETURN_I32_S;
+  case WebAssembly::RETURN_I64: return WebAssembly::RETURN_I64_S;
+  case WebAssembly::RETURN_VOID: return WebAssembly::RETURN_VOID_S;
+  case WebAssembly::RETURN_v16i8: return WebAssembly::RETURN_v16i8_S;
+  case WebAssembly::RETURN_v4f32: return WebAssembly::RETURN_v4f32_S;
+  case WebAssembly::RETURN_v4i32: return WebAssembly::RETURN_v4i32_S;
+  case WebAssembly::RETURN_v8i16: return WebAssembly::RETURN_v8i16_S;
+  case WebAssembly::ROTL_I32: return WebAssembly::ROTL_I32_S;
+  case WebAssembly::ROTL_I64: return WebAssembly::ROTL_I64_S;
+  case WebAssembly::ROTR_I32: return WebAssembly::ROTR_I32_S;
+  case WebAssembly::ROTR_I64: return WebAssembly::ROTR_I64_S;
+  case WebAssembly::SELECT_EXCEPT_REF: return WebAssembly::SELECT_EXCEPT_REF_S;
+  case WebAssembly::SELECT_F32: return WebAssembly::SELECT_F32_S;
+  case WebAssembly::SELECT_F64: return WebAssembly::SELECT_F64_S;
+  case WebAssembly::SELECT_I32: return WebAssembly::SELECT_I32_S;
+  case WebAssembly::SELECT_I64: return WebAssembly::SELECT_I64_S;
+  case WebAssembly::SET_GLOBAL_EXCEPT_REF: return WebAssembly::SET_GLOBAL_EXCEPT_REF_S;
+  case WebAssembly::SET_GLOBAL_F32: return WebAssembly::SET_GLOBAL_F32_S;
+  case WebAssembly::SET_GLOBAL_F64: return WebAssembly::SET_GLOBAL_F64_S;
+  case WebAssembly::SET_GLOBAL_I32: return WebAssembly::SET_GLOBAL_I32_S;
+  case WebAssembly::SET_GLOBAL_I64: return WebAssembly::SET_GLOBAL_I64_S;
+  case WebAssembly::SET_GLOBAL_V128: return WebAssembly::SET_GLOBAL_V128_S;
+  case WebAssembly::SET_LOCAL_EXCEPT_REF: return WebAssembly::SET_LOCAL_EXCEPT_REF_S;
+  case WebAssembly::SET_LOCAL_F32: return WebAssembly::SET_LOCAL_F32_S;
+  case WebAssembly::SET_LOCAL_F64: return WebAssembly::SET_LOCAL_F64_S;
+  case WebAssembly::SET_LOCAL_I32: return WebAssembly::SET_LOCAL_I32_S;
+  case WebAssembly::SET_LOCAL_I64: return WebAssembly::SET_LOCAL_I64_S;
+  case WebAssembly::SET_LOCAL_V128: return WebAssembly::SET_LOCAL_V128_S;
+  case WebAssembly::SHL_I32: return WebAssembly::SHL_I32_S;
+  case WebAssembly::SHL_I64: return WebAssembly::SHL_I64_S;
+  case WebAssembly::SHR_S_I32: return WebAssembly::SHR_S_I32_S;
+  case WebAssembly::SHR_S_I64: return WebAssembly::SHR_S_I64_S;
+  case WebAssembly::SHR_U_I32: return WebAssembly::SHR_U_I32_S;
+  case WebAssembly::SHR_U_I64: return WebAssembly::SHR_U_I64_S;
+  case WebAssembly::SQRT_F32: return WebAssembly::SQRT_F32_S;
+  case WebAssembly::SQRT_F64: return WebAssembly::SQRT_F64_S;
+  case WebAssembly::STORE16_I32: return WebAssembly::STORE16_I32_S;
+  case WebAssembly::STORE16_I64: return WebAssembly::STORE16_I64_S;
+  case WebAssembly::STORE32_I64: return WebAssembly::STORE32_I64_S;
+  case WebAssembly::STORE8_I32: return WebAssembly::STORE8_I32_S;
+  case WebAssembly::STORE8_I64: return WebAssembly::STORE8_I64_S;
+  case WebAssembly::STORE_F32: return WebAssembly::STORE_F32_S;
+  case WebAssembly::STORE_F64: return WebAssembly::STORE_F64_S;
+  case WebAssembly::STORE_I32: return WebAssembly::STORE_I32_S;
+  case WebAssembly::STORE_I64: return WebAssembly::STORE_I64_S;
+  case WebAssembly::SUB_F32: return WebAssembly::SUB_F32_S;
+  case WebAssembly::SUB_F32x4: return WebAssembly::SUB_F32x4_S;
+  case WebAssembly::SUB_F64: return WebAssembly::SUB_F64_S;
+  case WebAssembly::SUB_I16x8: return WebAssembly::SUB_I16x8_S;
+  case WebAssembly::SUB_I32: return WebAssembly::SUB_I32_S;
+  case WebAssembly::SUB_I32x4: return WebAssembly::SUB_I32x4_S;
+  case WebAssembly::SUB_I64: return WebAssembly::SUB_I64_S;
+  case WebAssembly::SUB_I8x16: return WebAssembly::SUB_I8x16_S;
+  case WebAssembly::TEE_EXCEPT_REF: return WebAssembly::TEE_EXCEPT_REF_S;
+  case WebAssembly::TEE_F32: return WebAssembly::TEE_F32_S;
+  case WebAssembly::TEE_F64: return WebAssembly::TEE_F64_S;
+  case WebAssembly::TEE_I32: return WebAssembly::TEE_I32_S;
+  case WebAssembly::TEE_I64: return WebAssembly::TEE_I64_S;
+  case WebAssembly::TEE_LOCAL_EXCEPT_REF: return WebAssembly::TEE_LOCAL_EXCEPT_REF_S;
+  case WebAssembly::TEE_LOCAL_F32: return WebAssembly::TEE_LOCAL_F32_S;
+  case WebAssembly::TEE_LOCAL_F64: return WebAssembly::TEE_LOCAL_F64_S;
+  case WebAssembly::TEE_LOCAL_I32: return WebAssembly::TEE_LOCAL_I32_S;
+  case WebAssembly::TEE_LOCAL_I64: return WebAssembly::TEE_LOCAL_I64_S;
+  case WebAssembly::TEE_LOCAL_V128: return WebAssembly::TEE_LOCAL_V128_S;
+  case WebAssembly::TEE_V128: return WebAssembly::TEE_V128_S;
+  case WebAssembly::THROW_I32: return WebAssembly::THROW_I32_S;
+  case WebAssembly::THROW_I64: return WebAssembly::THROW_I64_S;
+  case WebAssembly::TRUNC_F32: return WebAssembly::TRUNC_F32_S;
+  case WebAssembly::TRUNC_F64: return WebAssembly::TRUNC_F64_S;
+  case WebAssembly::TRY: return WebAssembly::TRY_S;
+  case WebAssembly::UNREACHABLE: return WebAssembly::UNREACHABLE_S;
+  case WebAssembly::XOR_I32: return WebAssembly::XOR_I32_S;
+  case WebAssembly::XOR_I64: return WebAssembly::XOR_I64_S;
+  }
 }

lib/Target/WebAssembly/WebAssemblyInstrMemory.td

 
 // We don't need a regPlusES because external symbols never have constant
 // offsets folded into them, so we can just use add.
 
 let Defs = [ARGUMENTS] in {
 
 // Defines atomic and non-atomic loads, regular and extending.
 multiclass WebAssemblyLoad<WebAssemblyRegClass rc, string Name, int Opcode> {
+  let mayLoad = 1 in
   defm "": I<(outs rc:$dst),
              (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
              (outs), (ins P2Align:$p2align, offset32_op:$off),
              [], !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}"),
-             !strconcat(Name, "\t${off}, ${p2align}"), Opcode>;
+             !strconcat(Name, "\t${off}${p2align}"), Opcode>;
 }
 
 // Basic load.
 // FIXME: When we can break syntax compatibility, reorder the fields in the
 // asmstrings to match the binary encoding.
 defm LOAD_I32 : WebAssemblyLoad<I32, "i32.load", 0x28>;
 defm LOAD_I64 : WebAssemblyLoad<I64, "i64.load", 0x29>;
 defm LOAD_F32 : WebAssemblyLoad<F32, "f32.load", 0x2a>;

 def : LoadPatExternSymOffOnly<i64, extloadi16, LOAD16_U_I64>;
 def : LoadPatExternSymOffOnly<i64, extloadi32, LOAD32_U_I64>;
 
 
 let Defs = [ARGUMENTS] in {
 
 // Defines atomic and non-atomic stores, regular and truncating
 multiclass WebAssemblyStore<WebAssemblyRegClass rc, string Name, int Opcode> {
+  let mayStore = 1 in
   defm "" : I<(outs),
               (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val),
               (outs),
               (ins P2Align:$p2align, offset32_op:$off), [],
               !strconcat(Name, "\t${off}(${addr})${p2align}, $val"),
-              !strconcat(Name, "\t${off}, ${p2align}"), Opcode>;
+              !strconcat(Name, "\t${off}${p2align}"), Opcode>;
 }
 // Basic store.
 // Note: WebAssembly inverts SelectionDAG's usual operand order.
 defm STORE_I32  : WebAssemblyStore<I32, "i32.store", 0x36>;
 defm STORE_I64  : WebAssemblyStore<I64, "i64.store", 0x37>;
 defm STORE_F32  : WebAssemblyStore<F32, "f32.store", 0x38>;
 defm STORE_F64  : WebAssemblyStore<F64, "f64.store", 0x39>;
 
defm CURRENT_MEMORY_I32 : I<(outs I32:$dst), (ins i32imm:$flags),
                             (outs), (ins i32imm:$flags),
                             [],
                             "current_memory\t$dst",
                             "current_memory\t$flags", 0x3f>,
                           Requires<[HasAddr32]>;
 
 // Grow memory.
 defm MEMORY_GROW_I32 : I<(outs I32:$dst), (ins i32imm:$flags, I32:$delta),
-                         (outs), (ins i32imm:$flags, I32:$delta),
+                         (outs), (ins i32imm:$flags),
                          [(set I32:$dst,
                            (int_wasm_memory_grow (i32 imm:$flags),
                              I32:$delta))],
                          "memory.grow\t$dst, $flags, $delta",
-                         "memory.grow\t$flags, $delta", 0x3f>,
+                         "memory.grow\t$flags", 0x3f>,
                        Requires<[HasAddr32]>;
 defm MEM_GROW_I32 : I<(outs I32:$dst), (ins i32imm:$flags, I32:$delta),
                       (outs), (ins i32imm:$flags),
                       [(set I32:$dst,
                             (int_wasm_mem_grow (i32 imm:$flags), I32:$delta))],
                       "mem.grow\t$dst, $flags, $delta", "mem.grow\t$flags",
                       0x3f>,
                     Requires<[HasAddr32]>;

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

if (getOptLevel() != CodeGenOpt::None) {
     addPass(createWebAssemblyRegColoring());
   }
 
   // Eliminate multiple-entry loops. Do this before inserting explicit get_local
   // and set_local operators because we create a new variable that we want
   // converted into a local.
   addPass(createWebAssemblyFixIrreducibleControlFlow());
 
-  // Insert explicit get_local and set_local operators.
-  addPass(createWebAssemblyExplicitLocals());
-
   // Do various transformations for exception handling
   addPass(createWebAssemblyLateEHPrepare());
 
   // Sort the blocks of the CFG into topological order, a prerequisite for
   // BLOCK and LOOP markers.
   addPass(createWebAssemblyCFGSort());
 
   // Insert BLOCK and LOOP markers.
   addPass(createWebAssemblyCFGStackify());
 
   // Lower br_unless into br_if.
   addPass(createWebAssemblyLowerBrUnless());
 
   // Perform the very last peephole optimizations on the code.
   if (getOptLevel() != CodeGenOpt::None)
     addPass(createWebAssemblyPeephole());
 
+  // Insert explicit get_local and set_local operators.
+  addPass(createWebAssemblyExplicitLocals());
+
   // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
   addPass(createWebAssemblyRegNumbering());
 }

test/CodeGen/WebAssembly/address-offsets.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test folding constant offsets and symbols into load and store addresses under
 ; a variety of circumstances.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 @g = external global [0 x i32], align 4

test/CodeGen/WebAssembly/byval.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs -fast-isel | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -verify-machineinstrs -fast-isel | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 %SmallStruct = type { i32 }
 %OddStruct = type { i32, i8, i32 }
 %AlignedStruct = type { double, double }
 %BigStruct = type { double, double, double, double, double, double, double, double, double, double, double, i8, i8, i8 }

test/CodeGen/WebAssembly/call.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-temporary-workarounds=false | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 -wasm-temporary-workarounds=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -wasm-temporary-workarounds=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -fast-isel -fast-isel-abort=1 -wasm-temporary-workarounds=false | FileCheck %s
 
 ; Test that basic call operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i32 @i32_nullary()
 declare i32 @i32_unary(i32)

test/CodeGen/WebAssembly/cfg-stackify.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -tail-dup-placement=0 -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck -check-prefix=OPT %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -disable-block-placement -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -tail-dup-placement=0 -verify-machineinstrs -fast-isel=false -machine-sink-split-probability-threshold=0 -cgp-freq-ratio-to-skip-merge=1000 | FileCheck -check-prefix=OPT %s
 
 ; Test the CFG stackifier pass.
 
 ; Explicitly disable fast-isel, since it gets implicitly enabled in the
 ; optnone test.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"

test/CodeGen/WebAssembly/cfi.ll

-; RUN: opt -S -lowertypetests < %s | llc -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: opt -S -lowertypetests < %s | llc -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Tests that we correctly assign indexes for control flow integrity.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 @0 = private unnamed_addr constant [2 x void (...)*] [void (...)* bitcast (void ()* @f to void (...)*), void (...)* bitcast (void ()* @g to void (...)*)], align 16
 

test/CodeGen/WebAssembly/comparisons_f32.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that basic 32-bit floating-point comparison operations assemble as
 ; expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: ord_f32:

test/CodeGen/WebAssembly/comparisons_f64.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that basic 64-bit floating-point comparison operations assemble as
 ; expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: ord_f64:

test/CodeGen/WebAssembly/comparisons_i32.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that basic 32-bit integer comparison operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: eq_i32:
 ; CHECK-NEXT: .param i32, i32{{$}}

test/CodeGen/WebAssembly/comparisons_i64.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that basic 64-bit integer comparison operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: eq_i64:
 ; CHECK-NEXT: .param i64, i64{{$}}

test/CodeGen/WebAssembly/conv-trap.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-nontrapping-fptoint | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-nontrapping-fptoint | FileCheck %s
 
 ; Test that basic conversion operations assemble as expected using
 ; the trapping opcodes and explicit code to suppress the trapping.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: i32_trunc_s_f32:

test/CodeGen/WebAssembly/conv.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+nontrapping-fptoint | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+nontrapping-fptoint | FileCheck %s
 
 ; Test that basic conversion operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: i32_wrap_i64:
 ; CHECK-NEXT: .param i64{{$}}

test/CodeGen/WebAssembly/copysign-casts.ll

-; RUN: llc < %s -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; DAGCombiner oddly folds casts into the rhs of copysign. Test that they get
 ; unfolded.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare double @copysign(double, double) nounwind readnone

test/CodeGen/WebAssembly/divrem-constant.ll

-; RUN: llc < %s -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that integer div and rem by constant are optimized appropriately.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: test_udiv_2:
 ; CHECK: i32.shr_u

test/CodeGen/WebAssembly/exception.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -exception-model=wasm | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -exception-model=wasm | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 %struct.Cleanup = type { i8 }
 
 @_ZTIi = external constant i8*
 

test/CodeGen/WebAssembly/explicit-locals.mir

-# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass wasm-explicit-locals %s -o - | FileCheck %s
+# RUN: llc -mtriple=wasm32-unknown-unknown -run-pass wasm-explicit-locals -wasm-explicit-locals-codegen-test-mode %s -o - | FileCheck %s
 
 # When a drop instruction is inserted to drop a dead register operand, the
 # original operand should be marked not dead anymore because it is now used by
 # the new drop instruction. And the operand to the new drop instruction should
 # be marked killed instead.
 ---
 name: drop_test
 liveins:

test/CodeGen/WebAssembly/f16.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -fast-isel | FileCheck %s
 
 ; Test that f16 is expanded.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: demote:
 ; CHECK-NEXT: .param    f32{{$}}

test/CodeGen/WebAssembly/f32.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that basic 32-bit floating-point operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare float @llvm.fabs.f32(float)
 declare float @llvm.copysign.f32(float, float)

test/CodeGen/WebAssembly/f64.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that basic 64-bit floating-point operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare double @llvm.fabs.f64(double)
 declare double @llvm.copysign.f64(double, double)

test/CodeGen/WebAssembly/fast-isel-br-i1.ll

-; RUN: llc < %s -fast-isel -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -fast-isel -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Fast-isel uses a 32-bit xor with -1 to negate i1 values, because it doesn't
 ; make any guarantees about the contents of the high bits of a register holding
 ; an i1 value. Test that when we do a `br_if` or `br_unless` with what what an
 ; i1 value in LLVM IR, that we only test the low bit.

test/CodeGen/WebAssembly/fast-isel-i24.ll

-; RUN: llc < %s -O0
+; RUN: llc < %s -O0 -wasm-explicit-locals-codegen-test-mode
 ; PR36564
 ; PR37546
 
 ; Test that fast-isel properly copes with i24 arguments and return types.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 

test/CodeGen/WebAssembly/fast-isel-i256.ll

-; RUN: llc < %s -O0
+; RUN: llc < %s -O0 -wasm-explicit-locals-codegen-test-mode
 ; PR36564
 ; PR37546
 
 ; Test that fast-isel properly copes with i256 arguments and return types.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 

test/CodeGen/WebAssembly/fast-isel-noreg.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode -fast-isel -verify-machineinstrs | FileCheck %s
 
 ; Test that FastISel does not generate instructions with NoReg
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK: i32.const $push0=, 0
 define hidden i32 @a() #0 {

test/CodeGen/WebAssembly/fast-isel.ll

 ; RUN: llc < %s -asm-verbose=false \
 ; RUN:   -fast-isel -fast-isel-abort=1 -verify-machineinstrs \
-; RUN:   -disable-wasm-explicit-locals \
+; RUN:   -wasm-register-codegen-test-mode \
 ; RUN:   | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; This tests very minimal fast-isel functionality.
 
 ; CHECK-LABEL: immediate_f32:

test/CodeGen/WebAssembly/frem.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that the frem instruction works.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: frem32:
 ; CHECK-NEXT: .param f32, f32{{$}}

test/CodeGen/WebAssembly/func.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that basic functions assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: f0:
 ; CHECK: return{{$}}

test/CodeGen/WebAssembly/function-bitcasts-varargs.ll

-; RUN: llc < %s -asm-verbose=false -wasm-temporary-workarounds=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-temporary-workarounds=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that function pointer casts casting away varargs are replaced with
 ; wrappers.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 define void @callWithArgs() {

test/CodeGen/WebAssembly/function-bitcasts.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals -enable-emscripten-cxx-exceptions -wasm-temporary-workarounds=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-register-codegen-test-mode -enable-emscripten-cxx-exceptions -wasm-temporary-workarounds=false | FileCheck %s
 
 ; Test that function pointer casts are replaced with wrappers.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare void @has_i32_arg(i32)
 declare i32 @has_i32_ret()

test/CodeGen/WebAssembly/global.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that globals assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-NOT: llvm.used
 ; CHECK-NOT: llvm.metadata

test/CodeGen/WebAssembly/i128.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that basic 128-bit integer operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i128 @llvm.ctlz.i128(i128, i1)
 declare i128 @llvm.cttz.i128(i128, i1)

test/CodeGen/WebAssembly/i32-load-store-alignment.ll

-; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test loads and stores with custom alignment values.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Loads.
 

test/CodeGen/WebAssembly/i32.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that basic 32-bit integer operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i32 @llvm.ctlz.i32(i32, i1)
 declare i32 @llvm.cttz.i32(i32, i1)

test/CodeGen/WebAssembly/i64-load-store-alignment.ll

-; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -mattr=+atomics -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test loads and stores with custom alignment values.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Loads.
 

test/CodeGen/WebAssembly/i64.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that basic 64-bit integer operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i64 @llvm.ctlz.i64(i64, i1)
 declare i64 @llvm.cttz.i64(i64, i1)

test/CodeGen/WebAssembly/ident.ll

-; RUN: llc < %s -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test llvm.ident.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK: .ident "hello world"
 
 !llvm.ident = !{!0}
 
 !0 = !{!"hello world"}

test/CodeGen/WebAssembly/immediates.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that basic immediates assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: zero_i32:
 ; CHECK-NEXT: .result i32{{$}}

test/CodeGen/WebAssembly/implicit-def.ll

-; RUN: llc -o - %s -asm-verbose=false | FileCheck %s
+; RUN: llc -o - %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Test that stackified IMPLICIT_DEF instructions are converted into
 ; CONST_I32 to provide an explicit push.
 
 ; CHECK:      br_if 2,
 ; CHECK:      i32.const $push[[L0:[0-9]+]]=, 0{{$}}

test/CodeGen/WebAssembly/import-module.ll

-; RUN: llc < %s -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 define void @test() {
   call void @foo()
   call void @plain()
   ret void

test/CodeGen/WebAssembly/indirect-import.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -verify-machineinstrs -fast-isel | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -verify-machineinstrs -fast-isel | FileCheck %s
 
 ; ModuleID = 'test/dot_s/indirect-import.c'
 source_filename = "test/dot_s/indirect-import.c"
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32"
 
 %struct.big = type { float, double, i32 }
 

test/CodeGen/WebAssembly/inline-asm-m.ll

-; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -no-integrated-as
+; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -no-integrated-as
 
 ; Test basic inline assembly "m" operands, which are unsupported. Pass
 ; -no-integrated-as since these aren't actually valid assembly syntax.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 define void @bar(i32* %r, i32* %s) {
 entry:
   tail call void asm sideeffect "# $0 = bbb($1)", "=*m,*m"(i32* %s, i32* %r) #0, !srcloc !1
   ret void
 }

test/CodeGen/WebAssembly/inline-asm.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -no-integrated-as | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -no-integrated-as | FileCheck %s
 
 ; Test basic inline assembly. Pass -no-integrated-as since these aren't
 ; actually valid assembly syntax.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: foo:

test/CodeGen/WebAssembly/irreducible-cfg.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-block-placement -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-block-placement -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test irreducible CFG handling.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; A simple loop with two entries.
 

test/CodeGen/WebAssembly/legalize.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test various types and operators that need to be legalized.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: shl_i3:
 ; CHECK: i32.const   $push0=, 7{{$}}

test/CodeGen/WebAssembly/libcalls.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test a subset of compiler-rt/libm libcalls expected to be emitted by the wasm backend
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare fp128 @llvm.sqrt.f128(fp128)
 declare fp128 @llvm.floor.f128(fp128)

test/CodeGen/WebAssembly/load-ext-atomic.ll

-; RUN: llc < %s -mattr=+atomics,+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -mattr=+atomics,+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that extending loads are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: sext_i8_i32:
 ; CHECK: i32.atomic.load8_u $push0=, 0($0){{$}}

test/CodeGen/WebAssembly/load-ext.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that extending loads are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: sext_i8_i32:
 ; CHECK: i32.load8_s $push0=, 0($0){{$}}

test/CodeGen/WebAssembly/load-store-i1.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that i1 extending loads and truncating stores are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: load_u_i1_i32:
 ; CHECK:      i32.load8_u $push[[NUM0:[0-9]+]]=, 0($0){{$}}

test/CodeGen/WebAssembly/load.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that basic loads are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: ldi32:
 ; CHECK-NEXT: .param i32{{$}}

test/CodeGen/WebAssembly/lower-em-ehsjlj-options.ll

 ; NONE-LABEL: type setjmp_longjmp,@function
 entry:
   %buf = alloca [1 x %struct.__jmp_buf_tag], align 16
   %arraydecay = getelementptr inbounds [1 x %struct.__jmp_buf_tag], [1 x %struct.__jmp_buf_tag]* %buf, i32 0, i32 0
   %call = call i32 @setjmp(%struct.__jmp_buf_tag* %arraydecay) #0
   %arraydecay1 = getelementptr inbounds [1 x %struct.__jmp_buf_tag], [1 x %struct.__jmp_buf_tag]* %buf, i32 0, i32 0
   call void @longjmp(%struct.__jmp_buf_tag* %arraydecay1, i32 1) #1
   unreachable
-; SJLJ: i32.call ${{[a-zA-Z0-9]+}}=, saveSetjmp@FUNCTION
-; SJLJ: i32.call ${{[a-zA-Z0-9]+}}=, testSetjmp@FUNCTION
-; NONE: i32.call ${{[a-zA-Z0-9]+}}=, setjmp@FUNCTION
+; SJLJ: i32.call saveSetjmp@FUNCTION
+; SJLJ: i32.call testSetjmp@FUNCTION
+; NONE: i32.call setjmp@FUNCTION
 ; NONE: call longjmp@FUNCTION
 }
 
 declare void @foo()
 declare i32 @__gxx_personality_v0(...)
 declare i8* @__cxa_begin_catch(i8*)
 declare void @__cxa_end_catch()
 ; Function Attrs: returns_twice

test/CodeGen/WebAssembly/lower-global-dtors.ll

-; RUN: llc < %s -asm-verbose=false | FileCheck --check-prefix=CHECK --check-prefix=FINI --check-prefix=NULL %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck --check-prefix=CHECK --check-prefix=FINI --check-prefix=NULL %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Test that @llvm.global_dtors is properly lowered into @llvm.global_ctors,
 ; grouping dtor calls by priority and associated symbol.
 
 declare void @orig_ctor()

test/CodeGen/WebAssembly/mem-intrinsics.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -tail-dup-placement=0 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -tail-dup-placement=0 | FileCheck %s
 
 ; Test memcpy, memmove, and memset intrinsics.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1)
 declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i1)

test/CodeGen/WebAssembly/memory-addr32.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that basic memory operations assemble as expected with 32-bit addresses.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i32 @llvm.wasm.memory.size.i32(i32) nounwind readonly
 declare i32 @llvm.wasm.memory.grow.i32(i32, i32) nounwind

test/CodeGen/WebAssembly/muloti4.ll

-; RUN: llc -asm-verbose=false < %s | FileCheck %s
+; RUN: llc -asm-verbose=false < %s -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that 128-bit smul.with.overflow assembles as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 define i128 @call_muloti4(i128 %a, i128 %b) nounwind {
 entry:

test/CodeGen/WebAssembly/negative-base-reg.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 @args = hidden local_unnamed_addr global [32 x i32] zeroinitializer, align 16
 
 ; Function Attrs: norecurse nounwind
 define hidden i32 @main() local_unnamed_addr #0 {

test/CodeGen/WebAssembly/offset-atomics.ll

 ; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+atomics,+sign-ext | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+atomics,+sign-ext | FileCheck %s
 
 ; Test that atomic loads are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Basic load.
 

test/CodeGen/WebAssembly/offset-fastisel.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals -fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-register-codegen-test-mode -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; TODO: Merge this with offset.ll when fast-isel matches better.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: store_i8_with_variable_gep_offset:
 ; CHECK: i32.add    $push[[L0:[0-9]+]]=, $0, $1{{$}}

test/CodeGen/WebAssembly/offset-folding.ll

-; RUN: llc < %s -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that constant offsets can be folded into global addresses.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 @x = external global [0 x i32]
 @y = global [50 x i32] zeroinitializer

test/CodeGen/WebAssembly/offset.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test constant load and store address offsets.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; With an nuw add, we can fold an offset.
 

test/CodeGen/WebAssembly/phi.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -verify-machineinstrs | FileCheck %s
 
 ; Test that phis are lowered.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Basic phi triangle.
 

test/CodeGen/WebAssembly/reg-stackify-stack.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -verify-machineinstrs | FileCheck %s
 
 ; Test the register stackifier pass.
 
+; NOTE: These are the same tests as in reg-stackify.ll, but using stack based
+; output instead of register output. We use register ouput for tests since it
+; is more informative on what the backend actually does, but in the long run
+; we'd like most test to be using the stack format or MIR.
+
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; No because of pointer aliasing.
 
 ; CHECK-LABEL: no0:
-; CHECK: return $1{{$}}
+; CHECK: return
 define i32 @no0(i32* %p, i32* %q) {
   %t = load i32, i32* %q
   store i32 0, i32* %p
   ret i32 %t
 }
 
 ; No because of side effects.
 
 ; CHECK-LABEL: no1:
-; CHECK: return $1{{$}}
+; CHECK: return
 define i32 @no1(i32* %p, i32* dereferenceable(4) %q) {
   %t = load volatile i32, i32* %q, !invariant.load !0
   store volatile i32 0, i32* %p
   ret i32 %t
 }
 
 ; Yes because of invariant load and no side effects.
 
 ; CHECK-LABEL: yes0:
-; CHECK: return $pop{{[0-9]+}}{{$}}
+; CHECK: return{{$}}
 define i32 @yes0(i32* %p, i32* dereferenceable(4) %q) {
   %t = load i32, i32* %q, !invariant.load !0
   store i32 0, i32* %p
   ret i32 %t
 }
 
 ; Yes because of no intervening side effects.
 
 ; CHECK-LABEL: yes1:
-; CHECK: return $pop0{{$}}
+; CHECK: return{{$}}
 define i32 @yes1(i32* %q) {
   %t = load volatile i32, i32* %q
   ret i32 %t
 }
 
 ; Yes because undefined behavior can be sunk past a store.
 
 ; CHECK-LABEL: sink_trap:
-; CHECK: return $pop{{[0-9]+}}{{$}}
+; CHECK: return{{$}}
 define i32 @sink_trap(i32 %x, i32 %y, i32* %p) {
   %t = sdiv i32 %x, %y
   store volatile i32 0, i32* %p
   ret i32 %t
 }
 
 ; Yes because the call is readnone.
 
 ; CHECK-LABEL: sink_readnone_call:
-; CHECK: return $pop0{{$}}
+; CHECK: return{{$}}
 declare i32 @readnone_callee() readnone nounwind
 define i32 @sink_readnone_call(i32 %x, i32 %y, i32* %p) {
   %t = call i32 @readnone_callee()
   store volatile i32 0, i32* %p
   ret i32 %t
 }
 
 ; No because the call is readonly and there's an intervening store.
 
 ; CHECK-LABEL: no_sink_readonly_call:
-; CHECK: return ${{[0-9]+}}{{$}}
+; CHECK: return{{$}}
 declare i32 @readonly_callee() readonly nounwind
 define i32 @no_sink_readonly_call(i32 %x, i32 %y, i32* %p) {
   %t = call i32 @readonly_callee()
   store i32 0, i32* %p
   ret i32 %t
 }
 
 ; Don't schedule stack uses into the stack. To reduce register pressure, the
 ; scheduler might be tempted to move the definition of $2 down. However, this
 ; would risk getting incorrect liveness if the instructions are later
 ; rearranged to make the stack contiguous.
 
 ; CHECK-LABEL: stack_uses:
 ; CHECK: .param i32, i32, i32, i32{{$}}
 ; CHECK-NEXT: .result i32{{$}}
-; CHECK-NEXT: block   {{$}}
-; CHECK-NEXT: i32.const   $push[[L13:[0-9]+]]=, 1{{$}}
-; CHECK-NEXT: i32.lt_s    $push[[L0:[0-9]+]]=, $0, $pop[[L13]]{{$}}
-; CHECK-NEXT: i32.const   $push[[L1:[0-9]+]]=, 2{{$}}
-; CHECK-NEXT: i32.lt_s    $push[[L2:[0-9]+]]=, $1, $pop[[L1]]{{$}}
-; CHECK-NEXT: i32.xor     $push[[L5:[0-9]+]]=, $pop[[L0]], $pop[[L2]]{{$}}
-; CHECK-NEXT: i32.const   $push[[L12:[0-9]+]]=, 1{{$}}
-; CHECK-NEXT: i32.lt_s    $push[[L3:[0-9]+]]=, $2, $pop[[L12]]{{$}}
-; CHECK-NEXT: i32.const   $push[[L11:[0-9]+]]=, 2{{$}}
-; CHECK-NEXT: i32.lt_s    $push[[L4:[0-9]+]]=, $3, $pop[[L11]]{{$}}
-; CHECK-NEXT: i32.xor     $push[[L6:[0-9]+]]=, $pop[[L3]], $pop[[L4]]{{$}}
-; CHECK-NEXT: i32.xor     $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
-; CHECK-NEXT: i32.const   $push10=, 1{{$}}
-; CHECK-NEXT: i32.ne      $push8=, $pop7, $pop10{{$}}
-; CHECK-NEXT: br_if       0, $pop8{{$}}
-; CHECK-NEXT: i32.const   $push9=, 0{{$}}
-; CHECK-NEXT: return      $pop9{{$}}
+; CHECK-NEXT: block {{$}}
+; CHECK-NEXT: get_local 0{{$}}
+; CHECK-NEXT: i32.const   1{{$}}
+; CHECK-NEXT: i32.lt_s
+; CHECK-NEXT: get_local 1{{$}}
+; CHECK-NEXT: i32.const   2{{$}}
+; CHECK-NEXT: i32.lt_s
+; CHECK-NEXT: i32.xor {{$}}
+; CHECK-NEXT: get_local 2{{$}}
+; CHECK-NEXT: i32.const   1{{$}}
+; CHECK-NEXT: i32.lt_s
+; CHECK-NEXT: get_local 3{{$}}
+; CHECK-NEXT: i32.const   2{{$}}
+; CHECK-NEXT: i32.lt_s
+; CHECK-NEXT: i32.xor {{$}}
+; CHECK-NEXT: i32.xor {{$}}
+; CHECK-NEXT: i32.const   1{{$}}
+; CHECK-NEXT: i32.ne {{$}}
+; CHECK-NEXT: br_if       0{{$}}
+; CHECK-NEXT: i32.const   0{{$}}
+; CHECK-NEXT: return{{$}}
 ; CHECK-NEXT: .LBB7_2:
 ; CHECK-NEXT: end_block{{$}}
-; CHECK-NEXT: i32.const   $push14=, 1{{$}}
-; CHECK-NEXT: return      $pop14{{$}}
+; CHECK-NEXT: i32.const   1{{$}}
+; CHECK-NEXT: return{{$}}
 define i32 @stack_uses(i32 %x, i32 %y, i32 %z, i32 %w) {
 entry:
   %c = icmp sle i32 %x, 0
   %d = icmp sle i32 %y, 1
   %e = icmp sle i32 %z, 0
   %f = icmp sle i32 %w, 1
   %g = xor i1 %c, %d
   %h = xor i1 %e, %f
   %i = xor i1 %g, %h
   br i1 %i, label %true, label %false
 true:
   ret i32 0
 false:
   ret i32 1
 }
 
 ; Test an interesting case where the load has multiple uses and cannot
 ; be trivially stackified. However, it can be stackified with a tee_local.
 
 ; CHECK-LABEL: multiple_uses:
 ; CHECK: .param       i32, i32, i32{{$}}
-; CHECK-NEXT: block   {{$}}
-; CHECK-NEXT: i32.load    $push[[NUM0:[0-9]+]]=, 0($2){{$}}
-; CHECK-NEXT: tee_local   $push[[NUM1:[0-9]+]]=, $3=, $pop[[NUM0]]{{$}}
-; CHECK-NEXT: i32.ge_u    $push[[NUM2:[0-9]+]]=, $pop[[NUM1]], $1{{$}}
-; CHECK-NEXT: br_if       0, $pop[[NUM2]]{{$}}
-; CHECK-NEXT: i32.lt_u    $push[[NUM3:[0-9]+]]=, $3, $0{{$}}
-; CHECK-NEXT: br_if       0, $pop[[NUM3]]{{$}}
-; CHECK-NEXT: i32.store   0($2), $3{{$}}
+; CHECK: .local i32{{$}}
+; CHECK-NEXT: block {{$}}
+; CHECK-NEXT: get_local   2{{$}}
+; CHECK-NEXT: i32.load    0{{$}}
+; CHECK-NEXT: tee_local   3{{$}}
+; CHECK-NEXT: get_local   1{{$}}
+; CHECK-NEXT: i32.ge_u
+; CHECK-NEXT: br_if       0{{$}}
+; CHECK-NEXT: get_local   3{{$}}
+; CHECK-NEXT: get_local   0{{$}}
+; CHECK-NEXT: i32.lt_u
+; CHECK-NEXT: br_if       0{{$}}
+; CHECK-NEXT: get_local   2{{$}}
+; CHECK-NEXT: get_local   3{{$}}
+; CHECK-NEXT: i32.store   0{{$}}
 ; CHECK-NEXT: .LBB8_3:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @multiple_uses(i32* %arg0, i32* %arg1, i32* %arg2) nounwind {
 bb:
   br label %loop
 
 loop:

 
 ; Div instructions have side effects and can't be reordered, but this entire
 ; function should still be able to be stackified because it's already in
 ; tree order.
 
 ; CHECK-LABEL: div_tree:
 ; CHECK: .param i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32{{$}}
 ; CHECK-NEXT: .result     i32{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L0:[0-9]+]]=, $0, $1{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L1:[0-9]+]]=, $2, $3{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L3:[0-9]+]]=, $4, $5{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L4:[0-9]+]]=, $6, $7{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L5:[0-9]+]]=, $pop[[L3]], $pop[[L4]]{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L6:[0-9]+]]=, $pop[[L2]], $pop[[L5]]{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L7:[0-9]+]]=, $8, $9{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L8:[0-9]+]]=, $10, $11{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L10:[0-9]+]]=, $12, $13{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L11:[0-9]+]]=, $14, $15{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L12:[0-9]+]]=, $pop[[L10]], $pop[[L11]]{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L13:[0-9]+]]=, $pop[[L9]], $pop[[L12]]{{$}}
-; CHECK-NEXT: i32.div_s   $push[[L14:[0-9]+]]=, $pop[[L6]], $pop[[L13]]{{$}}
-; CHECK-NEXT: return      $pop[[L14]]{{$}}
+; CHECK-NEXT: get_local 0{{$}}
+; CHECK-NEXT: get_local 1{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: get_local 2{{$}}
+; CHECK-NEXT: get_local 3{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: get_local 4{{$}}
+; CHECK-NEXT: get_local 5{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: get_local 6{{$}}
+; CHECK-NEXT: get_local 7{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: get_local 8{{$}}
+; CHECK-NEXT: get_local 9{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: get_local 10{{$}}
+; CHECK-NEXT: get_local 11{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: get_local 12{{$}}
+; CHECK-NEXT: get_local 13{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: get_local 14{{$}}
+; CHECK-NEXT: get_local 15{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: i32.div_s{{$}}
+; CHECK-NEXT: return{{$}}
 define i32 @div_tree(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) {
 entry:
   %div = sdiv i32 %a, %b
   %div1 = sdiv i32 %c, %d
   %div2 = sdiv i32 %div, %div1
   %div3 = sdiv i32 %e, %f
   %div4 = sdiv i32 %g, %h
   %div5 = sdiv i32 %div3, %div4
   %div6 = sdiv i32 %div2, %div5
   %div7 = sdiv i32 %i, %j
   %div8 = sdiv i32 %k, %l
   %div9 = sdiv i32 %div7, %div8
   %div10 = sdiv i32 %m, %n
   %div11 = sdiv i32 %o, %p
   %div12 = sdiv i32 %div10, %div11
   %div13 = sdiv i32 %div9, %div12
   %div14 = sdiv i32 %div6, %div13
   ret i32 %div14
 }
 
 ; A simple multiple-use case.
 
 ; CHECK-LABEL: simple_multiple_use:
 ; CHECK:  .param      i32, i32{{$}}
-; CHECK-NEXT:  i32.mul     $push[[NUM0:[0-9]+]]=, $1, $0{{$}}
-; CHECK-NEXT:  tee_local   $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}}
-; CHECK-NEXT:  call        use_a@FUNCTION, $pop[[NUM1]]{{$}}
-; CHECK-NEXT:  call        use_b@FUNCTION, $[[NUM2]]{{$}}
+; CHECK-NEXT:  get_local 1{{$}}
+; CHECK-NEXT:  get_local 0{{$}}
+; CHECK-NEXT:  i32.mul
+; CHECK-NEXT:  tee_local   1{{$}}
+; CHECK-NEXT:  call        use_a@FUNCTION{{$}}
+; CHECK-NEXT:  get_local   1{{$}}
+; CHECK-NEXT:  call        use_b@FUNCTION{{$}}
 ; CHECK-NEXT:  return{{$}}
 declare void @use_a(i32)
 declare void @use_b(i32)
 define void @simple_multiple_use(i32 %x, i32 %y) {
   %mul = mul i32 %y, %x
   call void @use_a(i32 %mul)
   call void @use_b(i32 %mul)
   ret void
 }
 
 ; Multiple uses of the same value in one instruction.
 
 ; CHECK-LABEL: multiple_uses_in_same_insn:
 ; CHECK:  .param      i32, i32{{$}}
-; CHECK-NEXT:  i32.mul     $push[[NUM0:[0-9]+]]=, $1, $0{{$}}
-; CHECK-NEXT:  tee_local   $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}}
-; CHECK-NEXT:  call        use_2@FUNCTION, $pop[[NUM1]], $[[NUM2]]{{$}}
+; CHECK-NEXT:  get_local 1{{$}}
+; CHECK-NEXT:  get_local 0{{$}}
+; CHECK-NEXT:  i32.mul
+; CHECK-NEXT:  tee_local   1{{$}}
+; CHECK-NEXT:  get_local   1{{$}}
+; CHECK-NEXT:  call        use_2@FUNCTION{{$}}
 ; CHECK-NEXT:  return{{$}}
 declare void @use_2(i32, i32)
 define void @multiple_uses_in_same_insn(i32 %x, i32 %y) {
   %mul = mul i32 %y, %x
   call void @use_2(i32 %mul, i32 %mul)
   ret void
 }
 
 ; Commute operands to achieve better stackifying.
 
 ; CHECK-LABEL: commute:
 ; CHECK-NOT: param
 ; CHECK:  .result     i32{{$}}
-; CHECK-NEXT:  i32.call    $push0=, red@FUNCTION{{$}}
-; CHECK-NEXT:  i32.call    $push1=, green@FUNCTION{{$}}
-; CHECK-NEXT:  i32.add     $push2=, $pop0, $pop1{{$}}
-; CHECK-NEXT:  i32.call    $push3=, blue@FUNCTION{{$}}
-; CHECK-NEXT:  i32.add     $push4=, $pop2, $pop3{{$}}
-; CHECK-NEXT:  return      $pop4{{$}}
+; CHECK-NEXT:  i32.call    red@FUNCTION{{$}}
+; CHECK-NEXT:  i32.call    green@FUNCTION{{$}}
+; CHECK-NEXT:  i32.add {{$}}
+; CHECK-NEXT:  i32.call    blue@FUNCTION{{$}}
+; CHECK-NEXT:  i32.add {{$}}
+; CHECK-NEXT:  return{{$}}
 declare i32 @red()
 declare i32 @green()
 declare i32 @blue()
 define i32 @commute() {
   %call = call i32 @red()
   %call1 = call i32 @green()
   %add = add i32 %call1, %call
   %call2 = call i32 @blue()
   %add3 = add i32 %add, %call2
   ret i32 %add3
 }
 
 ; Don't stackify a register when it would move a the def of the register past
 ; an implicit get_local for the register.
 
 ; CHECK-LABEL: no_stackify_past_use:
-; CHECK:      i32.call        $1=, callee@FUNCTION, $0
-; CHECK-NEXT: i32.const       $push0=, 1
-; CHECK-NEXT: i32.add         $push1=, $0, $pop0
-; CHECK-NEXT: i32.call        $push2=, callee@FUNCTION, $pop1
-; CHECK-NEXT: i32.sub         $push3=, $pop2, $1
-; CHECK-NEXT: i32.div_s       $push4=, $pop3, $1
-; CHECK-NEXT: return          $pop4
+; CHECK:      get_local       0{{$}}
+; CHECK-NEXT: i32.call        callee@FUNCTION
+; CHECK-NEXT: set_local       1{{$}}
+; CHECK-NEXT: get_local       0{{$}}
+; CHECK-NEXT: i32.const       1
+; CHECK-NEXT: i32.add
+; CHECK-NEXT: i32.call        callee@FUNCTION
+; CHECK-NEXT: get_local       1{{$}}
+; CHECK-NEXT: i32.sub
+; CHECK-NEXT: get_local       1{{$}}
+; CHECK-NEXT: i32.div_s
+; CHECK-NEXT: return
 declare i32 @callee(i32)
 define i32 @no_stackify_past_use(i32 %arg) {
   %tmp1 = call i32 @callee(i32 %arg)
   %tmp2 = add i32 %arg, 1
   %tmp3 = call i32 @callee(i32 %tmp2)
   %tmp5 = sub i32 %tmp3, %tmp1
   %tmp6 = sdiv i32 %tmp5, %tmp1
   ret i32 %tmp6
 }
 
 ; This is the same as no_stackify_past_use, except using a commutative operator,
 ; so we can reorder the operands and stackify.
 
 ; CHECK-LABEL: commute_to_fix_ordering:
-; CHECK: i32.call        $push[[L0:.+]]=, callee@FUNCTION, $0
-; CHECK: tee_local       $push[[L1:.+]]=, $1=, $pop[[L0]]
-; CHECK: i32.const       $push0=, 1
-; CHECK: i32.add         $push1=, $0, $pop0
-; CHECK: i32.call        $push2=, callee@FUNCTION, $pop1
-; CHECK: i32.add         $push3=, $1, $pop2
-; CHECK: i32.mul         $push4=, $pop[[L1]], $pop3
-; CHECK: return          $pop4
+; CHECK: get_local       0{{$}}
+; CHECK: i32.call        callee@FUNCTION
+; CHECK: tee_local       1
+; CHECK: get_local       1{{$}}
+; CHECK: get_local       0{{$}}
+; CHECK: i32.const       1
+; CHECK: i32.add
+; CHECK: i32.call        callee@FUNCTION
+; CHECK: i32.add
+; CHECK: i32.mul
+; CHECK: return
 define i32 @commute_to_fix_ordering(i32 %arg) {
   %tmp1 = call i32 @callee(i32 %arg)
   %tmp2 = add i32 %arg, 1
   %tmp3 = call i32 @callee(i32 %tmp2)
   %tmp5 = add i32 %tmp3, %tmp1
   %tmp6 = mul i32 %tmp5, %tmp1
   ret i32 %tmp6
 }
 
 ; Stackify individual defs of virtual registers with multiple defs.
 
 ; CHECK-LABEL: multiple_defs:
-; CHECK:        f64.add         $push[[NUM0:[0-9]+]]=, ${{[0-9]+}}, $pop{{[0-9]+}}{{$}}
-; CHECK-NEXT:   tee_local       $push[[NUM1:[0-9]+]]=, $[[NUM2:[0-9]+]]=, $pop[[NUM0]]{{$}}
-; CHECK-NEXT:   f64.select      $push{{[0-9]+}}=, $pop{{[0-9]+}}, $pop[[NUM1]], ${{[0-9]+}}{{$}}
-; CHECK:        $[[NUM2]]=,
+; CHECK:        f64.add
+; CHECK:        tee_local
+; CHECK:        f64.select
 define void @multiple_defs(i32 %arg, i32 %arg1, i1 %arg2, i1 %arg3, i1 %arg4) {
 bb:
   br label %bb5
 
 bb5:                                              ; preds = %bb21, %bb
   %tmp = phi double [ 0.000000e+00, %bb ], [ %tmp22, %bb21 ]
   %tmp6 = phi double [ 0.000000e+00, %bb ], [ %tmp23, %bb21 ]
   %tmp7 = fcmp olt double %tmp6, 2.323450e+01
bb21:                                             ; preds = %bb17, %bb5
   %tmp23 = fadd double %tmp6, 1.000000e+00
   br i1 %arg4, label %exit, label %bb5
 exit:
   ret void
 }
 
 ; Don't move calls past loads
 ; CHECK-LABEL: no_stackify_call_past_load:
-; CHECK: i32.call $0=, red
-; CHECK: i32.const $push0=, 0
-; CHECK: i32.load $1=, count($pop0)
+; CHECK: i32.call red
+; CHECK: i32.const 0
+; CHECK: i32.load count
 @count = hidden global i32 0, align 4
 define i32 @no_stackify_call_past_load() {
   %a = call i32 @red()
   %b = load i32, i32* @count, align 4
   call i32 @callee(i32 %a)
   ret i32 %b
   ; use of a
 }
 
 ; Don't move stores past loads if there may be aliasing
 ; CHECK-LABEL: no_stackify_store_past_load
-; CHECK: i32.store 0($1), $0
-; CHECK: i32.load {{.*}}, 0($2)
-; CHECK: i32.call {{.*}}, callee@FUNCTION, $0{{$}}
+; CHECK: i32.store 0
+; CHECK: i32.load 0
+; CHECK: i32.call callee@FUNCTION{{$}}
 define i32 @no_stackify_store_past_load(i32 %a, i32* %p1, i32* %p2) {
   store i32 %a, i32* %p1
   %b = load i32, i32* %p2, align 4
   call i32 @callee(i32 %a)
   ret i32 %b
 }
 
 ; Can still stackify past invariant loads.
 ; CHECK-LABEL: store_past_invar_load
-; CHECK: i32.store 0($1), $0
-; CHECK: i32.call {{.*}}, callee@FUNCTION, $0
-; CHECK: i32.load $push{{.*}}, 0($2)
-; CHECK: return $pop
+; CHECK: i32.store 0
+; CHECK: i32.call callee@FUNCTION
+; CHECK: i32.load 0
+; CHECK: return
 define i32 @store_past_invar_load(i32 %a, i32* %p1, i32* dereferenceable(4) %p2) {
   store i32 %a, i32* %p1
   %b = load i32, i32* %p2, !invariant.load !0
   call i32 @callee(i32 %a)
   ret i32 %b
 }
 
 ; CHECK-LABEL: ignore_dbg_value:
 ; CHECK-NEXT: .Lfunc_begin
 ; CHECK-NEXT: unreachable
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
 define void @ignore_dbg_value() {
   call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !9), !dbg !10
   unreachable
 }
 
 ; Don't stackify an expression that might use the stack into a return, since we
 ; might insert a prologue before the return.
 
 ; CHECK-LABEL: no_stackify_past_epilogue:
-; CHECK: return ${{[0-9]+}}{{$}}
+; CHECK: return{{$}}
 declare i32 @use_memory(i32*)
 define i32 @no_stackify_past_epilogue() {
   %x = alloca i32
   %call = call i32 @use_memory(i32* %x)
   ret i32 %call
 }
 
 ; Stackify a loop induction variable into a loop comparison.
 
 ; CHECK-LABEL: stackify_indvar:
-; CHECK:             i32.const   $push[[L5:.+]]=, 1{{$}}
-; CHECK-NEXT:        i32.add     $push[[L4:.+]]=, $[[R0:.+]], $pop[[L5]]{{$}}
-; CHECK-NEXT:        tee_local   $push[[L3:.+]]=, $[[R0]]=, $pop[[L4]]{{$}}
-; CHECK-NEXT:        i32.ne      $push[[L2:.+]]=, $0, $pop[[L3]]{{$}}
+; CHECK:             i32.const   1{{$}}
+; CHECK-NEXT:        i32.add
+; CHECK-NEXT:        tee_local   2{{$}}
+; CHECK-NEXT:        i32.ne
 define void @stackify_indvar(i32 %tmp, i32* %v) #0 {
 bb:
   br label %bb3
 
 bb3:                                              ; preds = %bb3, %bb2
   %tmp4 = phi i32 [ %tmp7, %bb3 ], [ 0, %bb ]
   %tmp5 = load volatile i32, i32* %v, align 4
   %tmp6 = add nsw i32 %tmp5, %tmp4
   store volatile i32 %tmp6, i32* %v, align 4
   %tmp7 = add nuw nsw i32 %tmp4, 1
   %tmp8 = icmp eq i32 %tmp7, %tmp
   br i1 %tmp8, label %bb10, label %bb3
 
 bb10:                                             ; preds = %bb9, %bb
   ret void
 }
 
 ; Don't stackify a call past a __stack_pointer store.
 
 ; CHECK-LABEL: stackpointer_dependency:
-; CHECK:      call {{.+}}, stackpointer_callee@FUNCTION,
-; CHECK-NEXT: set_global __stack_pointer,
+; CHECK:      call stackpointer_callee@FUNCTION
+; CHECK:      set_global __stack_pointer
 declare i32 @stackpointer_callee(i8* readnone, i8* readnone)
 declare i8* @llvm.frameaddress(i32)
 define i32 @stackpointer_dependency(i8* readnone) {
   %2 = tail call i8* @llvm.frameaddress(i32 0)
   %3 = tail call i32 @stackpointer_callee(i8* %0, i8* %2)
   ret i32 %3
 }
 
 ; Stackify a call_indirect with respect to its ordering
 
 ; CHECK-LABEL: call_indirect_stackify:
-; CHECK: i32.load  $push[[L4:.+]]=, 0($0)
-; CHECK-NEXT: tee_local $push[[L3:.+]]=, $0=, $pop[[L4]]
-; CHECK-NEXT: i32.load  $push[[L0:.+]]=, 0($0)
-; CHECK-NEXT: i32.load  $push[[L1:.+]]=, 0($pop[[L0]])
-; CHECK-NEXT: i32.call_indirect $push{{.+}}=, $pop[[L3]], $1, $pop[[L1]]
+; CHECK: i32.load  0
+; CHECK-NEXT: tee_local 0
+; CHECK:      i32.load  0
+; CHECK-NEXT: i32.load  0
+; CHECK-NEXT: i32.call_indirect
 %class.call_indirect = type { i32 (...)** }
 define i32 @call_indirect_stackify(%class.call_indirect** %objptr, i32 %arg) {
   %obj = load %class.call_indirect*, %class.call_indirect** %objptr
   %addr = bitcast %class.call_indirect* %obj to i32(%class.call_indirect*, i32)***
   %vtable = load i32(%class.call_indirect*, i32)**, i32(%class.call_indirect*, i32)*** %addr
   %vfn = getelementptr inbounds i32(%class.call_indirect*, i32)*, i32(%class.call_indirect*, i32)** %vtable, i32 0
   %f = load i32(%class.call_indirect*, i32)*, i32(%class.call_indirect*, i32)** %vfn
   %ret = call i32 %f(%class.call_indirect* %obj, i32 %arg)

test/CodeGen/WebAssembly/reg-stackify.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -verify-machineinstrs | FileCheck %s
 
 ; Test the register stackifier pass.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; No because of pointer aliasing.
 

test/CodeGen/WebAssembly/return-int32.ll

-; RUN: llc < %s -asm-verbose=false | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: return_i32:
 ; CHECK-NEXT:  .param i32{{$}}
 ; CHECK-NEXT:  .result i32{{$}}
 ; CHECK-NEXT:  get_local  $push0=, 0

 ; CHECK-NEXT: i32.const $push{{[^,]+}}=, 3{{$}}
 ; CHECK-NEXT: end_function{{$}}
 define i32 @return_i32_twice(i32 %a) {
   %b = icmp ne i32 %a, 0
   br i1 %b, label %true, label %false
 
 true:
   store i32 0, i32* null
-  ret i32 1 
+  ret i32 1
 
 false:
   store i32 2, i32* null
   ret i32 3
 }

test/CodeGen/WebAssembly/returned.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that the "returned" attribute is optimized effectively.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: _Z3foov:
 ; CHECK-NEXT: .result   i32{{$}}

test/CodeGen/WebAssembly/select.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that wasm select instruction is selected from LLVM select instruction.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: select_i32_bool:
 ; CHECK-NEXT: .param     i32, i32, i32{{$}}

test/CodeGen/WebAssembly/signext-arg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-register-codegen-test-mode | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i32 @get_int(i16 %arg)
 
 define i32 @func_1(i16 %arg1 , i32 %arg2) #0 {
 ; CHECK-LABEL: func_1:

test/CodeGen/WebAssembly/signext-inreg.ll

-; RUN: llc < %s -mattr=+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s --check-prefix=NOSIGNEXT
+; RUN: llc < %s -mattr=+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s --check-prefix=NOSIGNEXT
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: i32_extend8_s:
 ; CHECK-NEXT: .param i32{{$}}
 ; CHECK-NEXT: .result i32{{$}}
 ; CHECK-NEXT: i32.extend8_s $push[[NUM:[0-9]+]]=, $0{{$}}

test/CodeGen/WebAssembly/signext-zeroext.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test zeroext and signext ABI keywords
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: z2s_func:
 ; CHECK-NEXT: .param i32{{$}}

test/CodeGen/WebAssembly/simd-arith.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that basic SIMD128 arithmetic operations assemble as expected.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare i32 @llvm.ctlz.i32(i32, i1)
 declare i32 @llvm.cttz.i32(i32, i1)

test/CodeGen/WebAssembly/stack-alignment.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare void @somefunc(i32*)
 
 ; CHECK-LABEL: underalign:
 ; CHECK:      get_global $push[[L1:.+]]=, __stack_pointer{{$}}

test/CodeGen/WebAssembly/store-trunc-atomic.ll

-; RUN: llc < %s -mattr=+atomics,+sign-ext -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -mattr=+atomics,+sign-ext -asm-verbose=false -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that truncating stores are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: trunc_i8_i32:
 ; CHECK: i32.atomic.store8 0($0), $1{{$}}

test/CodeGen/WebAssembly/store-trunc.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Test that truncating stores are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: trunc_i8_i32:
 ; CHECK: i32.store8 0($0), $1{{$}}

test/CodeGen/WebAssembly/store.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -fast-isel -fast-isel-abort=1 | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that basic stores are assembled properly.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: sti32:
 ; CHECK-NEXT: .param i32, i32{{$}}

test/CodeGen/WebAssembly/switch.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-block-placement -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -disable-block-placement -verify-machineinstrs | FileCheck %s
 
 ; Test switch instructions. Block placement is disabled because it reorders
 ; the blocks in a way that isn't interesting here.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare void @foo0()

test/CodeGen/WebAssembly/tls.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -thread-model=single | FileCheck --check-prefix=SINGLE %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -thread-model=single | FileCheck --check-prefix=SINGLE %s
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; SINGLE-LABEL: address_of_tls:
 define i32 @address_of_tls() {
   ; SINGLE: i32.const $push0=, tls
   ; SINGLE-NEXT: return $pop0
   ret i32 ptrtoint(i32* @tls to i32)
 }
 
 ; SINGLE: .type tls,@object
 ; SINGLE-NEXT: .section .bss.tls,"",@
 ; SINGLE-NEXT: .p2align 2
 ; SINGLE-NEXT: tls:
 ; SINGLE-NEXT: .int32 0
 @tls = internal thread_local global i32 0

test/CodeGen/WebAssembly/umulo-i64.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-register-codegen-test-mode | FileCheck %s
 ; Test that UMULO works correctly on 64-bit operands.
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: _ZN4core3num21_$LT$impl$u20$u64$GT$15overflowing_mul17h07be88b4cbac028fE:
 ; CHECK:     __multi3
 ; Function Attrs: inlinehint
 define void @"_ZN4core3num21_$LT$impl$u20$u64$GT$15overflowing_mul17h07be88b4cbac028fE"(i64, i64) unnamed_addr #0 {

test/CodeGen/WebAssembly/unsupported-function-bitcasts.ll

-; RUN: llc < %s -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 ; Test that function pointer casts that require conversions are not converted
 ; to wrappers. In theory some conversions could be supported, but currently no
 ; conversions are implemented.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 

test/CodeGen/WebAssembly/unused-argument.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode | FileCheck %s
 
 ; Make sure that argument offsets are correct even if some arguments are unused.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: unused_first:
 ; CHECK-NEXT: .param i32, i32{{$}}

test/CodeGen/WebAssembly/userstack.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-explicit-locals-codegen-test-mode | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare void @ext_func(i64* %ptr)
 declare void @ext_func_i32(i32* %ptr)
 
 ; CHECK-LABEL: alloca32:

 
 ; CHECK-LABEL: dynamic_alloca:
 define void @dynamic_alloca(i32 %alloc) {
  ; CHECK: get_global $push[[L13:.+]]=, __stack_pointer{{$}}
  ; CHECK-NEXT: tee_local $push[[L12:.+]]=, [[SP:.+]], $pop[[L13]]{{$}}
  ; Target independent codegen bumps the stack pointer.
  ; CHECK: i32.sub
  ; Check that SP is written back to memory after decrement
- ; CHECK: set_global __stack_pointer, 
+ ; CHECK: set_global __stack_pointer,
  %r = alloca i32, i32 %alloc
  ; Target-independent codegen also calculates the store addr
  ; CHECK: call ext_func_i32@FUNCTION
  call void @ext_func_i32(i32* %r)
  ; CHECK: set_global __stack_pointer, $pop{{.+}}
  ret void
 }
 

test/CodeGen/WebAssembly/varargs.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -verify-machineinstrs | FileCheck %s
 
 ; Test varargs constructs.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Test va_start.
 

test/CodeGen/WebAssembly/vtable.ll

-; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s --check-prefix=TYPEINFONAME
-; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s --check-prefix=VTABLE
-; RUN: llc < %s -asm-verbose=false -disable-wasm-explicit-locals | FileCheck %s --check-prefix=TYPEINFO
+; RUN: llc < %s -asm-verbose=false -wasm-register-codegen-test-mode | FileCheck %s --check-prefix=TYPEINFONAME
+; RUN: llc < %s -asm-verbose=false -wasm-register-codegen-test-mode | FileCheck %s --check-prefix=VTABLE
+; RUN: llc < %s -asm-verbose=false -wasm-register-codegen-test-mode | FileCheck %s --check-prefix=TYPEINFO
 
 ; Test that simple vtables assemble as expected.
 ;
 ; The class hierarchy is:
 ;   struct A;
 ;   struct B : public A;
 ;   struct C : public A;
 ;   struct D : public B;

test/MC/Disassembler/WebAssembly/wasm.txt

 # RUN: llvm-mc --disassemble %s -triple=wasm32-unknown-unknown | FileCheck %s
 
 # CHECK: .text
 
 # CHECK: nop
 0x01
 
 # CHECK: i32.add
 0x6a
 
 # CHECK: i64.const -1
 0x42 0x7F
 
-# CHECK: i64.load32_u 16, :p2align=1
-# FIXME: fix p2align output in WebAssemblyInstPrinter
+# CHECK: i64.load32_u 16:p2align=1
 0x35 0x01 0x10
 
 # CHECK: block
 # 3
 # FIXME: WebAssemblyInstPrinter does not currently print block number.
 0x02 0x03
 
 # CHECK: call_indirect

test/MC/WebAssembly/basic-assembly.s

-# RUN: llvm-mc -triple=wasm32-unknown-unknown-elf < %s | FileCheck %s
 # RUN: llvm-mc -triple=wasm32-unknown-unknown < %s | FileCheck %s
 
     .text
     .type    test0,@function
 test0:
     # Test all types:
     .param      i32, i64
     .local      f32, f64  #, i8x16, i16x8, i32x4, f32x4
     # Explicit getlocal/setlocal:
-    get_local   $push0=, 2
-    set_local   2, $pop0=
-    # Implicit locals & immediates:
-    i32.const   $0=, -1
-    f64.const   $3=, 0x1.999999999999ap1
+    get_local   2
+    set_local   2
+    # Immediates:
+    i32.const   -1
+    f64.const   0x1.999999999999ap1
     # Indirect addressing:
-    get_local   $push1=, 0
-    f64.store   0($pop1), $3
+    get_local   0
+    f64.store   0
     # Loops, conditionals, binary ops, calls etc:
     block
-    i32.const   $push2=, 1
-    get_local   $push7=, 0
-    i32.ge_s    $push0=, $pop2, $pop7
-    br_if       0, $pop0        # 0: down to label0
+    i32.const   1
+    get_local   0
+    i32.ge_s
+    br_if       0        # 0: down to label0
 .LBB0_1:
     loop             # label1:
-    call        $drop=, something1@FUNCTION
-    i64.const   $push10=, 1234
-    i32.call    $push8=, something2@FUNCTION, $pop10
-    i32.const   $push11=, 0
-    call_indirect $pop11
-    i32.const   $push5=, 1
-    i32.add     $push4=, $pop8, $pop5
-    tee_local   $push3=, 0, $pop4
-    get_local   $push9=, 0
-    i32.lt_s    $push1=, $pop3, $pop9
-    br_if       0, $pop1        # 0: up to label1
+    call        something1@FUNCTION
+    i64.const   1234
+    i32.call    something2@FUNCTION
+    i32.const   0
+    call_indirect
+    i32.const   1
+    i32.add
+    tee_local   0
+    get_local   0
+    i32.lt_s
+    br_if       0        # 0: up to label1
 .LBB0_2:
     end_loop
     end_block                       # label0:
     end_function
 
 
 # CHECK:           .text
 # CHECK-LABEL: test0:
 # CHECK-NEXT:      .param      i32, i64
 # CHECK-NEXT:      .local      f32, f64
-# CHECK-NEXT:      get_local   $push0=, 2
-# CHECK-NEXT:      set_local   2, $pop0
-# CHECK-NEXT:      i32.const   $0=, -1
-# CHECK-NEXT:      f64.const   $3=, 0x1.999999999999ap1
-# CHECK-NEXT:      get_local   $push1=, 0
-# CHECK-NEXT:      f64.store   0($pop1):p2align=0, $3
+# CHECK-NEXT:      get_local   2
+# CHECK-NEXT:      set_local   2
+# CHECK-NEXT:      i32.const   -1
+# CHECK-NEXT:      f64.const   0x1.999999999999ap1
+# CHECK-NEXT:      get_local   0
+# CHECK-NEXT:      f64.store   0:p2align=0
 # CHECK-NEXT:      block
-# CHECK-NEXT:      i32.const   $push2=, 1
-# CHECK-NEXT:      get_local   $push7=, 0
-# CHECK-NEXT:      i32.ge_s    $push0=, $pop2, $pop7
-# CHECK-NEXT:      br_if 0,    $pop0        # 0: down to label0
+# CHECK-NEXT:      i32.const   1
+# CHECK-NEXT:      get_local   0
+# CHECK-NEXT:      i32.ge_s
+# CHECK-NEXT:      br_if 0            # 0: down to label0
 # CHECK-NEXT:  .LBB0_1:
 # CHECK-NEXT:      loop                    # label1:
 # CHECK-NEXT:      call        something1@FUNCTION
-# CHECK-NEXT:      i64.const   $push10=, 1234
-# CHECK-NEXT:      i32.call    $push8=, something2@FUNCTION
-# CHECK-NEXT:      i32.const   $push11=, 0
+# CHECK-NEXT:      i64.const   1234
+# CHECK-NEXT:      i32.call    something2@FUNCTION
+# CHECK-NEXT:      i32.const   0
 # CHECK-NEXT:      call_indirect
-# CHECK-NEXT:      i32.const   $push5=, 1
-# CHECK-NEXT:      i32.add     $push4=, $pop8, $pop5
-# CHECK-NEXT:      tee_local   $push3=, 0, $pop4
-# CHECK-NEXT:      get_local   $push9=, 0
-# CHECK-NEXT:      i32.lt_s    $push1=, $pop3, $pop9
-# CHECK-NEXT:      br_if 0,    $pop1        # 0: up to label1
+# CHECK-NEXT:      i32.const   1
+# CHECK-NEXT:      i32.add
+# CHECK-NEXT:      tee_local   0
+# CHECK-NEXT:      get_local   0
+# CHECK-NEXT:      i32.lt_s
+# CHECK-NEXT:      br_if 0            # 0: up to label1
 # CHECK-NEXT:  .LBB0_2:
 # CHECK-NEXT:      end_loop
 # CHECK-NEXT:      end_block                       # label0:
 # CHECK-NEXT:      end_function

test/MC/WebAssembly/reloc-code.ll

-; RUN: llc -filetype=obj %s -o - | llvm-readobj -r -expand-relocs | FileCheck %s
+; RUN: llc -filetype=obj -wasm-explicit-locals-codegen-test-mode %s -o - | llvm-readobj -r -expand-relocs | FileCheck %s
 
 target triple = "wasm32-unknown-unknown"
 
 ; Pointers to functions of two different types
 @a = global i64 ()* inttoptr (i64 5 to i64 ()*), align 8
 @b = global i32 ()* inttoptr (i32 7 to i32 ()*), align 8
 
 ; External functions

test/MC/WebAssembly/weak-alias.ll

-; RUN: llc -filetype=obj %s -o %t.o
+; RUN: llc -filetype=obj -wasm-explicit-locals-codegen-test-mode %s -o %t.o
 ; RUN: obj2yaml %t.o | FileCheck %s
 ; RUN: llvm-objdump -t %t.o | FileCheck --check-prefix=CHECK-SYMS %s
 
 target triple = "wasm32-unknown-unknown"
 
 ; 'foo_alias()' is weak alias of function 'foo()'
 ; 'bar_alias' is weak alias of global variable 'bar'
 ; Generates two exports of the same function, one of them weak

 define hidden i32 @call_alias_ptr() #0 {
 entry:
   %0 = load i32 ()*, i32 ()** @alias_address, align 8
   %call = call i32 %0()
   ret i32 %call
 }
 
 ; CHECK:        - Type:            TYPE
-; CHECK-NEXT:     Signatures:      
+; CHECK-NEXT:     Signatures:
 ; CHECK-NEXT:       - Index:           0
 ; CHECK-NEXT:         ReturnType:      I32
-; CHECK-NEXT:         ParamTypes:      
+; CHECK-NEXT:         ParamTypes:
 ; CHECK-NEXT:   - Type:            IMPORT
 ; CHECK-NEXT:     Imports:
 ; CHECK-NEXT:       - Module:          env
 ; CHECK-NEXT:         Field:           __linear_memory
 ; CHECK-NEXT:         Kind:            MEMORY
 ; CHECK-NEXT:         Memory:
 ; CHECK-NEXT:           Initial:         0x00000001
 ; CHECK-NEXT:       - Module:          env
 ; CHECK-NEXT:         Field:           __indirect_function_table
 ; CHECK-NEXT:         Kind:            TABLE
 ; CHECK-NEXT:         Table:
 ; CHECK-NEXT:           ElemType:        ANYFUNC
 ; CHECK-NEXT:           Limits:
 ; CHECK-NEXT:             Initial:         0x00000001
 ; CHECK-NEXT:   - Type:            FUNCTION
 ; CHECK-NEXT:     FunctionTypes:   [ 0, 0, 0, 0, 0 ]
 ; CHECK-NEXT:   - Type:            ELEM
-; CHECK-NEXT:     Segments:        
-; CHECK-NEXT:       - Offset:          
+; CHECK-NEXT:     Segments:
+; CHECK-NEXT:       - Offset:
 ; CHECK-NEXT:           Opcode:          I32_CONST
 ; CHECK-NEXT:           Value:           1
 ; CHECK-NEXT:         Functions:       [ 0 ]
 ; CHECK-NEXT:   - Type:            CODE
-; CHECK-NEXT:     Relocations:     
+; CHECK-NEXT:     Relocations:
 ; CHECK-NEXT:       - Type:            R_WEBASSEMBLY_FUNCTION_INDEX_LEB
 ; CHECK-NEXT:         Index:           0
 ; CHECK-NEXT:         Offset:          0x00000009
 ; CHECK-NEXT:       - Type:            R_WEBASSEMBLY_FUNCTION_INDEX_LEB
 ; CHECK-NEXT:         Index:           3
 ; CHECK-NEXT:         Offset:          0x00000012
 ; CHECK-NEXT:       - Type:            R_WEBASSEMBLY_MEMORY_ADDR_LEB
 ; CHECK-NEXT:         Index:           5
 ; CHECK-NEXT:         Offset:          0x0000001E
 ; CHECK-NEXT:       - Type:            R_WEBASSEMBLY_TYPE_INDEX_LEB
 ; CHECK-NEXT:         Index:           0
 ; CHECK-NEXT:         Offset:          0x00000024
 ; CHECK-NEXT:       - Type:            R_WEBASSEMBLY_MEMORY_ADDR_LEB
 ; CHECK-NEXT:         Index:           7
 ; CHECK-NEXT:         Offset:          0x00000031
 ; CHECK-NEXT:       - Type:            R_WEBASSEMBLY_TYPE_INDEX_LEB
 ; CHECK-NEXT:         Index:           0
 ; CHECK-NEXT:         Offset:          0x00000037
-; CHECK-NEXT:     Functions:       
+; CHECK-NEXT:     Functions:
 ; CHECK-NEXT:       - Index:           0
-; CHECK-NEXT:         Locals:          
+; CHECK-NEXT:         Locals:
 ; CHECK-NEXT:         Body:            41000B
 ; CHECK-NEXT:       - Index:           1
-; CHECK-NEXT:         Locals:          
+; CHECK-NEXT:         Locals:
 ; CHECK-NEXT:         Body:            1080808080000B
 ; CHECK-NEXT:       - Index:           2
-; CHECK-NEXT:         Locals:          
+; CHECK-NEXT:         Locals:
 ; CHECK-NEXT:         Body:            1080808080000B
 ; CHECK-NEXT:       - Index:           3
-; CHECK-NEXT:         Locals:          
+; CHECK-NEXT:         Locals:
 ; CHECK-NEXT:         Body:            410028028880808000118080808000000B
 ; CHECK-NEXT:       - Index:           4
-; CHECK-NEXT:         Locals:          
+; CHECK-NEXT:         Locals:
 ; CHECK-NEXT:         Body:            410028029080808000118080808000000B
 ; CHECK-NEXT:   - Type:            DATA
-; CHECK-NEXT:     Relocations:     
+; CHECK-NEXT:     Relocations:
 ; CHECK-NEXT:       - Type:            R_WEBASSEMBLY_TABLE_INDEX_I32
 ; CHECK-NEXT:         Index:           0
 ; CHECK-NEXT:         Offset:          0x0000000F
 ; CHECK-NEXT:       - Type:            R_WEBASSEMBLY_TABLE_INDEX_I32
 ; CHECK-NEXT:         Index:           3
 ; CHECK-NEXT:         Offset:          0x00000018
-; CHECK-NEXT:     Segments:        
+; CHECK-NEXT:     Segments:
 ; CHECK-NEXT:       - SectionOffset:   6
 ; CHECK-NEXT:         MemoryIndex:     0
-; CHECK-NEXT:         Offset:          
+; CHECK-NEXT:         Offset:
 ; CHECK-NEXT:           Opcode:          I32_CONST
 ; CHECK-NEXT:           Value:           0
 ; CHECK-NEXT:         Content:         '07000000'
 ; CHECK-NEXT:       - SectionOffset:   15
 ; CHECK-NEXT:         MemoryIndex:     0
-; CHECK-NEXT:         Offset:          
+; CHECK-NEXT:         Offset:
 ; CHECK-NEXT:           Opcode:          I32_CONST
 ; CHECK-NEXT:           Value:           8
 ; CHECK-NEXT:         Content:         '01000000'
 ; CHECK-NEXT:       - SectionOffset:   24
 ; CHECK-NEXT:         MemoryIndex:     0
 ; CHECK-NEXT:         Offset:
 ; CHECK-NEXT:           Opcode:          I32_CONST
 ; CHECK-NEXT:           Value:           16
 ; CHECK-NEXT:         Content:         '01000000'
 ; CHECK-NEXT:   - Type:            CUSTOM
 ; CHECK-NEXT:     Name:            linking
 ; CHECK-NEXT:     Version:         1
-; CHECK-NEXT:     SymbolTable:      
+; CHECK-NEXT:     SymbolTable:
 ; CHECK-NEXT:       - Index:           0
 ; CHECK-NEXT:         Kind:            FUNCTION
 ; CHECK-NEXT:         Name:            foo
 ; CHECK-NEXT:         Flags:           [ VISIBILITY_HIDDEN ]
 ; CHECK-NEXT:         Function:        0
 ; CHECK-NEXT:       - Index:           1
 ; CHECK-NEXT:         Kind:            FUNCTION
 ; CHECK-NEXT:         Name:            call_direct

 ; CHECK-NEXT:         Segment:         0
 ; CHECK-NEXT:         Size:            4
 ; CHECK-NEXT:       - Index:           9
 ; CHECK-NEXT:         Kind:            DATA
 ; CHECK-NEXT:         Name:            bar_alias
 ; CHECK-NEXT:         Flags:           [ BINDING_WEAK, VISIBILITY_HIDDEN ]
 ; CHECK-NEXT:         Segment:         0
 ; CHECK-NEXT:         Size:            4
-; CHECK-NEXT:     SegmentInfo:    
+; CHECK-NEXT:     SegmentInfo:
 ; CHECK-NEXT:       - Index:           0
 ; CHECK-NEXT:         Name:            .data.bar
 ; CHECK-NEXT:         Alignment:       8
 ; CHECK-NEXT:         Flags:           [ ]
 ; CHECK-NEXT:       - Index:           1
 ; CHECK-NEXT:         Name:            .data.direct_address
 ; CHECK-NEXT:         Alignment:       8
 ; CHECK-NEXT:         Flags:           [ ]

unittests/MC/Disassembler.cpp

TEST(Disassembler, WebAssemblyTest) {
 
   PC += InstSize;
   BytesP += InstSize;
   NumBytes -= InstSize;
 
   InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
                                    OutStringSize);
   EXPECT_EQ(InstSize, 3U);
-  EXPECT_EQ(StringRef(OutString), "\ti64.load32_u\t16, :p2align=1");
+  EXPECT_EQ(StringRef(OutString), "\ti64.load32_u\t16:p2align=1");
 
   LLVMDisasmDispose(DCR);
 }