[AArch64] Armv8.4-A: Virtualization system registers

[olista01]

It would be worth clarifying in the comments and commit message that this is the "Secure EL2" extension, to avoid confusion with the "Enhanced Support for Nested Virtualization" extension, which I assume will be in a later patch.

Other than that, LGTM.

test/MC/Disassembler/AArch64/armv8.4a-vir.txt

1

Should the file name be armv8.4a-virt.txt, for consistency with the assembly test?

[SjoerdMeijer]

Thanks for the suggestion: will clarify that this is indeed "Secure EL2" extension, and the "Enhanced Support for Nested Virtualization" will follow.
I was thinking of keeping the patches small and manageable, but might do the rest of all these system registers in one go; will put something up for review soon.

I will change the file name before committing.

lib/Target/AArch64/AArch64SystemOperands.td

 def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>;
 def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>;
 def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>;
 def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>;
 def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>;
 def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>;
 }
 
+let Requires = [{ {AArch64::HasV8_4aOps} }] in {
+
+// v8.4a "Virtualization secure second stage translation" registers
+//                           Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>;
+def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000>;
+
+// v8.4a "Virtualization timer" registers
+//                                Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>;
+def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>;
+def : RWSysReg<"CNTHVS_CTL_EL2",  0b11, 0b100, 0b1110, 0b0100, 0b001>;
+def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>;
+def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>;
+def : RWSysReg<"CNTHPS_CTL_EL2",  0b11, 0b100, 0b1110, 0b0101, 0b001>;
+
+// v8.4a "Virtualization debug state" registers
+//                           Op0   Op1    CRn     CRm     Op2
+def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;
+
+} // HasV8_4aOps
+
 // Cyclone specific system registers
 //                                 Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::ProcCyclone} }] in
 def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;

test/MC/AArch64/armv8.4a-virt.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+//------------------------------------------------------------------------------
+// Virtualization Enhancements
+//------------------------------------------------------------------------------
+
+  msr   VSTCR_EL2, x0
+  msr   VSTTBR_EL2, x0
+  msr   SDER32_EL2, x12
+  msr   CNTHVS_TVAL_EL2, x0
+  msr   CNTHVS_CVAL_EL2, x0
+  msr   CNTHVS_CTL_EL2, x0
+  msr   CNTHPS_TVAL_EL2, x0
+  msr   CNTHPS_CVAL_EL2, x0
+  msr   CNTHPS_CTL_EL2, x0
+
+//CHECK:  msr VSTCR_EL2, x0           // encoding: [0x40,0x26,0x1c,0xd5]
+//CHECK:  msr VSTTBR_EL2, x0          // encoding: [0x00,0x26,0x1c,0xd5]
+//CHECK:  msr SDER32_EL2, x12         // encoding: [0x2c,0x13,0x1c,0xd5]
+//CHECK:  msr CNTHVS_TVAL_EL2, x0     // encoding: [0x00,0xe4,0x1c,0xd5]
+//CHECK:  msr CNTHVS_CVAL_EL2, x0     // encoding: [0x40,0xe4,0x1c,0xd5]
+//CHECK:  msr CNTHVS_CTL_EL2, x0      // encoding: [0x20,0xe4,0x1c,0xd5]
+//CHECK:  msr CNTHPS_TVAL_EL2, x0     // encoding: [0x00,0xe5,0x1c,0xd5]
+//CHECK:  msr CNTHPS_CVAL_EL2, x0     // encoding: [0x40,0xe5,0x1c,0xd5]
+//CHECK:  msr CNTHPS_CTL_EL2, x0      // encoding: [0x20,0xe5,0x1c,0xd5]
+
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected writable system register or pstate
+//CHECK-ERROR: error: expected writable system register or pstate

test/MC/Disassembler/AArch64/armv8.4a-vir.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+
+0x40,0x26,0x1c,0xd5
+0x40,0x26,0x3c,0xd5
+0x00,0x26,0x1c,0xd5
+0x00,0x26,0x3c,0xd5
+0x2c,0x13,0x1c,0xd5
+0x2c,0x13,0x3c,0xd5
+0x00,0xe4,0x1c,0xd5
+0x00,0xe4,0x3c,0xd5
+0x40,0xe4,0x1c,0xd5
+0x40,0xe4,0x3c,0xd5
+0x20,0xe4,0x1c,0xd5
+0x20,0xe4,0x3c,0xd5
+0x00,0xe5,0x1c,0xd5
+0x00,0xe5,0x3c,0xd5
+0x40,0xe5,0x1c,0xd5
+0x40,0xe5,0x3c,0xd5
+0x20,0xe5,0x1c,0xd5
+0x20,0xe5,0x3c,0xd5
+
+#CHECK:   msr   VSTCR_EL2, x0
+#CHECK:   mrs   x0, VSTCR_EL2
+#CHECK:   msr   VSTTBR_EL2, x0
+#CHECK:   mrs   x0, VSTTBR_EL2
+#CHECK:   msr   SDER32_EL2, x12
+#CHECK:   mrs   x12, SDER32_EL2
+#CHECK:   msr   CNTHVS_TVAL_EL2, x0
+#CHECK:   mrs   x0, CNTHVS_TVAL_EL2
+#CHECK:   msr   CNTHVS_CVAL_EL2, x0
+#CHECK:   mrs   x0, CNTHVS_CVAL_EL2
+#CHECK:   msr   CNTHVS_CTL_EL2, x0
+#CHECK:   mrs   x0, CNTHVS_CTL_EL2
+#CHECK:   msr   CNTHPS_TVAL_EL2, x0
+#CHECK:   mrs   x0, CNTHPS_TVAL_EL2
+#CHECK:   msr   CNTHPS_CVAL_EL2, x0
+#CHECK:   mrs   x0, CNTHPS_CVAL_EL2
+#CHECK:   msr   CNTHPS_CTL_EL2, x0
+#CHECK:   mrs   x0, CNTHPS_CTL_EL2