[llvm-mca] Rename Backend to Pipeline. NFC.

[mattd]

Summary

This change renames the Backend and BackendPrinter to Pipeline and PipelinePrinter respectively.
Variables and comments have also been updated to reflect this change.

The reason for this rename, is to be slightly more correct about what MCA is modeling. MCA models a Pipeline, which implies some logical sequence of stages.

[andreadb]

Hi Matt,

The patch looks good modulo the minor nits reported below.

Thanks!
-Andrea

tools/llvm-mca/HWEventListener.h

34

Please change Scheduler to ExecuteState. Also change components into 'stages'.

tools/llvm-mca/Instruction.h

49

"backend" was correct here. Please revert this change.

267

This comment is no longer valid and should be rewritten. We shouldn't just replace backend with pipeline in this sentence.

tools/llvm-mca/Pipeline.cpp

11

Same.

tools/llvm-mca/Pipeline.h

11

Remove the OoO part. I don't think it makes much sense when applied to pipeline.

28

Same. This sentence should probably be rewritten.

30

The default pipeline currently emulates an OoO execution.

tools/llvm-mca/README.txt

10

Please revert this line. "Backend" was correct.

21

Please revert this part too.

347

I think this should still say 'out-of-order backend'.

tools/llvm-mca/RetireControlUnit.h

29

s/pipeline/backend

[courbet]

tools/llvm-mca/Pipeline.h

11

I would keep it, just to make it clear to the reader that it's not strictly a linear DAG.

[andreadb]

tools/llvm-mca/Pipeline.h

11

The Pipeline (as a container of stages) is not out-of-order. Instead, the hardware backend is OoO. I don't think it is semantically correct to say that the Pipeline is out-of-order.
We could rephrase this as "a Stage pipeline for an OoO processor". Or something similar.

[courbet]

tools/llvm-mca/Pipeline.h

11

SG

[mattd]

Thanks for the feedback. I'll make the changes and land the patch.

tools/llvm-mca/Pipeline.h

11

That's a very interesting distinction I never really considered, but do agree with. It sounds like we should probably define the terms (backend,pipeline,component) formally somewhere, perhaps as a separate commit to the mythical documentation that describes the stage and pipeline designs :)

tools/llvm-mca/CMakeLists.txt

 set(LLVM_LINK_COMPONENTS
   AllTargetsAsmPrinters
   AllTargetsAsmParsers
   AllTargetsDescs
   AllTargetsDisassemblers
   AllTargetsInfos
   MC
   MCParser
   Support
   )
 
 add_llvm_tool(llvm-mca
-  Backend.cpp
-  BackendPrinter.cpp
   CodeRegion.cpp
   DispatchStage.cpp
   DispatchStatistics.cpp
   ExecuteStage.cpp
   FetchStage.cpp
   HWEventListener.cpp
   InstrBuilder.cpp
   Instruction.cpp
   InstructionInfoView.cpp
   InstructionTables.cpp
   LSUnit.cpp
   llvm-mca.cpp
+  Pipeline.cpp
+  PipelinePrinter.cpp
   RegisterFile.cpp
   RegisterFileStatistics.cpp
   ResourcePressureView.cpp
   RetireControlUnit.cpp
   RetireControlUnitStatistics.cpp
   RetireStage.cpp
   Scheduler.cpp
   SchedulerStatistics.cpp
   Stage.cpp
   Support.cpp
   SummaryView.cpp
   TimelineView.cpp
   View.cpp
   )

tools/llvm-mca/DispatchStage.h

 #include "Stage.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace mca {
 
 class WriteState;
 class Scheduler;
-class Backend;
+class Pipeline;
 
 // Implements the hardware dispatch logic.
 //
 // This class is responsible for the dispatch stage, in which instructions are
 // dispatched in groups to the Scheduler.  An instruction can be dispatched if
 // the following conditions are met:
 //  1) There are enough entries in the reorder buffer (see class
 //     RetireControlUnit) to write the opcodes associated with the instruction.
 //  2) There are enough temporaries to rename output register operands.
 //  3) There are enough entries available in the used buffered resource(s).
 //
 // The number of micro opcodes that can be dispatched in one cycle is limited by
 // the value of field 'DispatchWidth'. A "dynamic dispatch stall" occurs when
 // processor resources are not available. Dispatch stall events are counted
 // during the entire execution of the code, and displayed by the performance
 // report when flag '-dispatch-stats' is specified.
 //
 // If the number of micro opcodes exceedes DispatchWidth, then the instruction
 // is dispatched in multiple cycles.
 class DispatchStage : public Stage {
   unsigned DispatchWidth;
   unsigned AvailableEntries;
   unsigned CarryOver;
-  Backend *Owner;
+  Pipeline *Owner;
   const llvm::MCSubtargetInfo &STI;
   RetireControlUnit &RCU;
   RegisterFile &PRF;
   Scheduler ≻
 
   bool checkRCU(const InstRef &IR);
   bool checkPRF(const InstRef &IR);
   bool checkScheduler(const InstRef &IR);
class DispatchStage : public Stage {
   }
 
   void collectWrites(llvm::SmallVectorImpl<WriteState *> &Vec,
                      unsigned RegID) const {
     return PRF.collectWrites(Vec, RegID);
   }
 
 public:
-  DispatchStage(Backend *B, const llvm::MCSubtargetInfo &Subtarget,
+  DispatchStage(Pipeline *P, const llvm::MCSubtargetInfo &Subtarget,
                 const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
                 unsigned MaxDispatchWidth, RetireControlUnit &R,
                 RegisterFile &F, Scheduler &Sched)
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
-        CarryOver(0U), Owner(B), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
+        CarryOver(0U), Owner(P), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
 
   // We can always try to dispatch, so returning false is okay in this case.
   // The retire stage, which controls the RCU, might have items to complete but
   // RetireStage::hasWorkToComplete will check for that case.
   virtual bool hasWorkToComplete() const override final { return false; }
   virtual void preExecute(const InstRef &IR) override final;
   virtual bool execute(InstRef &IR) override final;
   void notifyDispatchStall(const InstRef &IR, unsigned EventType);
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H

tools/llvm-mca/DispatchStage.cpp

 ///
 /// The DispatchStage is responsible for updating instruction dependencies
 /// and communicating to the simulated instruction scheduler that an instruction
 /// is ready to be scheduled for execution.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "DispatchStage.h"
-#include "Backend.h"
 #include "HWEventListener.h"
+#include "Pipeline.h"
 #include "Scheduler.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {

tools/llvm-mca/ExecuteStage.h

 #include "Instruction.h"
 #include "RetireControlUnit.h"
 #include "Scheduler.h"
 #include "Stage.h"
 #include "llvm/ADT/ArrayRef.h"
 
 namespace mca {
 
-class Backend;
+class Pipeline;
 
 class ExecuteStage : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
-  Backend *Owner;
+  Pipeline *Owner;
   RetireControlUnit &RCU;
   Scheduler &HWS;
 
   // The following routines are used to maintain the HWS.
   void reclaimSchedulerResources();
   void updateSchedulerQueues();
   void issueReadyInstructions();
 
 public:
-  ExecuteStage(Backend *B, RetireControlUnit &R, Scheduler &S)
-      : Stage(), Owner(B), RCU(R), HWS(S) {}
+  ExecuteStage(Pipeline *P, RetireControlUnit &R, Scheduler &S)
+      : Stage(), Owner(P), RCU(R), HWS(S) {}
   ExecuteStage(const ExecuteStage &Other) = delete;
   ExecuteStage &operator=(const ExecuteStage &Other) = delete;
 
   // The ExecuteStage will always complete all of its work per call to
   // execute(), so it is never left in a 'to-be-processed' state.
   virtual bool hasWorkToComplete() const override final { return false; }
 
   virtual void preExecute(const InstRef &IR) override final;

tools/llvm-mca/ExecuteStage.cpp

 /// This file defines the execution stage of an instruction pipeline.
 ///
 /// The ExecuteStage is responsible for managing the hardware scheduler
 /// and issuing notifications that an instruction has been executed.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "ExecuteStage.h"
-#include "Backend.h"
+#include "Pipeline.h"
 #include "Scheduler.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 

tools/llvm-mca/HWEventListener.h

 namespace mca {
 
 // An HWInstructionEvent represents state changes of instructions that
 // listeners might be interested in. Listeners can choose to ignore any event
 // they are not interested in.
 class HWInstructionEvent {
 public:
   // This is the list of event types that are shared by all targets, that
-  // generic subtarget-agnostic classes (e.g. Backend, HWInstructionEvent, ...)
-  // and generic Views can manipulate.
+  // generic subtarget-agnostic classes (e.g., Pipeline, HWInstructionEvent,
+  // ...) and generic Views can manipulate.
   // Subtargets are free to define additional event types, that are goin to be
   // handled by generic components as opaque values, but can still be
-  // emitted by subtarget-specific pipeline components (e.g. Scheduler,
+  // emitted by subtarget-specific pipeline components (e.g., Scheduler,
   // DispatchStage, ...) and interpreted by subtarget-specific EventListener
   // implementations.
   enum GenericEventType {
     Invalid = 0,
     // Events generated by the Retire Control Unit.
     Retired,
     // Events generated by the Scheduler.
     Ready,
public:
   const unsigned Type;
 
   // The instruction this event was generated for.
   const InstRef &IR;
 };
 
 class HWEventListener {
 public:
-  // Generic events generated by the backend pipeline.
+  // Generic events generated by the pipeline.
   virtual void onCycleBegin() {}
   virtual void onCycleEnd() {}
 
   virtual void onInstructionEvent(const HWInstructionEvent &Event) {}
   virtual void onStallEvent(const HWStallEvent &Event) {}
 
   using ResourceRef = std::pair<uint64_t, uint64_t>;
   virtual void onResourceAvailable(const ResourceRef &RRef) {}

tools/llvm-mca/Instruction.h

 //===--------------------- Instruction.h ------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file defines abstractions used by the Backend to model register reads,
+/// This file defines abstractions used by the Pipeline to model register reads,
 /// register writes and instructions.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_INSTRUCTION_H
 #define LLVM_TOOLS_LLVM_MCA_INSTRUCTION_H
 
 #include "llvm/Support/MathExtras.h"
struct WriteDescriptor {
   int Latency;
   // This field is set to a value different than zero only if this
   // is an implicit definition.
   unsigned RegisterID;
   // Instruction itineraries would set this field to the SchedClass ID.
   // Otherwise, it defaults to the WriteResourceID from the MCWriteLatencyEntry
   // element associated to this write.
   // When computing read latencies, this value is matched against the
-  // "ReadAdvance" information. The hardware backend may implement
+  // "ReadAdvance" information. The hardware pipeline may implement
   // dedicated forwarding paths to quickly propagate write results to dependent
   // instructions waiting in the reservation station (effectively bypassing the
   // write-back stage).
   unsigned SClassOrWriteResourceID;
   // True only if this is a write obtained from an optional definition.
   // Optional definitions are allowed to reference regID zero (i.e. "no
   // register").
   bool IsOptionalDef;
struct InstrDesc {
   bool MayLoad;
   bool MayStore;
   bool HasSideEffects;
 
   // A zero latency instruction doesn't consume any scheduler resources.
   bool isZeroLatency() const { return !MaxLatency && Resources.empty(); }
 };
 
-/// An instruction dispatched to the out-of-order backend.
+/// An instruction dispatched to the out-of-order pipeline.
 ///
 /// This class is used to monitor changes in the internal state of instructions
 /// that are dispatched by the DispatchUnit to the hardware schedulers.
 class Instruction {
   const InstrDesc &Desc;
 
   enum InstrStage {
     IS_INVALID,   // Instruction in an invalid state.

tools/llvm-mca/Instruction.cpp

 //===--------------------- Instruction.cpp ----------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
-// This file defines abstractions used by the Backend to model register reads,
+// This file defines abstractions used by the Pipeline to model register reads,
 // register writes and instructions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "Instruction.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 

tools/llvm-mca/InstructionTables.cpp

 //===--------------------- InstructionTables.cpp ----------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file implements method InstructionTables::run().
 /// Method run() prints a theoretical resource pressure distribution based on
 /// the information available in the scheduling model, and without running
-/// the backend pipeline.
+/// the pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "InstructionTables.h"
 
 namespace mca {
 
 using namespace llvm;

tools/llvm-mca/Pipeline.h

-//===--------------------- Backend.h ----------------------------*- C++ -*-===//
+//===--------------------- Pipeline.h ---------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements an OoO backend for the llvm-mca tool.
+/// This file implements an OoO pipeline for the llvm-mca tool.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_BACKEND_H
-#define LLVM_TOOLS_LLVM_MCA_BACKEND_H
+#ifndef LLVM_TOOLS_LLVM_MCA_PIPELINE_H
+#define LLVM_TOOLS_LLVM_MCA_PIPELINE_H
 
 #include "Scheduler.h"
 #include "Stage.h"
 #include "llvm/ADT/SmallVector.h"
 
 namespace mca {
 
 class HWEventListener;
 class HWInstructionEvent;
 class HWStallEvent;
 
-/// An out of order backend for a specific subtarget.
+/// An out of order pipeline for a specific subtarget.
 ///
 /// It emulates an out-of-order execution of instructions. Instructions are
 /// fetched from a MCInst sequence managed by an initial 'Fetch' stage.
 /// Instructions are firstly fetched, then dispatched to the schedulers, and
 /// then executed.
 ///
 /// This class tracks the lifetime of an instruction from the moment where
 /// it gets dispatched to the schedulers, to the moment where it finishes
 /// executing and register writes are architecturally committed.
 /// In particular, it monitors changes in the state of every instruction
 /// in flight.
 ///
 /// Instructions are executed in a loop of iterations. The number of iterations
 /// is defined by the SourceMgr object, which is managed by the initial stage
 /// of the instruction pipeline.
 ///
-/// The Backend entry point is method 'run()' which executes cycles in a loop
+/// The Pipeline entry point is method 'run()' which executes cycles in a loop
 /// until there are new instructions to dispatch, and not every instruction
 /// has been retired.
 ///
-/// Internally, the Backend collects statistical information in the form of
+/// Internally, the Pipeline collects statistical information in the form of
 /// histograms. For example, it tracks how the dispatch group size changes
 /// over time.
-class Backend {
-  /// An ordered list of stages that define this backend's instruction pipeline.
+class Pipeline {
+  /// An ordered list of stages that define this instruction pipeline.
   llvm::SmallVector<std::unique_ptr<Stage>, 8> Stages;
   std::set<HWEventListener *> Listeners;
   unsigned Cycles;
 
   bool executeStages(InstRef &IR);
   void postExecuteStages(const InstRef &IR);
   bool hasWorkToProcess();
   void runCycle(unsigned Cycle);
 
 public:
-  Backend(unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
+  Pipeline(unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
            unsigned LoadQueueSize = 0, unsigned StoreQueueSize = 0,
            bool AssumeNoAlias = false)
       : Cycles(0) {}
   void appendStage(std::unique_ptr<Stage> S) { Stages.push_back(std::move(S)); }
   void run();
   void addEventListener(HWEventListener *Listener);
   void notifyCycleBegin(unsigned Cycle);
   void notifyInstructionEvent(const HWInstructionEvent &Event);
   void notifyStallEvent(const HWStallEvent &Event);
   void notifyResourceAvailable(const ResourceRef &RR);
   void notifyReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyCycleEnd(unsigned Cycle);
 };
 } // namespace mca
 
-#endif
+#endif // LLVM_TOOLS_LLVM_MCA_PIPELINE_H

tools/llvm-mca/Pipeline.cpp

-//===--------------------- Backend.cpp --------------------------*- C++ -*-===//
+//===--------------------- Pipeline.cpp -------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// Implementation of class Backend which emulates an hardware OoO backend.
+/// Implementation of class Pipeline which emulates a hardware OoO pipeline.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "Backend.h"
+#include "Pipeline.h"
 #include "HWEventListener.h"
 #include "llvm/CodeGen/TargetSchedule.h"
 #include "llvm/Support/Debug.h"
 
 namespace mca {
 
 #define DEBUG_TYPE "llvm-mca"
 
 using namespace llvm;
 
-void Backend::addEventListener(HWEventListener *Listener) {
+void Pipeline::addEventListener(HWEventListener *Listener) {
   if (Listener)
     Listeners.insert(Listener);
 }
 
-bool Backend::hasWorkToProcess() {
+bool Pipeline::hasWorkToProcess() {
   const auto It = llvm::find_if(Stages, [](const std::unique_ptr<Stage> &S) {
     return S->hasWorkToComplete();
   });
   return It != Stages.end();
 }
 
 // This routine returns early if any stage returns 'false' after execute() is
 // called on it.
-bool Backend::executeStages(InstRef &IR) {
+bool Pipeline::executeStages(InstRef &IR) {
   for (const std::unique_ptr<Stage> &S : Stages)
     if (!S->execute(IR))
       return false;
   return true;
 }
 
-void Backend::postExecuteStages(const InstRef &IR) {
+void Pipeline::postExecuteStages(const InstRef &IR) {
   for (const std::unique_ptr<Stage> &S : Stages)
     S->postExecute(IR);
 }
 
-void Backend::run() {
+void Pipeline::run() {
   while (hasWorkToProcess())
     runCycle(Cycles++);
 }
 
-void Backend::runCycle(unsigned Cycle) {
+void Pipeline::runCycle(unsigned Cycle) {
   notifyCycleBegin(Cycle);
 
   // Update the stages before we do any processing for this cycle.
   InstRef IR;
   for (auto &S : Stages)
     S->preExecute(IR);
 
   // Continue executing this cycle until any stage claims it cannot make
   // progress.
   while (executeStages(IR))
     postExecuteStages(IR);
 
   notifyCycleEnd(Cycle);
 }
 
-void Backend::notifyCycleBegin(unsigned Cycle) {
+void Pipeline::notifyCycleBegin(unsigned Cycle) {
   LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleBegin();
 }
 
-void Backend::notifyInstructionEvent(const HWInstructionEvent &Event) {
+void Pipeline::notifyInstructionEvent(const HWInstructionEvent &Event) {
   for (HWEventListener *Listener : Listeners)
     Listener->onInstructionEvent(Event);
 }
 
-void Backend::notifyStallEvent(const HWStallEvent &Event) {
+void Pipeline::notifyStallEvent(const HWStallEvent &Event) {
   for (HWEventListener *Listener : Listeners)
     Listener->onStallEvent(Event);
 }
 
-void Backend::notifyResourceAvailable(const ResourceRef &RR) {
+void Pipeline::notifyResourceAvailable(const ResourceRef &RR) {
   LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.'
                     << RR.second << "]\n");
   for (HWEventListener *Listener : Listeners)
     Listener->onResourceAvailable(RR);
 }
 
-void Backend::notifyReservedBuffers(ArrayRef<unsigned> Buffers) {
+void Pipeline::notifyReservedBuffers(ArrayRef<unsigned> Buffers) {
   for (HWEventListener *Listener : Listeners)
     Listener->onReservedBuffers(Buffers);
 }
 
-void Backend::notifyReleasedBuffers(ArrayRef<unsigned> Buffers) {
+void Pipeline::notifyReleasedBuffers(ArrayRef<unsigned> Buffers) {
   for (HWEventListener *Listener : Listeners)
     Listener->onReleasedBuffers(Buffers);
 }
 
-void Backend::notifyCycleEnd(unsigned Cycle) {
+void Pipeline::notifyCycleEnd(unsigned Cycle) {
   LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycle << "\n\n");
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleEnd();
 }
 } // namespace mca.

tools/llvm-mca/PipelinePrinter.h

-//===--------------------- BackendPrinter.h ---------------------*- C++ -*-===//
+//===--------------------- PipelinePrinter.h --------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements class BackendPrinter.
+/// This file implements class PipelinePrinter.
 ///
-/// BackendPrinter allows the customization of the performance report.
+/// PipelinePrinter allows the customization of the performance report.
 ///
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TOOLS_LLVM_MCA_BACKENDPRINTER_H
-#define LLVM_TOOLS_LLVM_MCA_BACKENDPRINTER_H
+#ifndef LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H
+#define LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H
 
-#include "Backend.h"
+#include "Pipeline.h"
 #include "View.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
 /// A printer class that knows how to collects statistics on the
 /// code analyzed by the llvm-mca tool.
 ///
 /// This class knows how to print out the analysis information collected
 /// during the execution of the code. Internally, it delegates to other
 /// classes the task of printing out timeline information as well as
 /// resource pressure.
-class BackendPrinter {
-  Backend &B;
+class PipelinePrinter {
+  Pipeline &P;
   llvm::SmallVector<std::unique_ptr<View>, 8> Views;
 
 public:
-  BackendPrinter(Backend &backend) : B(backend) {}
+  PipelinePrinter(Pipeline &pipeline) : P(pipeline) {}
 
   void addView(std::unique_ptr<View> V) {
-    B.addEventListener(V.get());
+    P.addEventListener(V.get());
     Views.emplace_back(std::move(V));
   }
 
   void printReport(llvm::raw_ostream &OS) const;
 };
 } // namespace mca
 
-#endif
+#endif // LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H

tools/llvm-mca/PipelinePrinter.cpp

-//===--------------------- BackendPrinter.cpp -------------------*- C++ -*-===//
+//===--------------------- PipelinePrinter.cpp ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements the BackendPrinter interface.
+/// This file implements the PipelinePrinter interface.
 ///
 //===----------------------------------------------------------------------===//
 
-#include "BackendPrinter.h"
+#include "PipelinePrinter.h"
 #include "View.h"
 #include "llvm/CodeGen/TargetSchedule.h"
 
 namespace mca {
 
 using namespace llvm;
 
-void BackendPrinter::printReport(llvm::raw_ostream &OS) const {
+void PipelinePrinter::printReport(llvm::raw_ostream &OS) const {
   for (const auto &V : Views)
     V->printView(OS);
 }
 } // namespace mca.

tools/llvm-mca/README.txt

 llvm-mca - LLVM Machine Code Analyzer
 -------------------------------------
 
 llvm-mca is a performance analysis tool that uses information which is already
 available in LLVM (e.g., scheduling models) to statically measure the
 performance of machine code in a specific cpu.
 
 Performance is measured in terms of throughput as well as processor resource
 consumption.  The tool currently works for processors with an out-of-order
-backend, for which there is a scheduling model available in LLVM.
+pipeline, for which there is a scheduling model available in LLVM.
 
 The main goal of this tool is not just to predict the performance of the code
 when run on the target, but also help with diagnosing potential performance
 issues.
 
 Given an assembly code sequence, llvm-mca estimates the IPC (instructions Per
 cycle), as well as hardware resources pressure. The analysis and reporting style
 were inspired by the IACA tool from Intel.
 
 The presence of long data dependency chains, as well as poor usage of hardware
-resources may lead to bottlenecks in the back-end.  The tool is able to generate
+resources may lead to bottlenecks in the pipeline.  The tool is able to generate
 a detailed report which should help with identifying and analyzing sources of
 bottlenecks.
 
 Scheduling models are mostly used to compute instruction latencies, to obtain
 read-advance information, and understand how processor resources are used by
 instructions.  By design, the quality of the performance analysis conducted by
 the tool is inevitably affected by the quality of the target scheduling models.
 However, scheduling models intentionally do not describe all processor details,

 limitations, some of which could be overcome by integrating extra information
 into the scheduling models.
 
 How the tool works
 ------------------
 
 The tool takes assembly code as input. Assembly code is parsed into a sequence
 of MCInst with the help of the existing LLVM target assembly parsers. The parsed
-sequence of MCInst is then analyzed by a 'Backend' module to generate a
+sequence of MCInst is then analyzed by a 'Pipeline' module to generate a
 performance report.
 
-The Backend module internally emulates the execution of the machine code
+The Pipeline module internally emulates the execution of the machine code
 sequence in a loop of iterations (which by default is 100). At the end of this
-process, the backend collects a number of statistics which are then printed out
+process, the pipeline collects a number of statistics which are then printed out
 in the form of a report.
 
 Here is an example of performance report generated by the tool for a dot-product
 of two packed float vectors of four elements. The analysis is conducted for
 target x86, cpu btver2:
 
 ///////////////////
 

 
 
 Scheduler's queue usage:
 JALU01,  0/20
 JFPU01,  18/18
 JLSAGU,  0/12
 ///////////////////
 
-Based on the verbose report, the backend was only able to dispatch two
+Based on the verbose report, the pipeline was only able to dispatch two
 instructions 51.5% of the time.  The dispatch group was limited to one
 instruction 44.6% of the cycles, which corresponds to 272 cycles.
 
 If we look at section "Dynamic Dispatch Stall Cycles", we can see how counter
 SCHEDQ reports 272 cycles.  Counter SCHEDQ is incremented every time the
 dispatch logic is unable to dispatch a full group of two instructions because
 the scheduler's queue is full.
 

 to bottlenecks caused by the presence of long data dependencies.
 
 In this example, we can conclude that the IPC is mostly limited by data
 dependencies, and not by resource pressure.
 
 LLVM-MCA instruction flow
 -------------------------
 
-This section describes the instruction flow through the out-of-order backend, as
-well as the functional units involved in the process.
+This section describes the instruction flow through the out-of-order pipeline,
+as well as the functional units involved in the process.
 
 An instruction goes through a default sequence of stages:
     - Dispatch (Instruction is dispatched to the schedulers).
     - Issue (Instruction is issued to the processor pipelines).
     - Write Back (Instruction is executed, and results are written back).
     - Retire (Instruction is retired; writes are architecturally committed).
 
 The tool only models the out-of-order portion of a processor. Therefore, the

tools/llvm-mca/ResourcePressureView.h

 //===--------------------- ResourcePressureView.h ---------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This file define class ResourcePressureView.
 /// Class ResourcePressureView observes hardware events generated by
-/// the Backend object and collects statistics related to resource usage at
+/// the Pipeline object and collects statistics related to resource usage at
 /// instruction granularity.
 /// Resource pressure information is then printed out to a stream in the
 /// form of a table like the one from the example below:
 ///
 /// Resources:
 /// [0] - JALU0
 /// [1] - JALU1
 /// [2] - JDiv

 #include "View.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
 namespace mca {
 
-class Backend;
-
 /// This class collects resource pressure statistics and it is able to print
 /// out all the collected information as a table to an output stream.
 class ResourcePressureView : public View {
   const llvm::MCSubtargetInfo &STI;
   llvm::MCInstPrinter &MCIP;
   const SourceMgr &Source;
 
   // Map to quickly obtain the ResourceUsage column index from a processor

tools/llvm-mca/RetireControlUnit.h

 #include <algorithm>
 #include <vector>
 
 namespace mca {
 
 class DispatchStage;
 
 /// This class tracks which instructions are in-flight (i.e., dispatched but not
-/// retired) in the OoO backend.
+/// retired) in the OoO pipeline.
 //
 /// This class checks on every cycle if/which instructions can be retired.
 /// Instructions are retired in program order.
 /// In the event of instruction retired, the DispatchStage object that owns
 /// this RetireControlUnit (RCU) gets notified.
 /// On instruction retired, register updates are all architecturally
 /// committed, and any temporary registers originally allocated for the
 /// retired instruction are freed.

tools/llvm-mca/RetireStage.h

 #define LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
 
 #include "RegisterFile.h"
 #include "RetireControlUnit.h"
 #include "Stage.h"
 
 namespace mca {
 
-class Backend;
+class Pipeline;
 
 class RetireStage : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
-  Backend *Owner;
+  Pipeline *Owner;
   RetireControlUnit &RCU;
   RegisterFile &PRF;
 
 public:
-  RetireStage(Backend *B, RetireControlUnit &R, RegisterFile &F)
-      : Stage(), Owner(B), RCU(R), PRF(F) {}
+  RetireStage(Pipeline *P, RetireControlUnit &R, RegisterFile &F)
+      : Stage(), Owner(P), RCU(R), PRF(F) {}
   RetireStage(const RetireStage &Other) = delete;
   RetireStage &operator=(const RetireStage &Other) = delete;
 
   virtual bool hasWorkToComplete() const override final { return !RCU.isEmpty(); }
   virtual void preExecute(const InstRef &IR) override final;
   virtual bool execute(InstRef &IR) override final { return true; }
   void notifyInstructionRetired(const InstRef &IR);
   void onInstructionExecuted(unsigned TokenID);
 };
 
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H

tools/llvm-mca/RetireStage.cpp

 ///
 /// This file defines the retire stage of an instruction pipeline.
 /// The RetireStage represents the process logic that interacts with the
 /// simulated RetireControlUnit hardware.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "RetireStage.h"
-#include "Backend.h"
 #include "HWEventListener.h"
+#include "Pipeline.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 

tools/llvm-mca/Scheduler.cpp

 //===--------------------- Scheduler.cpp ------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // A scheduler for processor resource units and processor resource groups.
 //
 //===----------------------------------------------------------------------===//
 
 #include "Scheduler.h"
-#include "Backend.h"
 #include "HWEventListener.h"
+#include "Pipeline.h"
 #include "Support.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace mca {
 
 using namespace llvm;
 
 uint64_t ResourceState::selectNextInSequence() {

tools/llvm-mca/Support.h

 //===--------------------- Support.h ----------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// Helper functions used by various backend components.
+/// Helper functions used by various pipeline components.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_SUPPORT_H
 #define LLVM_TOOLS_LLVM_MCA_SUPPORT_H
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"

tools/llvm-mca/Support.cpp

 //===--------------------- Support.cpp --------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements a few helper functions used by various backend
+/// This file implements a few helper functions used by various pipeline
 /// components.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "Support.h"
 #include "llvm/MC/MCSchedule.h"
 
 namespace mca {

tools/llvm-mca/TimelineView.h

 //===--------------------- TimelineView.h -----------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \brief
 ///
 /// This file implements a timeline view for the llvm-mca tool.
 ///
-/// Class TimelineView observes events generated by the backend. For every
-/// instruction executed by the backend, it stores information related to
+/// Class TimelineView observes events generated by the pipeline. For every
+/// instruction executed by the pipeline, it stores information related to
 /// state transition. It then plots that information in the form of a table
 /// as reported by the example below:
 ///
 /// Timeline view:
 ///                 0123456
 /// Index 0123456789
 ///
 /// [0,0] DeER .    .    .. vmovshdup  %xmm0, %xmm1

 #include "llvm/Support/raw_ostream.h"
 #include <map>
 
 namespace mca {
 
 /// This class listens to instruction state transition events
 /// in order to construct a timeline information.
 ///
-/// For every instruction executed by the Backend, this class constructs
+/// For every instruction executed by the Pipeline, this class constructs
 /// a TimelineViewEntry object. TimelineViewEntry objects are then used
 /// to print the timeline information, as well as the "average wait times"
 /// for every instruction in the input assembly sequence.
 class TimelineView : public View {
   const llvm::MCSubtargetInfo &STI;
   llvm::MCInstPrinter &MCIP;
   const SourceMgr &AsmSequence;
 

tools/llvm-mca/llvm-mca.cpp

 //      -o <file>
 //
 // The target defaults to the host target.
 // The cpu defaults to the 'native' host cpu.
 // The output defaults to standard output.
 //
 //===----------------------------------------------------------------------===//
 
-#include "BackendPrinter.h"
 #include "CodeRegion.h"
 #include "DispatchStage.h"
 #include "DispatchStatistics.h"
 #include "ExecuteStage.h"
 #include "FetchStage.h"
 #include "InstructionInfoView.h"
 #include "InstructionTables.h"
+#include "Pipeline.h"
+#include "PipelinePrinter.h"
 #include "RegisterFile.h"
 #include "RegisterFileStatistics.h"
 #include "ResourcePressureView.h"
 #include "RetireControlUnit.h"
 #include "RetireControlUnitStatistics.h"
 #include "RetireStage.h"
 #include "Scheduler.h"
 #include "SchedulerStatistics.h"
for (const std::unique_ptr<mca::CodeRegion> &Region : Regions) {
     }
 
     // Create the hardware components required for the pipeline.
     mca::RetireControlUnit RCU(SM);
     mca::RegisterFile PRF(SM, *MRI, RegisterFileSize);
     mca::Scheduler HWS(SM, LoadQueueSize, StoreQueueSize, AssumeNoAlias);
 
     // Create the pipeline and add stages to it.
-    auto B = llvm::make_unique<mca::Backend>(
+    auto P = llvm::make_unique<mca::Pipeline>(
         Width, RegisterFileSize, LoadQueueSize, StoreQueueSize, AssumeNoAlias);
-    B->appendStage(llvm::make_unique<mca::FetchStage>(IB, S));
-    B->appendStage(llvm::make_unique<mca::DispatchStage>(
-        B.get(), *STI, *MRI, RegisterFileSize, Width, RCU, PRF, HWS));
-    B->appendStage(llvm::make_unique<mca::RetireStage>(B.get(), RCU, PRF));
-    B->appendStage(llvm::make_unique<mca::ExecuteStage>(B.get(), RCU, HWS));
-    mca::BackendPrinter Printer(*B);
+    P->appendStage(llvm::make_unique<mca::FetchStage>(IB, S));
+    P->appendStage(llvm::make_unique<mca::DispatchStage>(
+        P.get(), *STI, *MRI, RegisterFileSize, Width, RCU, PRF, HWS));
+    P->appendStage(llvm::make_unique<mca::RetireStage>(P.get(), RCU, PRF));
+    P->appendStage(llvm::make_unique<mca::ExecuteStage>(P.get(), RCU, HWS));
+    mca::PipelinePrinter Printer(*P);
 
     if (PrintSummaryView)
       Printer.addView(llvm::make_unique<mca::SummaryView>(SM, S, Width));
 
     if (PrintInstructionInfoView)
       Printer.addView(
           llvm::make_unique<mca::InstructionInfoView>(*STI, *MCII, S, *IP));
 
if (PrintResourcePressureView)
       Printer.addView(
           llvm::make_unique<mca::ResourcePressureView>(*STI, *IP, S));
 
     if (PrintTimelineView) {
       Printer.addView(llvm::make_unique<mca::TimelineView>(
           *STI, *IP, S, TimelineMaxIterations, TimelineMaxCycles));
     }
 
-    B->run();
+    P->run();
     Printer.printReport(TOF->os());
   }
 
   TOF->keep();
   return 0;
 }