[Power9] [LLVM] Add __float128 support for trunc to double round to odd

[stefanp]

Summary

Add support for this builtin:
double builtin_truncf128_round_to_odd(float128)

[lei]

LGTM. Please feel free to fix the nit comments before committing.

lib/Target/PowerPC/PPCInstrVSX.td

2570 ↗

(On Diff #152468)

nit: indent

[(set f64:$vT,
      (int_ppc_truncf128_round_to_odd
        f128:$vB))]>;

test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

146 ↗

(On Diff #152468)

register?

llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_divdeu : GCCBuiltin<"__builtin_divdeu">,
                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                                  [IntrNoMem]>;
 
   // Bit permute doubleword
   def int_ppc_bpermd : GCCBuiltin<"__builtin_bpermd">,
                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                                  [IntrNoMem]>;
 
+  def int_ppc_truncf128_round_to_odd
+      : GCCBuiltin<"__builtin_truncf128_round_to_odd">,
+        Intrinsic <[llvm_double_ty], [llvm_f128_ty], [IntrNoMem]>;
   def int_ppc_sqrtf128_round_to_odd
       : GCCBuiltin<"__builtin_sqrtf128_round_to_odd">,
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty], [IntrNoMem]>;
   def int_ppc_addf128_round_to_odd
       : GCCBuiltin<"__builtin_addf128_round_to_odd">,
         Intrinsic <[llvm_f128_ty], [llvm_f128_ty,llvm_f128_ty], [IntrNoMem]>;
   def int_ppc_subf128_round_to_odd
       : GCCBuiltin<"__builtin_subf128_round_to_odd">,

llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   // Quad-Precision Floating-Point Conversion Instructions:
 
   // Convert DP -> QP
   def XSCVDPQP  : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc,
                                      [(set f128:$vT, (fpextend f64:$vB))]>;
 
   // Round & Convert QP -> DP (dword[1] is set to zero)
   def XSCVQPDP  : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>;
-  def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo", []>;
+  def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo",
+                                        [(set f64:$vT,
+                                        (int_ppc_truncf128_round_to_odd
+                                        f128:$vB))]>;
 
   // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
   def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
   def XSCVQPSWZ : X_VT5_XO5_VB5<63,  9, 836, "xscvqpswz", []>;
   def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
   def XSCVQPUWZ : X_VT5_XO5_VB5<63,  1, 836, "xscvqpuwz", []>;
 
   // Convert (Un)Signed DWord -> QP.

llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

entry:
   %2 = call fp128 @llvm.ppc.divf128.round.to.odd(fp128 %0, fp128 %1)
   ret fp128 %2
 ; CHECK-LABEL: testDivOdd
 ; CHECK: xsdivqpo
 }
 
 declare fp128 @llvm.ppc.divf128.round.to.odd(fp128, fp128)
 
+define double @testTruncOdd() {
+entry:
+  %0 = load fp128, fp128* @A, align 16
+  %1 = call double @llvm.ppc.truncf128.round.to.odd(fp128 %0)
+  ret double %1
+  ; CHECK-LABEL: testTruncOdd
+  ; CHECK: xscvqpdpo
+}
+
+declare double @llvm.ppc.truncf128.round.to.odd(fp128)