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Differential D48483

[Power9] [LLVM] Add __float128 support for trunc to double round to odd
ClosedPublic

Authored by stefanp on Jun 22 2018, 6:49 AM.

Details

Reviewers
nemanjai
kbarton
hfinkel
sfertile
syzaara
lei
Commits
rG58e3e0a827ad: [Power9] [LLVM] Add __float128 support for trunc to double round to odd
rL336595: [Power9] [LLVM] Add __float128 support for trunc to double round to odd
Summary

Add support for this builtin:
double builtin_truncf128_round_to_odd(float128)

Diff Detail

Event Timeline

stefanp created this revision.Jun 22 2018, 6:49 AM
lei accepted this revision.Jun 26 2018, 11:33 AM

LGTM. Please feel free to fix the nit comments before committing.

lib/Target/PowerPC/PPCInstrVSX.td
2570

nit: indent

[(set f64:$vT,
      (int_ppc_truncf128_round_to_odd
        f128:$vB))]>;
test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
146

register?

This revision is now accepted and ready to land.Jun 26 2018, 11:33 AM
Closed by commit rL336595: [Power9] [LLVM] Add __float128 support for trunc to double round to odd (authored by stefanp). · Explain WhyJul 9 2018, 1:14 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
include/
llvm/
IR/
3 lines
lib/
Target/
PowerPC/
5 lines
test/
CodeGen/
PowerPC/
11 lines

Diff 152468

include/llvm/IR/IntrinsicsPowerPC.td

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines def int_ppc_divdeu : GCCBuiltin<"__builtin_divdeu">,
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
[IntrNoMem]>; [IntrNoMem]>;
// Bit permute doubleword // Bit permute doubleword
def int_ppc_bpermd : GCCBuiltin<"__builtin_bpermd">, def int_ppc_bpermd : GCCBuiltin<"__builtin_bpermd">,
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
[IntrNoMem]>; [IntrNoMem]>;
def int_ppc_truncf128_round_to_odd
: GCCBuiltin<"__builtin_truncf128_round_to_odd">,
Intrinsic <[llvm_double_ty], [llvm_f128_ty], [IntrNoMem]>;
def int_ppc_sqrtf128_round_to_odd def int_ppc_sqrtf128_round_to_odd
: GCCBuiltin<"__builtin_sqrtf128_round_to_odd">, : GCCBuiltin<"__builtin_sqrtf128_round_to_odd">,
Intrinsic <[llvm_f128_ty], [llvm_f128_ty], [IntrNoMem]>; Intrinsic <[llvm_f128_ty], [llvm_f128_ty], [IntrNoMem]>;
def int_ppc_addf128_round_to_odd def int_ppc_addf128_round_to_odd
: GCCBuiltin<"__builtin_addf128_round_to_odd">, : GCCBuiltin<"__builtin_addf128_round_to_odd">,
Intrinsic <[llvm_f128_ty], [llvm_f128_ty,llvm_f128_ty], [IntrNoMem]>; Intrinsic <[llvm_f128_ty], [llvm_f128_ty,llvm_f128_ty], [IntrNoMem]>;
def int_ppc_subf128_round_to_odd def int_ppc_subf128_round_to_odd
: GCCBuiltin<"__builtin_subf128_round_to_odd">, : GCCBuiltin<"__builtin_subf128_round_to_odd">,
▲ Show 20 Lines • Show All 1,095 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCInstrVSX.td

Show First 20 Lines • Show All 2,558 Lines • ▼ Show 20 Lineslet AddedComplexity = 400, Predicates = [HasP9Vector] in {
// Quad-Precision Floating-Point Conversion Instructions: // Quad-Precision Floating-Point Conversion Instructions:
// Convert DP -> QP // Convert DP -> QP
def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, []>; def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, []>;
def : Pat<(f128 (fpextend f64:$src)), (f128 (XSCVDPQP $src))>; def : Pat<(f128 (fpextend f64:$src)), (f128 (XSCVDPQP $src))>;
// Round & Convert QP -> DP (dword[1] is set to zero) // Round & Convert QP -> DP (dword[1] is set to zero)
def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>; def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>;
def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo", []>; def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo",
[(set f64:$vT,
(int_ppc_truncf128_round_to_odd
f128:$vB))]>;
leiUnsubmitted
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nit: indent

[(set f64:$vT,
      (int_ppc_truncf128_round_to_odd
        f128:$vB))]>;
lei: nit: indent ``` [(set f64:$vT, (int_ppc_truncf128_round_to_odd f128:$vB))]>; ```
// Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero) // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>; def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>; def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>;
def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>; def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>; def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>;
// Convert (Un)Signed DWord -> QP. // Convert (Un)Signed DWord -> QP.
▲ Show 20 Lines • Show All 1,181 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Linesentry:
ret i64 %1 ret i64 %1
; CHECK-LABEL: extract_exp ; CHECK-LABEL: extract_exp
; CHECK: xsxexpqp ; CHECK: xsxexpqp
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i64 @llvm.ppc.scalar.extract.expq(fp128) declare i64 @llvm.ppc.scalar.extract.expq(fp128)
define double @testTruncOdd() {
entry:
%0 = load fp128, fp128* @A, align 16
%1 = call double @llvm.ppc.truncf128.round.to.odd(fp128 %0)
ret double %1
; CHECK-LABEL: testTruncOdd
; CHECK: xscvqpdpo
leiUnsubmitted
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register?

lei: register?
}
declare double @llvm.ppc.truncf128.round.to.odd(fp128)