[RISCV] Add support for _interrupt attribute

[apazos]

Summary

• Save/restore only registers that are used. This includes Callee saved registers and Caller saved registers (arguments and temporaries) for integer and FP registers.
• If there is a call in the interrupt handler, save/restore all Caller saved registers and all FP registers.
• Emit special return instructions depending on "interrupt" attribute type.

Based on initial patch by Zhaoshi Zheng.

[apazos]

Initial code was saving all registers.
Modified it to save only the ones used, or all registers if there is a call.
Still needs some fixes and tests update.
Sharing the WIP to collect feedback.

[apazos]

Updated tests and registers saved with extensions F and D

[asb]

Thanks Ana. I've added some initial review comments. Sorry for the slight delay, I've been on vacation the past week.

lib/Target/RISCV/RISCVCallingConv.td

22–23

Shouldn't these sets include the normal callee-saved registers? (X1, X3, X4, X8, X9). As it stands, I think an interrupt handler with high register pressure would fail to save these registers before dirtying them.

lib/Target/RISCV/RISCVRegisterInfo.cpp

37–40

F and D registers should be saved based on the target ABI rather than the presence of F/D. As support for the hard-float RISC-V ABIs hasn't landed in upstream LLVM yet, leaving save/restore of floating point registers out of this patch might be sensible.

test/CodeGen/RISCV/interrupt-attr.ll

21–24

It would be good to extend these tests so they do something simple that will require registers to be allocated (load a value from a global, add 1 and store again?). Then it should demonstrate the registers are being saved and restored as expected.

43–45

In the interests of completeness it would be good to have on test for an interrupt handler with "no-frame-pointer-elim"="true" as well, demonstrating that there are no problems saving the frame pointer.

[apazos]

lib/Target/RISCV/RISCVCallingConv.td

22–23

I initially thought about only saving the Caller saved registers that are either arguments (X10-X17) or temporaries (X5-X7 and X28-X31).

But this list is being used not only to force the registers that need to be saved unconditionally (when the interrupt handler calls another function) but also in the call to getCalleeSavedRegs. So it has to have all Callee and Caller saved registers. I will update the list and add the additional registers X3, X4, X8, X9.

lib/Target/RISCV/RISCVRegisterInfo.cpp

37–40

In that case I think we should at least warn that interrupt attribute in the presence of F and D extensions will not preserve the registers correctly. What do you think?

test/CodeGen/RISCV/interrupt-attr.ll

21–24

Sure, we can create the test for riscv32 for now, but riscv64 global address lowering will fail. I will add the riscv32 test case and leave a TODO for the riscv64 test case.

43–45

Sure, will add a function test case with the attribute being set.

[apazos]

Updated patch to address review comments.

[apazos]

lib/Target/RISCV/RISCVCallingConv.td

31

Note that CSR_Interrupt_With_Call is only used to provide a list of registers that need to be unconditionally saved. It is not used by
getCalleeSavedRegs nor getCallPreservedMask. Maybe the reuse of the class CalleeSavedRegs is confusing? I wanted to avoid listing each register in RISCVFrameLowering::determineCalleeSave.

[asb]

lib/Target/RISCV/RISCVRegisterInfo.cpp

37–40

Thanks for questioning this because this was a 'thinko' on my part and I was incorrect. If F/D are enabled for codegen then we _should_ save and restore F+D, as the function that was interrupted might have been using them, as could a function that we call from the interrupt handler.

[apazos]

Added back code to save FP registers.

[asb]

This is looking good to me, I've added some comments. The logic around callee/caller save registers is a little confusing but the way you're handling it seems sensible. A comment clarifying things in determineCalleeSaves would be really useful I think.

lib/Target/RISCV/RISCVCallingConv.td

32

Would be more accurately called CSR_XLEN_F32 or CSR_GPR_F32 as the X registers are a variable-length register class. i.e. we won't need to define CSR_X64_F32. Same for CSR_X32_F64.

lib/Target/RISCV/RISCVFrameLowering.cpp

217

callee-saved

218

Just for clarity, the reason we can't use getCalleeSavedRegs is that we want to force-save only those registers that are callee-saved under the standard ABI, while the array returned by getCalleeSaved regs contains the full set of registers that are either callee or caller saved under the standard ABI? It would be useful to add a comment explaining this I think.

[apazos]

lib/Target/RISCV/RISCVCallingConv.td

32

Sure, will change the name to XLEN.

lib/Target/RISCV/RISCVFrameLowering.cpp

217

This code is forcing the saving of all arguments and temporaries plus all the floating point registers, even if they are not used.
Arguments and temporaries are ra, t0-2, a0-a7, t3-t6 (which are all Caller-saved registers).
So the comment is correct (includes Caller and floating point registers only).

Here is the logic I am enforcing:

• If interrupt is enabled:
  • If no calls Save all registers if they are used. That includes callee saved, caller saved, and FP registers. When you call getCalleeSavedRegs and getCallPreservedMask, it returns the data for the lists CSR_XLEN_F32 and CSR_XLEN_F64. In my last patch I missed getCallPreservedMask. I will update that function. ----If has calls Force saving all arguments and temporaries (these are the Caller saved registers), even if not used. Force saving all FP registers, even if not used. RISCVFrameLowering::determineCalleeSaves is the place to force saving these registers.

I checked GCC and it seems to implement this behavior from what I could test.

Let me know if you agree.

[asb]

lib/Target/RISCV/RISCVFrameLowering.cpp

217

I agree that's the desired logic and your original comment is correct.

[asb]

Looks good to me, thanks!

lib/Target/RISCV/RISCVCallingConv.td

 
 // The RISC-V calling convention is handled with custom code in
 // RISCVISelLowering.cpp (CC_RISCV).
 
 def CSR : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
 
 // Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
+
+// Interrupt handler needs to save/restore all registers that are used,
+// both Caller and Callee saved registers.
+def CSR_Interrupt : CalleeSavedRegs<(add X1, X3, X4, X5, X6, X7, X8, X9,
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 18, 27),
+    (sequence "X%u", 28, 31))>;
+
+// Interrupt handler with calls to other functions needs to
+// unconditionally save all Caller saved registers.
+def CSR_Interrupt_With_Call :  CalleeSavedRegs<(add X1, X3, X4, X5, X6, X7,
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 28, 31))>;

lib/Target/RISCV/RISCVFrameLowering.cpp

void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                               RegScavenger *RS) const {
   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
   // Unconditionally spill RA and FP only if the function uses a frame
   // pointer.
   if (hasFP(MF)) {
     SavedRegs.set(RISCV::X1);
     SavedRegs.set(RISCV::X8);
   }
+
+  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
+  // If interrupt is enabled and there are calls, unconditionally save
+  // all Caller saved registers regardless whether they are used.
+  if (MF.getFunction().hasFnAttribute("interrupt")) {
+    MachineFrameInfo &MFI = MF.getFrameInfo();
+    if(MFI.hasCalls()) {
+      const MCPhysReg *CSRegs = RI->getCalleeSavedRegsForInterruptWithCall();
+      for (unsigned i = 0; CSRegs[i]; ++i)
+        SavedRegs.set(CSRegs[i]);
+    }
+  }
 }
 
 void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
     MachineFunction &MF, RegScavenger *RS) const {
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterClass *RC = &RISCV::GPRRegClass;
   // estimateStackSize has been observed to under-estimate the final stack

lib/Target/RISCV/RISCVISelLowering.h

 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {
 class RISCVSubtarget;
 namespace RISCVISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   RET_FLAG,
+  URET_FLAG,
+  SRET_FLAG,
+  MRET_FLAG,
   CALL,
   SELECT_CC,
   BuildPairF64,
   SplitF64,
   TAIL
 };
 }
 

lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::LowerFormalArguments(
   default:
     report_fatal_error("Unsupported calling convention");
   case CallingConv::C:
   case CallingConv::Fast:
     break;
   }
 
   MachineFunction &MF = DAG.getMachineFunction();
+
+  const Function &Func = MF.getFunction();
+  if (Func.hasFnAttribute("interrupt")) {
+    if (!Func.arg_empty())
+      report_fatal_error(
+        "Functions with the interrupt attribute cannot have arguments!");
+
+    StringRef Kind =
+      MF.getFunction().getFnAttribute("interrupt").getValueAsString();
+
+    if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
+      report_fatal_error(
+        "Function interrupt attribute argument not supported!");
+  }
+
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   MVT XLenVT = Subtarget.getXLenVT();
   unsigned XLenInBytes = Subtarget.getXLen() / 8;
   // Used with vargs to acumulate store chains.
   std::vector<SDValue> OutChains;
 
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
 
   RetOps[0] = Chain; // Update chain.
 
   // Add the glue node if we have it.
   if (Glue.getNode()) {
     RetOps.push_back(Glue);
   }
 
+  // Interrupt service routines use different return instructions.
+  const Function &Func = DAG.getMachineFunction().getFunction();
+  if (Func.hasFnAttribute("interrupt")) {
+    if (!Func.getReturnType()->isVoidTy())
+      report_fatal_error(
+          "Functions with the interrupt attribute must have void return type!");
+
+    MachineFunction &MF = DAG.getMachineFunction();
+    StringRef Kind =
+      MF.getFunction().getFnAttribute("interrupt").getValueAsString();
+
+    unsigned RetOpc;
+    if (Kind == "user")
+      RetOpc = RISCVISD::URET_FLAG;
+    else if (Kind == "supervisor")
+      RetOpc = RISCVISD::SRET_FLAG;
+    else
+      RetOpc = RISCVISD::MRET_FLAG;
+
+    return DAG.getNode(RetOpc, DL, MVT::Other, RetOps);
+  }
+
   return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
 }
 
 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((RISCVISD::NodeType)Opcode) {
   case RISCVISD::FIRST_NUMBER:
     break;
   case RISCVISD::RET_FLAG:
     return "RISCVISD::RET_FLAG";
+  case RISCVISD::URET_FLAG:
+    return "RISCVISD::URET_FLAG";
+  case RISCVISD::SRET_FLAG:
+    return "RISCVISD::SRET_FLAG";
+  case RISCVISD::MRET_FLAG:
+    return "RISCVISD::MRET_FLAG";
   case RISCVISD::CALL:
     return "RISCVISD::CALL";
   case RISCVISD::SELECT_CC:
     return "RISCVISD::SELECT_CC";
   case RISCVISD::BuildPairF64:
     return "RISCVISD::BuildPairF64";
   case RISCVISD::SplitF64:
     return "RISCVISD::SplitF64";

lib/Target/RISCV/RISCVInstrInfo.cpp

void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                          const TargetRegisterInfo *TRI) const {
   DebugLoc DL;
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
   unsigned Opcode;
 
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
-    Opcode = RISCV::SW;
+    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
+             RISCV::SW : RISCV::SD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FSW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FSD;
   else
     llvm_unreachable("Can't store this register to stack slot");
 
   BuildMI(MBB, I, DL, get(Opcode))
void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                           const TargetRegisterInfo *TRI) const {
   DebugLoc DL;
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
   unsigned Opcode;
 
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
-    Opcode = RISCV::LW;
+    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
+             RISCV::LW : RISCV::LD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FLW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FLD;
   else
     llvm_unreachable("Can't load this register from stack slot");
 
   BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);

lib/Target/RISCV/RISCVInstrInfo.td

def Call         : SDNode<"RISCVISD::CALL", SDT_RISCVCall,
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                            SDNPVariadic]>;
 def CallSeqStart : SDNode<"ISD::CALLSEQ_START", SDT_RISCVCallSeqStart,
                           [SDNPHasChain, SDNPOutGlue]>;
 def CallSeqEnd   : SDNode<"ISD::CALLSEQ_END", SDT_RISCVCallSeqEnd,
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 def RetFlag      : SDNode<"RISCVISD::RET_FLAG", SDTNone,
                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+def URetFlag     : SDNode<"RISCVISD::URET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
+def SRetFlag     : SDNode<"RISCVISD::SRET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
+def MRetFlag     : SDNode<"RISCVISD::MRET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
 def SelectCC     : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
                           [SDNPInGlue]>;
 def Tail         : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                            SDNPVariadic]>;
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.

 let isCall = 1, Defs = [X1], isCodeGenOnly = 0 in
 def PseudoCALL : Pseudo<(outs), (ins bare_symbol:$func),
                         [(Call tglobaladdr:$func)]> {
   let AsmString = "call\t$func";
 }
 
 def : Pat<(Call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
+def : Pat<(URetFlag), (URET X0, X0)>;
+def : Pat<(SRetFlag), (SRET X0, X0)>;
+def : Pat<(MRetFlag), (MRET X0, X0)>;
+
 let isCall = 1, Defs = [X1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>,
                          PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
 
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in
 def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>,
                 PseudoInstExpansion<(JALR X0, X1, 0)>;
 

lib/Target/RISCV/RISCVRegisterInfo.h

struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
 
   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
   bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
     return true;
   }
+
+ const MCPhysReg *getCalleeSavedRegsForInterruptWithCall() const;
 };
 }
 
 #endif

lib/Target/RISCV/RISCVRegisterInfo.cpp

 using namespace llvm;
 
 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
                            /*PC*/0, HwMode) {}
 
 const MCPhysReg *
 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+  if (MF->getFunction().hasFnAttribute("interrupt"))
+    return CSR_Interrupt_SaveList;
   return CSR_SaveList;
 }
 
 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
 
   // Use markSuperRegs to ensure any register aliases are also reserved
   markSuperRegs(Reserved, RISCV::X0); // zero
   markSuperRegs(Reserved, RISCV::X1); // ra
   markSuperRegs(Reserved, RISCV::X2); // sp
   markSuperRegs(Reserved, RISCV::X3); // gp

 }
 
 unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = getFrameLowering(MF);
   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
 }
 
 const uint32_t *
-RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
+RISCVRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                         CallingConv::ID /*CC*/) const {
+  if (MF.getFunction().hasFnAttribute("interrupt"))
+    return CSR_Interrupt_RegMask;
   return CSR_RegMask;
 }
+
+const MCPhysReg *
+RISCVRegisterInfo::getCalleeSavedRegsForInterruptWithCall() const {
+  return CSR_Interrupt_With_Call_SaveList;
+}

lib/Target/RISCV/RISCVSubtarget.cpp

RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(StringRef CPU,
   return *this;
 }
 
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, const TargetMachine &TM)
     : RISCVGenSubtargetInfo(TT, CPU, FS),
       FrameLowering(initializeSubtargetDependencies(CPU, FS, TT.isArch64Bit())),
       InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}
+

test/CodeGen/RISCV/interrupt-attr-args-error.ll

+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments!
+define i32 @isr_user(i8 %n) #0 {
+  ret i32 0
+}
+
+attributes #0 = { "interrupt"="user" }

test/CodeGen/RISCV/interrupt-attr-invalid.ll

+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Function interrupt attribute argument not supported!
+define void @isr_user() #0 {
+  ret void
+}
+
+attributes #0 = { "interrupt"="foo" }

test/CodeGen/RISCV/interrupt-attr-nocall.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32
+;
+; TODO: Add RV64 tests when we can lower global addresses.
+
+; Checking all registers that are used are being saved.
+; This includes Caller (arguments and temps) and
+; Callee saved registers.
+;
+; extern int a, b, c;
+; __attribute__((interrupt)) void foo_no_call(void) {
+;   c = a + b;
+; }
+;
+
+@a = external global i32
+@b = external global i32
+@c = external global i32
+
+define void @foo_no_call() #0 {
+; CHECK-RV32-LABEL: foo_no_call:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    sw a0, 12(sp)
+; CHECK-RV32-NEXT:    sw a1, 8(sp)
+; CHECK-RV32-NEXT:    lui a0, %hi(a)
+; CHECK-RV32-NEXT:    lw a0, %lo(a)(a0)
+; CHECK-RV32-NEXT:    lui a1, %hi(b)
+; CHECK-RV32-NEXT:    lw a1, %lo(b)(a1)
+; CHECK-RV32-NEXT:    add a0, a1, a0
+; CHECK-RV32-NEXT:    lui a1, %hi(c)
+; CHECK-RV32-NEXT:    sw a0, %lo(c)(a1)
+; CHECK-RV32-NEXT:    lw a1, 8(sp)
+; CHECK-RV32-NEXT:    lw a0, 12(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    mret
+  %1 = load i32, i32* @a
+  %2 = load i32, i32* @b
+  %add = add nsw i32 %2, %1
+  store i32 %add, i32* @c
+  ret void
+}
+
+;
+; Additionally check frame pointer and return address are properly saved.
+;
+
+define void @foo_no_call2() #1 {
+; CHECK-RV32-LABEL: foo_no_call2:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    sw ra, 12(sp)
+; CHECK-RV32-NEXT:    sw s0, 8(sp)
+; CHECK-RV32-NEXT:    sw a0, 4(sp)
+; CHECK-RV32-NEXT:    sw a1, 0(sp)
+; CHECK-RV32-NEXT:    addi s0, sp, 16
+; CHECK-RV32-NEXT:    lui a0, %hi(a)
+; CHECK-RV32-NEXT:    lw a0, %lo(a)(a0)
+; CHECK-RV32-NEXT:    lui a1, %hi(b)
+; CHECK-RV32-NEXT:    lw a1, %lo(b)(a1)
+; CHECK-RV32-NEXT:    add a0, a1, a0
+; CHECK-RV32-NEXT:    lui a1, %hi(c)
+; CHECK-RV32-NEXT:    sw a0, %lo(c)(a1)
+; CHECK-RV32-NEXT:    lw a1, 0(sp)
+; CHECK-RV32-NEXT:    lw a0, 4(sp)
+; CHECK-RV32-NEXT:    lw s0, 8(sp)
+; CHECK-RV32-NEXT:    lw ra, 12(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    mret
+  %1 = load i32, i32* @a
+  %2 = load i32, i32* @b
+  %add = add nsw i32 %2, %1
+  store i32 %add, i32* @c
+  ret void
+}
+
+attributes #0 = { "interrupt"="machine" }
+attributes #1 = { "interrupt"="machine" "no-frame-pointer-elim"="true" }

test/CodeGen/RISCV/interrupt-attr-ret-error.ll

+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type!
+define i32 @isr1_user() #0 {
+  ret i32 0
+}
+
+
+attributes #0 = { "interrupt"="user" }

test/CodeGen/RISCV/interrupt-attr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32
+; RUN: llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64
+
+;
+;
+; TODO: Add RV64 tests when we can lower global addresses.
+;
+; Checking for special return instructions (uret, sret, mret).
+;
+define void @foo_user() #0 {
+; CHECK-LABEL: foo_user:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    uret
+  ret void
+}
+
+define void @foo_supervisor() #1 {
+; CHECK-LABEL: foo_supervisor:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sret
+  ret void
+}
+
+define void @foo_machine() #2 {
+; CHECK-LABEL: foo_machine:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mret
+  ret void
+}
+
+;
+; Checking all Caller saved registers (arguments and temps)
+; are all saved since they might be clobbered if the handler
+; calls another function.
+;
+; extern int otherfoo();
+;
+; __attribute__((interrupt)) void foo_with_call() {
+;   otherfoo();
+; }
+;
+
+declare i32 @otherfoo(...)
+define void @foo_with_call() #2 {
+; CHECK-RV32-LABEL: foo_with_call:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -80
+; CHECK-RV32-NEXT:    sw ra, 76(sp)
+; CHECK-RV32-NEXT:    sw gp, 72(sp)
+; CHECK-RV32-NEXT:    sw tp, 68(sp)
+; CHECK-RV32-NEXT:    sw t0, 64(sp)
+; CHECK-RV32-NEXT:    sw t1, 60(sp)
+; CHECK-RV32-NEXT:    sw t2, 56(sp)
+; CHECK-RV32-NEXT:    sw a0, 52(sp)
+; CHECK-RV32-NEXT:    sw a1, 48(sp)
+; CHECK-RV32-NEXT:    sw a2, 44(sp)
+; CHECK-RV32-NEXT:    sw a3, 40(sp)
+; CHECK-RV32-NEXT:    sw a4, 36(sp)
+; CHECK-RV32-NEXT:    sw a5, 32(sp)
+; CHECK-RV32-NEXT:    sw a6, 28(sp)
+; CHECK-RV32-NEXT:    sw a7, 24(sp)
+; CHECK-RV32-NEXT:    sw t3, 20(sp)
+; CHECK-RV32-NEXT:    sw t4, 16(sp)
+; CHECK-RV32-NEXT:    sw t5, 12(sp)
+; CHECK-RV32-NEXT:    sw t6, 8(sp)
+; CHECK-RV32-NEXT:    call otherfoo
+; CHECK-RV32-NEXT:    lw t6, 8(sp)
+; CHECK-RV32-NEXT:    lw t5, 12(sp)
+; CHECK-RV32-NEXT:    lw t4, 16(sp)
+; CHECK-RV32-NEXT:    lw t3, 20(sp)
+; CHECK-RV32-NEXT:    lw a7, 24(sp)
+; CHECK-RV32-NEXT:    lw a6, 28(sp)
+; CHECK-RV32-NEXT:    lw a5, 32(sp)
+; CHECK-RV32-NEXT:    lw a4, 36(sp)
+; CHECK-RV32-NEXT:    lw a3, 40(sp)
+; CHECK-RV32-NEXT:    lw a2, 44(sp)
+; CHECK-RV32-NEXT:    lw a1, 48(sp)
+; CHECK-RV32-NEXT:    lw a0, 52(sp)
+; CHECK-RV32-NEXT:    lw t2, 56(sp)
+; CHECK-RV32-NEXT:    lw t1, 60(sp)
+; CHECK-RV32-NEXT:    lw t0, 64(sp)
+; CHECK-RV32-NEXT:    lw tp, 68(sp)
+; CHECK-RV32-NEXT:    lw gp, 72(sp)
+; CHECK-RV32-NEXT:    lw ra, 76(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 80
+; CHECK-RV32-NEXT:    mret
+;
+; CHECK-RV64-LABEL: foo_with_call:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    addi sp, sp, -144
+; CHECK-RV64-NEXT:    sd ra, 136(sp)
+; CHECK-RV64-NEXT:    sd gp, 128(sp)
+; CHECK-RV64-NEXT:    sd tp, 120(sp)
+; CHECK-RV64-NEXT:    sd t0, 112(sp)
+; CHECK-RV64-NEXT:    sd t1, 104(sp)
+; CHECK-RV64-NEXT:    sd t2, 96(sp)
+; CHECK-RV64-NEXT:    sd a0, 88(sp)
+; CHECK-RV64-NEXT:    sd a1, 80(sp)
+; CHECK-RV64-NEXT:    sd a2, 72(sp)
+; CHECK-RV64-NEXT:    sd a3, 64(sp)
+; CHECK-RV64-NEXT:    sd a4, 56(sp)
+; CHECK-RV64-NEXT:    sd a5, 48(sp)
+; CHECK-RV64-NEXT:    sd a6, 40(sp)
+; CHECK-RV64-NEXT:    sd a7, 32(sp)
+; CHECK-RV64-NEXT:    sd t3, 24(sp)
+; CHECK-RV64-NEXT:    sd t4, 16(sp)
+; CHECK-RV64-NEXT:    sd t5, 8(sp)
+; CHECK-RV64-NEXT:    sd t6, 0(sp)
+; CHECK-RV64-NEXT:    call otherfoo
+; CHECK-RV64-NEXT:    ld t6, 0(sp)
+; CHECK-RV64-NEXT:    ld t5, 8(sp)
+; CHECK-RV64-NEXT:    ld t4, 16(sp)
+; CHECK-RV64-NEXT:    ld t3, 24(sp)
+; CHECK-RV64-NEXT:    ld a7, 32(sp)
+; CHECK-RV64-NEXT:    ld a6, 40(sp)
+; CHECK-RV64-NEXT:    ld a5, 48(sp)
+; CHECK-RV64-NEXT:    ld a4, 56(sp)
+; CHECK-RV64-NEXT:    ld a3, 64(sp)
+; CHECK-RV64-NEXT:    ld a2, 72(sp)
+; CHECK-RV64-NEXT:    ld a1, 80(sp)
+; CHECK-RV64-NEXT:    ld a0, 88(sp)
+; CHECK-RV64-NEXT:    ld t2, 96(sp)
+; CHECK-RV64-NEXT:    ld t1, 104(sp)
+; CHECK-RV64-NEXT:    ld t0, 112(sp)
+; CHECK-RV64-NEXT:    ld tp, 120(sp)
+; CHECK-RV64-NEXT:    ld gp, 128(sp)
+; CHECK-RV64-NEXT:    ld ra, 136(sp)
+; CHECK-RV64-NEXT:    addi sp, sp, 144
+; CHECK-RV64-NEXT:    mret
+  %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
+  ret void
+}
+
+;
+; Additionally check frame pointer and return address are properly saved.
+;
+define void @foo_with_call2() #3 {
+; CHECK-RV32-LABEL: foo_with_call2:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -80
+; CHECK-RV32-NEXT:    sw ra, 76(sp)
+; CHECK-RV32-NEXT:    sw gp, 72(sp)
+; CHECK-RV32-NEXT:    sw tp, 68(sp)
+; CHECK-RV32-NEXT:    sw t0, 64(sp)
+; CHECK-RV32-NEXT:    sw t1, 60(sp)
+; CHECK-RV32-NEXT:    sw t2, 56(sp)
+; CHECK-RV32-NEXT:    sw s0, 52(sp)
+; CHECK-RV32-NEXT:    sw a0, 48(sp)
+; CHECK-RV32-NEXT:    sw a1, 44(sp)
+; CHECK-RV32-NEXT:    sw a2, 40(sp)
+; CHECK-RV32-NEXT:    sw a3, 36(sp)
+; CHECK-RV32-NEXT:    sw a4, 32(sp)
+; CHECK-RV32-NEXT:    sw a5, 28(sp)
+; CHECK-RV32-NEXT:    sw a6, 24(sp)
+; CHECK-RV32-NEXT:    sw a7, 20(sp)
+; CHECK-RV32-NEXT:    sw t3, 16(sp)
+; CHECK-RV32-NEXT:    sw t4, 12(sp)
+; CHECK-RV32-NEXT:    sw t5, 8(sp)
+; CHECK-RV32-NEXT:    sw t6, 4(sp)
+; CHECK-RV32-NEXT:    addi s0, sp, 80
+; CHECK-RV32-NEXT:    call otherfoo
+; CHECK-RV32-NEXT:    lw t6, 4(sp)
+; CHECK-RV32-NEXT:    lw t5, 8(sp)
+; CHECK-RV32-NEXT:    lw t4, 12(sp)
+; CHECK-RV32-NEXT:    lw t3, 16(sp)
+; CHECK-RV32-NEXT:    lw a7, 20(sp)
+; CHECK-RV32-NEXT:    lw a6, 24(sp)
+; CHECK-RV32-NEXT:    lw a5, 28(sp)
+; CHECK-RV32-NEXT:    lw a4, 32(sp)
+; CHECK-RV32-NEXT:    lw a3, 36(sp)
+; CHECK-RV32-NEXT:    lw a2, 40(sp)
+; CHECK-RV32-NEXT:    lw a1, 44(sp)
+; CHECK-RV32-NEXT:    lw a0, 48(sp)
+; CHECK-RV32-NEXT:    lw s0, 52(sp)
+; CHECK-RV32-NEXT:    lw t2, 56(sp)
+; CHECK-RV32-NEXT:    lw t1, 60(sp)
+; CHECK-RV32-NEXT:    lw t0, 64(sp)
+; CHECK-RV32-NEXT:    lw tp, 68(sp)
+; CHECK-RV32-NEXT:    lw gp, 72(sp)
+; CHECK-RV32-NEXT:    lw ra, 76(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 80
+; CHECK-RV32-NEXT:    mret
+;
+; CHECK-RV64-LABEL: foo_with_call2:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    addi sp, sp, -160
+; CHECK-RV64-NEXT:    sd ra, 152(sp)
+; CHECK-RV64-NEXT:    sd gp, 144(sp)
+; CHECK-RV64-NEXT:    sd tp, 136(sp)
+; CHECK-RV64-NEXT:    sd t0, 128(sp)
+; CHECK-RV64-NEXT:    sd t1, 120(sp)
+; CHECK-RV64-NEXT:    sd t2, 112(sp)
+; CHECK-RV64-NEXT:    sd s0, 104(sp)
+; CHECK-RV64-NEXT:    sd a0, 96(sp)
+; CHECK-RV64-NEXT:    sd a1, 88(sp)
+; CHECK-RV64-NEXT:    sd a2, 80(sp)
+; CHECK-RV64-NEXT:    sd a3, 72(sp)
+; CHECK-RV64-NEXT:    sd a4, 64(sp)
+; CHECK-RV64-NEXT:    sd a5, 56(sp)
+; CHECK-RV64-NEXT:    sd a6, 48(sp)
+; CHECK-RV64-NEXT:    sd a7, 40(sp)
+; CHECK-RV64-NEXT:    sd t3, 32(sp)
+; CHECK-RV64-NEXT:    sd t4, 24(sp)
+; CHECK-RV64-NEXT:    sd t5, 16(sp)
+; CHECK-RV64-NEXT:    sd t6, 8(sp)
+; CHECK-RV64-NEXT:    addi s0, sp, 160
+; CHECK-RV64-NEXT:    call otherfoo
+; CHECK-RV64-NEXT:    ld t6, 8(sp)
+; CHECK-RV64-NEXT:    ld t5, 16(sp)
+; CHECK-RV64-NEXT:    ld t4, 24(sp)
+; CHECK-RV64-NEXT:    ld t3, 32(sp)
+; CHECK-RV64-NEXT:    ld a7, 40(sp)
+; CHECK-RV64-NEXT:    ld a6, 48(sp)
+; CHECK-RV64-NEXT:    ld a5, 56(sp)
+; CHECK-RV64-NEXT:    ld a4, 64(sp)
+; CHECK-RV64-NEXT:    ld a3, 72(sp)
+; CHECK-RV64-NEXT:    ld a2, 80(sp)
+; CHECK-RV64-NEXT:    ld a1, 88(sp)
+; CHECK-RV64-NEXT:    ld a0, 96(sp)
+; CHECK-RV64-NEXT:    ld s0, 104(sp)
+; CHECK-RV64-NEXT:    ld t2, 112(sp)
+; CHECK-RV64-NEXT:    ld t1, 120(sp)
+; CHECK-RV64-NEXT:    ld t0, 128(sp)
+; CHECK-RV64-NEXT:    ld tp, 136(sp)
+; CHECK-RV64-NEXT:    ld gp, 144(sp)
+; CHECK-RV64-NEXT:    ld ra, 152(sp)
+; CHECK-RV64-NEXT:    addi sp, sp, 160
+; CHECK-RV64-NEXT:    mret
+  %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
+  ret void
+}
+
+attributes #0 = { "interrupt"="user" }
+attributes #1 = { "interrupt"="supervisor" }
+attributes #2 = { "interrupt"="machine" }
+attributes #3 = { "interrupt"="machine" "no-frame-pointer-elim"="true" }