[RISCV] Add support for _interrupt attribute

[apazos]

Summary

• Save/restore only registers that are used. This includes Callee saved registers and Caller saved registers (arguments and temporaries) for integer and FP registers.
• If there is a call in the interrupt handler, save/restore all Caller saved registers and all FP registers.
• Emit special return instructions depending on "interrupt" attribute type.

Based on initial patch by Zhaoshi Zheng.

[apazos]

Initial code was saving all registers.
Modified it to save only the ones used, or all registers if there is a call.
Still needs some fixes and tests update.
Sharing the WIP to collect feedback.

[apazos]

Updated tests and registers saved with extensions F and D

[asb]

Thanks Ana. I've added some initial review comments. Sorry for the slight delay, I've been on vacation the past week.

lib/Target/RISCV/RISCVCallingConv.td

22–23 ↗

(On Diff #153595)

Shouldn't these sets include the normal callee-saved registers? (X1, X3, X4, X8, X9). As it stands, I think an interrupt handler with high register pressure would fail to save these registers before dirtying them.

lib/Target/RISCV/RISCVRegisterInfo.cpp

37–40 ↗

(On Diff #153595)

F and D registers should be saved based on the target ABI rather than the presence of F/D. As support for the hard-float RISC-V ABIs hasn't landed in upstream LLVM yet, leaving save/restore of floating point registers out of this patch might be sensible.

test/CodeGen/RISCV/interrupt-attr.ll

20–23 ↗

(On Diff #153595)

It would be good to extend these tests so they do something simple that will require registers to be allocated (load a value from a global, add 1 and store again?). Then it should demonstrate the registers are being saved and restored as expected.

42–44 ↗

(On Diff #153595)

In the interests of completeness it would be good to have on test for an interrupt handler with "no-frame-pointer-elim"="true" as well, demonstrating that there are no problems saving the frame pointer.

[apazos]

lib/Target/RISCV/RISCVCallingConv.td

22–23 ↗

(On Diff #153595)

I initially thought about only saving the Caller saved registers that are either arguments (X10-X17) or temporaries (X5-X7 and X28-X31).

But this list is being used not only to force the registers that need to be saved unconditionally (when the interrupt handler calls another function) but also in the call to getCalleeSavedRegs. So it has to have all Callee and Caller saved registers. I will update the list and add the additional registers X3, X4, X8, X9.

lib/Target/RISCV/RISCVRegisterInfo.cpp

37–40 ↗

(On Diff #153595)

In that case I think we should at least warn that interrupt attribute in the presence of F and D extensions will not preserve the registers correctly. What do you think?

test/CodeGen/RISCV/interrupt-attr.ll

20–23 ↗

(On Diff #153595)

Sure, we can create the test for riscv32 for now, but riscv64 global address lowering will fail. I will add the riscv32 test case and leave a TODO for the riscv64 test case.

42–44 ↗

(On Diff #153595)

Sure, will add a function test case with the attribute being set.

[apazos]

Updated patch to address review comments.

[apazos]

lib/Target/RISCV/RISCVCallingConv.td

31 ↗

(On Diff #154889)

Note that CSR_Interrupt_With_Call is only used to provide a list of registers that need to be unconditionally saved. It is not used by
getCalleeSavedRegs nor getCallPreservedMask. Maybe the reuse of the class CalleeSavedRegs is confusing? I wanted to avoid listing each register in RISCVFrameLowering::determineCalleeSave.

[asb]

lib/Target/RISCV/RISCVRegisterInfo.cpp

37–40 ↗

(On Diff #153595)

Thanks for questioning this because this was a 'thinko' on my part and I was incorrect. If F/D are enabled for codegen then we _should_ save and restore F+D, as the function that was interrupted might have been using them, as could a function that we call from the interrupt handler.

[apazos]

Added back code to save FP registers.

[asb]

This is looking good to me, I've added some comments. The logic around callee/caller save registers is a little confusing but the way you're handling it seems sensible. A comment clarifying things in determineCalleeSaves would be really useful I think.

lib/Target/RISCV/RISCVCallingConv.td

32 ↗

(On Diff #155437)

Would be more accurately called CSR_XLEN_F32 or CSR_GPR_F32 as the X registers are a variable-length register class. i.e. we won't need to define CSR_X64_F32. Same for CSR_X32_F64.

lib/Target/RISCV/RISCVFrameLowering.cpp

217 ↗

(On Diff #155437)

callee-saved

218 ↗

(On Diff #155437)

Just for clarity, the reason we can't use getCalleeSavedRegs is that we want to force-save only those registers that are callee-saved under the standard ABI, while the array returned by getCalleeSaved regs contains the full set of registers that are either callee or caller saved under the standard ABI? It would be useful to add a comment explaining this I think.

[apazos]

lib/Target/RISCV/RISCVCallingConv.td

32 ↗

(On Diff #155437)

Sure, will change the name to XLEN.

lib/Target/RISCV/RISCVFrameLowering.cpp

217 ↗

(On Diff #155437)

This code is forcing the saving of all arguments and temporaries plus all the floating point registers, even if they are not used.
Arguments and temporaries are ra, t0-2, a0-a7, t3-t6 (which are all Caller-saved registers).
So the comment is correct (includes Caller and floating point registers only).

Here is the logic I am enforcing:

• If interrupt is enabled:
  • If no calls Save all registers if they are used. That includes callee saved, caller saved, and FP registers. When you call getCalleeSavedRegs and getCallPreservedMask, it returns the data for the lists CSR_XLEN_F32 and CSR_XLEN_F64. In my last patch I missed getCallPreservedMask. I will update that function. ----If has calls Force saving all arguments and temporaries (these are the Caller saved registers), even if not used. Force saving all FP registers, even if not used. RISCVFrameLowering::determineCalleeSaves is the place to force saving these registers.

I checked GCC and it seems to implement this behavior from what I could test.

Let me know if you agree.

[asb]

lib/Target/RISCV/RISCVFrameLowering.cpp

217 ↗

(On Diff #155437)

I agree that's the desired logic and your original comment is correct.

[asb]

Looks good to me, thanks!

llvm/trunk/lib/Target/RISCV/RISCVCallingConv.td

 
 // The RISC-V calling convention is handled with custom code in
 // RISCVISelLowering.cpp (CC_RISCV).
 
 def CSR : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
 
 // Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
+
+// Interrupt handler needs to save/restore all registers that are used,
+// both Caller and Callee saved registers.
+def CSR_Interrupt : CalleeSavedRegs<(add X1,
+    (sequence "X%u", 3, 9),
+    (sequence "X%u", 10, 11),
+    (sequence "X%u", 12, 17),
+    (sequence "X%u", 18, 27),
+    (sequence "X%u", 28, 31))>;
+
+// Same as CSR_Interrupt, but including all 32-bit FP registers.
+def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add X1,
+    (sequence "X%u", 3, 9),
+    (sequence "X%u", 10, 11),
+    (sequence "X%u", 12, 17),
+    (sequence "X%u", 18, 27),
+    (sequence "X%u", 28, 31),
+    (sequence "F%u_32", 0, 7),
+    (sequence "F%u_32", 10, 11),
+    (sequence "F%u_32", 12, 17),
+    (sequence "F%u_32", 28, 31),
+    (sequence "F%u_32", 8, 9),
+    (sequence "F%u_32", 18, 27))>;
+
+// Same as CSR_Interrupt, but including all 64-bit FP registers.
+def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
+    (sequence "X%u", 3, 9),
+    (sequence "X%u", 10, 11),
+    (sequence "X%u", 12, 17),
+    (sequence "X%u", 18, 27),
+    (sequence "X%u", 28, 31),
+    (sequence "F%u_64", 0, 7),
+    (sequence "F%u_64", 10, 11),
+    (sequence "F%u_64", 12, 17),
+    (sequence "F%u_64", 28, 31),
+    (sequence "F%u_64", 8, 9),
+    (sequence "F%u_64", 18, 27))>;

llvm/trunk/lib/Target/RISCV/RISCVFrameLowering.cpp

void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
                                               RegScavenger *RS) const {
   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
   // Unconditionally spill RA and FP only if the function uses a frame
   // pointer.
   if (hasFP(MF)) {
     SavedRegs.set(RISCV::X1);
     SavedRegs.set(RISCV::X8);
   }
+
+  // If interrupt is enabled and there are calls in the handler,
+  // unconditionally save all Caller-saved registers and
+  // all FP registers, regardless whether they are used.
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+
+  if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
+
+    static const MCPhysReg CSRegs[] = { RISCV::X1,      /* ra */
+      RISCV::X5, RISCV::X6, RISCV::X7,                  /* t0-t2 */
+      RISCV::X10, RISCV::X11,                           /* a0-a1, a2-a7 */
+      RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
+      RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */
+    };
+
+    for (unsigned i = 0; CSRegs[i]; ++i)
+      SavedRegs.set(CSRegs[i]);
+
+    if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD() ||
+        MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
+
+      // If interrupt is enabled, this list contains all FP registers.
+      const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
+
+      for (unsigned i = 0; Regs[i]; ++i)
+        if (RISCV::FPR32RegClass.contains(Regs[i]) ||
+            RISCV::FPR64RegClass.contains(Regs[i]))
+          SavedRegs.set(Regs[i]);
+    }
+  }
 }
 
 void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
     MachineFunction &MF, RegScavenger *RS) const {
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterClass *RC = &RISCV::GPRRegClass;
   // estimateStackSize has been observed to under-estimate the final stack

llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h

 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {
 class RISCVSubtarget;
 namespace RISCVISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   RET_FLAG,
+  URET_FLAG,
+  SRET_FLAG,
+  MRET_FLAG,
   CALL,
   SELECT_CC,
   BuildPairF64,
   SplitF64,
   TAIL
 };
 }
 

llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::LowerFormalArguments(
   default:
     report_fatal_error("Unsupported calling convention");
   case CallingConv::C:
   case CallingConv::Fast:
     break;
   }
 
   MachineFunction &MF = DAG.getMachineFunction();
+
+  const Function &Func = MF.getFunction();
+  if (Func.hasFnAttribute("interrupt")) {
+    if (!Func.arg_empty())
+      report_fatal_error(
+        "Functions with the interrupt attribute cannot have arguments!");
+
+    StringRef Kind =
+      MF.getFunction().getFnAttribute("interrupt").getValueAsString();
+
+    if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
+      report_fatal_error(
+        "Function interrupt attribute argument not supported!");
+  }
+
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   MVT XLenVT = Subtarget.getXLenVT();
   unsigned XLenInBytes = Subtarget.getXLen() / 8;
   // Used with vargs to acumulate store chains.
   std::vector<SDValue> OutChains;
 
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
 
   RetOps[0] = Chain; // Update chain.
 
   // Add the glue node if we have it.
   if (Glue.getNode()) {
     RetOps.push_back(Glue);
   }
 
+  // Interrupt service routines use different return instructions.
+  const Function &Func = DAG.getMachineFunction().getFunction();
+  if (Func.hasFnAttribute("interrupt")) {
+    if (!Func.getReturnType()->isVoidTy())
+      report_fatal_error(
+          "Functions with the interrupt attribute must have void return type!");
+
+    MachineFunction &MF = DAG.getMachineFunction();
+    StringRef Kind =
+      MF.getFunction().getFnAttribute("interrupt").getValueAsString();
+
+    unsigned RetOpc;
+    if (Kind == "user")
+      RetOpc = RISCVISD::URET_FLAG;
+    else if (Kind == "supervisor")
+      RetOpc = RISCVISD::SRET_FLAG;
+    else
+      RetOpc = RISCVISD::MRET_FLAG;
+
+    return DAG.getNode(RetOpc, DL, MVT::Other, RetOps);
+  }
+
   return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
 }
 
 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((RISCVISD::NodeType)Opcode) {
   case RISCVISD::FIRST_NUMBER:
     break;
   case RISCVISD::RET_FLAG:
     return "RISCVISD::RET_FLAG";
+  case RISCVISD::URET_FLAG:
+    return "RISCVISD::URET_FLAG";
+  case RISCVISD::SRET_FLAG:
+    return "RISCVISD::SRET_FLAG";
+  case RISCVISD::MRET_FLAG:
+    return "RISCVISD::MRET_FLAG";
   case RISCVISD::CALL:
     return "RISCVISD::CALL";
   case RISCVISD::SELECT_CC:
     return "RISCVISD::SELECT_CC";
   case RISCVISD::BuildPairF64:
     return "RISCVISD::BuildPairF64";
   case RISCVISD::SplitF64:
     return "RISCVISD::SplitF64";

llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp

void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                          const TargetRegisterInfo *TRI) const {
   DebugLoc DL;
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
   unsigned Opcode;
 
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
-    Opcode = RISCV::SW;
+    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
+             RISCV::SW : RISCV::SD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FSW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FSD;
   else
     llvm_unreachable("Can't store this register to stack slot");
 
   BuildMI(MBB, I, DL, get(Opcode))
void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                           const TargetRegisterInfo *TRI) const {
   DebugLoc DL;
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
   unsigned Opcode;
 
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
-    Opcode = RISCV::LW;
+    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
+             RISCV::LW : RISCV::LD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FLW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FLD;
   else
     llvm_unreachable("Can't load this register from stack slot");
 
   BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);

llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td

def Call         : SDNode<"RISCVISD::CALL", SDT_RISCVCall,
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                            SDNPVariadic]>;
 def CallSeqStart : SDNode<"ISD::CALLSEQ_START", SDT_RISCVCallSeqStart,
                           [SDNPHasChain, SDNPOutGlue]>;
 def CallSeqEnd   : SDNode<"ISD::CALLSEQ_END", SDT_RISCVCallSeqEnd,
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 def RetFlag      : SDNode<"RISCVISD::RET_FLAG", SDTNone,
                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+def URetFlag     : SDNode<"RISCVISD::URET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
+def SRetFlag     : SDNode<"RISCVISD::SRET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
+def MRetFlag     : SDNode<"RISCVISD::MRET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
 def SelectCC     : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
                           [SDNPInGlue]>;
 def Tail         : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                            SDNPVariadic]>;
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.

 let isCall = 1, Defs = [X1], isCodeGenOnly = 0 in
 def PseudoCALL : Pseudo<(outs), (ins bare_symbol:$func),
                         [(Call tglobaladdr:$func)]> {
   let AsmString = "call\t$func";
 }
 
 def : Pat<(Call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
+def : Pat<(URetFlag), (URET X0, X0)>;
+def : Pat<(SRetFlag), (SRET X0, X0)>;
+def : Pat<(MRetFlag), (MRET X0, X0)>;
+
 let isCall = 1, Defs = [X1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>,
                          PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
 
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in
 def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>,
                 PseudoInstExpansion<(JALR X0, X1, 0)>;
 

llvm/trunk/lib/Target/RISCV/RISCVRegisterInfo.cpp

 using namespace llvm;
 
 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
                            /*PC*/0, HwMode) {}
 
 const MCPhysReg *
 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+  if (MF->getFunction().hasFnAttribute("interrupt")) {
+    if (MF->getSubtarget<RISCVSubtarget>().hasStdExtD())
+      return CSR_XLEN_F64_Interrupt_SaveList;
+    if (MF->getSubtarget<RISCVSubtarget>().hasStdExtF())
+      return CSR_XLEN_F32_Interrupt_SaveList;
+    return CSR_Interrupt_SaveList;
+  }
   return CSR_SaveList;
 }
 
 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
 
   // Use markSuperRegs to ensure any register aliases are also reserved
   markSuperRegs(Reserved, RISCV::X0); // zero

 }
 
 unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = getFrameLowering(MF);
   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
 }
 
 const uint32_t *
-RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
+RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
                                         CallingConv::ID /*CC*/) const {
+  if (MF.getFunction().hasFnAttribute("interrupt")) {
+    if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD())
+      return CSR_XLEN_F64_Interrupt_RegMask;
+    if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF())
+      return CSR_XLEN_F32_Interrupt_RegMask;
+    return CSR_Interrupt_RegMask;
+  }
   return CSR_RegMask;
 }

llvm/trunk/test/CodeGen/RISCV/interrupt-attr-args-error.ll

+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments!
+define i32 @isr_user(i8 %n) #0 {
+  ret i32 0
+}
+
+attributes #0 = { "interrupt"="user" }

llvm/trunk/test/CodeGen/RISCV/interrupt-attr-invalid.ll

+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Function interrupt attribute argument not supported!
+define void @isr_user() #0 {
+  ret void
+}
+
+attributes #0 = { "interrupt"="foo" }

llvm/trunk/test/CodeGen/RISCV/interrupt-attr-nocall.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-F
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-FD
+;
+; TODO: Add RV64 tests when we can lower global addresses.
+
+; Checking all registers that are used are being saved.
+; This includes Caller (arguments and temps) and
+; Callee saved registers.
+;
+; extern int a, b, c;
+; __attribute__((interrupt)) void foo_no_call(void) {
+;   c = a + b;
+; }
+;
+
+@a = external global i32
+@b = external global i32
+@c = external global i32
+
+define void @foo_i32() #0 {
+; CHECK-RV32-LABEL: foo_i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    sw a0, 12(sp)
+; CHECK-RV32-NEXT:    sw a1, 8(sp)
+; CHECK-RV32-NEXT:    lui a0, %hi(a)
+; CHECK-RV32-NEXT:    lw a0, %lo(a)(a0)
+; CHECK-RV32-NEXT:    lui a1, %hi(b)
+; CHECK-RV32-NEXT:    lw a1, %lo(b)(a1)
+; CHECK-RV32-NEXT:    add a0, a1, a0
+; CHECK-RV32-NEXT:    lui a1, %hi(c)
+; CHECK-RV32-NEXT:    sw a0, %lo(c)(a1)
+; CHECK-RV32-NEXT:    lw a1, 8(sp)
+; CHECK-RV32-NEXT:    lw a0, 12(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    mret
+;
+  %1 = load i32, i32* @a
+  %2 = load i32, i32* @b
+  %add = add nsw i32 %2, %1
+  store i32 %add, i32* @c
+  ret void
+}
+
+;
+; Additionally check frame pointer and return address are properly saved.
+;
+
+define void @foo_fp_i32() #1 {
+; CHECK-RV32-LABEL: foo_fp_i32:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    sw ra, 12(sp)
+; CHECK-RV32-NEXT:    sw s0, 8(sp)
+; CHECK-RV32-NEXT:    sw a0, 4(sp)
+; CHECK-RV32-NEXT:    sw a1, 0(sp)
+; CHECK-RV32-NEXT:    addi s0, sp, 16
+; CHECK-RV32-NEXT:    lui a0, %hi(a)
+; CHECK-RV32-NEXT:    lw a0, %lo(a)(a0)
+; CHECK-RV32-NEXT:    lui a1, %hi(b)
+; CHECK-RV32-NEXT:    lw a1, %lo(b)(a1)
+; CHECK-RV32-NEXT:    add a0, a1, a0
+; CHECK-RV32-NEXT:    lui a1, %hi(c)
+; CHECK-RV32-NEXT:    sw a0, %lo(c)(a1)
+; CHECK-RV32-NEXT:    lw a1, 0(sp)
+; CHECK-RV32-NEXT:    lw a0, 4(sp)
+; CHECK-RV32-NEXT:    lw s0, 8(sp)
+; CHECK-RV32-NEXT:    lw ra, 12(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    mret
+;
+  %1 = load i32, i32* @a
+  %2 = load i32, i32* @b
+  %add = add nsw i32 %2, %1
+  store i32 %add, i32* @c
+  ret void
+}
+
+@e = external global float
+@f = external global float
+@d = external global float
+
+define void @foo_float() #0 {
+; CHECK-RV32-F-LABEL: foo_float:
+; CHECK-RV32-F:       # %bb.0:
+; CHECK-RV32-F-NEXT:    addi sp, sp, -16
+; CHECK-RV32-F-NEXT:    sw a0, 12(sp)
+; CHECK-RV32-F-NEXT:    fsw ft0, 8(sp)
+; CHECK-RV32-F-NEXT:    fsw ft1, 4(sp)
+; CHECK-RV32-F-NEXT:    lui a0, %hi(f)
+; CHECK-RV32-F-NEXT:    flw ft0, %lo(f)(a0)
+; CHECK-RV32-F-NEXT:    lui a0, %hi(e)
+; CHECK-RV32-F-NEXT:    flw ft1, %lo(e)(a0)
+; CHECK-RV32-F-NEXT:    fadd.s ft0, ft1, ft0
+; CHECK-RV32-F-NEXT:    lui a0, %hi(d)
+; CHECK-RV32-F-NEXT:    fsw ft0, %lo(d)(a0)
+; CHECK-RV32-F-NEXT:    flw ft1, 4(sp)
+; CHECK-RV32-F-NEXT:    flw ft0, 8(sp)
+; CHECK-RV32-F-NEXT:    lw a0, 12(sp)
+; CHECK-RV32-F-NEXT:    addi sp, sp, 16
+; CHECK-RV32-F-NEXT:    mret
+;
+  %1 = load float, float* @e
+  %2 = load float, float* @f
+  %add = fadd float %1, %2
+  store float %add, float* @d
+  ret void
+}
+
+;
+; Additionally check frame pointer and return address are properly saved.
+;
+define void @foo_fp_float() #1 {
+; CHECK-RV32-F-LABEL: foo_fp_float:
+; CHECK-RV32-F:       # %bb.0:
+; CHECK-RV32-F-NEXT:    addi sp, sp, -32
+; CHECK-RV32-F-NEXT:    sw ra, 28(sp)
+; CHECK-RV32-F-NEXT:    sw s0, 24(sp)
+; CHECK-RV32-F-NEXT:    sw a0, 20(sp)
+; CHECK-RV32-F-NEXT:    fsw ft0, 16(sp)
+; CHECK-RV32-F-NEXT:    fsw ft1, 12(sp)
+; CHECK-RV32-F-NEXT:    addi s0, sp, 32
+; CHECK-RV32-F-NEXT:    lui a0, %hi(f)
+; CHECK-RV32-F-NEXT:    flw ft0, %lo(f)(a0)
+; CHECK-RV32-F-NEXT:    lui a0, %hi(e)
+; CHECK-RV32-F-NEXT:    flw ft1, %lo(e)(a0)
+; CHECK-RV32-F-NEXT:    fadd.s ft0, ft1, ft0
+; CHECK-RV32-F-NEXT:    lui a0, %hi(d)
+; CHECK-RV32-F-NEXT:    fsw ft0, %lo(d)(a0)
+; CHECK-RV32-F-NEXT:    flw ft1, 12(sp)
+; CHECK-RV32-F-NEXT:    flw ft0, 16(sp)
+; CHECK-RV32-F-NEXT:    lw a0, 20(sp)
+; CHECK-RV32-F-NEXT:    lw s0, 24(sp)
+; CHECK-RV32-F-NEXT:    lw ra, 28(sp)
+; CHECK-RV32-F-NEXT:    addi sp, sp, 32
+; CHECK-RV32-F-NEXT:    mret
+;
+  %1 = load float, float* @e
+  %2 = load float, float* @f
+  %add = fadd float %1, %2
+  store float %add, float* @d
+  ret void
+}
+
+@h = external global double
+@i = external global double
+@g = external global double
+
+define void @foo_double() #0 {
+; CHECK-RV32-FD-LABEL: foo_double:
+; CHECK-RV32-FD:       # %bb.0:
+; CHECK-RV32-FD-NEXT:    addi sp, sp, -32
+; CHECK-RV32-FD-NEXT:    sw a0, 28(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft0, 16(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft1, 8(sp)
+; CHECK-RV32-FD-NEXT:    lui a0, %hi(i)
+; CHECK-RV32-FD-NEXT:    fld ft0, %lo(i)(a0)
+; CHECK-RV32-FD-NEXT:    lui a0, %hi(h)
+; CHECK-RV32-FD-NEXT:    fld ft1, %lo(h)(a0)
+; CHECK-RV32-FD-NEXT:    fadd.d ft0, ft1, ft0
+; CHECK-RV32-FD-NEXT:    lui a0, %hi(g)
+; CHECK-RV32-FD-NEXT:    fsd ft0, %lo(g)(a0)
+; CHECK-RV32-FD-NEXT:    fld ft1, 8(sp)
+; CHECK-RV32-FD-NEXT:    fld ft0, 16(sp)
+; CHECK-RV32-FD-NEXT:    lw a0, 28(sp)
+; CHECK-RV32-FD-NEXT:    addi sp, sp, 32
+; CHECK-RV32-FD-NEXT:    mret
+;
+  %1 = load double, double* @h
+  %2 = load double, double* @i
+  %add = fadd double %1, %2
+  store double %add, double* @g
+  ret void
+}
+
+;
+; Additionally check frame pointer and return address are properly saved.
+;
+define void @foo_fp_double() #1 {
+; CHECK-RV32-FD-LABEL: foo_fp_double:
+; CHECK-RV32-FD:       # %bb.0:
+; CHECK-RV32-FD-NEXT:    addi sp, sp, -32
+; CHECK-RV32-FD-NEXT:    sw ra, 28(sp)
+; CHECK-RV32-FD-NEXT:    sw s0, 24(sp)
+; CHECK-RV32-FD-NEXT:    sw a0, 20(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft0, 8(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft1, 0(sp)
+; CHECK-RV32-FD-NEXT:    addi s0, sp, 32
+; CHECK-RV32-FD-NEXT:    lui a0, %hi(i)
+; CHECK-RV32-FD-NEXT:    fld ft0, %lo(i)(a0)
+; CHECK-RV32-FD-NEXT:    lui a0, %hi(h)
+; CHECK-RV32-FD-NEXT:    fld ft1, %lo(h)(a0)
+; CHECK-RV32-FD-NEXT:    fadd.d ft0, ft1, ft0
+; CHECK-RV32-FD-NEXT:    lui a0, %hi(g)
+; CHECK-RV32-FD-NEXT:    fsd ft0, %lo(g)(a0)
+; CHECK-RV32-FD-NEXT:    fld ft1, 0(sp)
+; CHECK-RV32-FD-NEXT:    fld ft0, 8(sp)
+; CHECK-RV32-FD-NEXT:    lw a0, 20(sp)
+; CHECK-RV32-FD-NEXT:    lw s0, 24(sp)
+; CHECK-RV32-FD-NEXT:    lw ra, 28(sp)
+; CHECK-RV32-FD-NEXT:    addi sp, sp, 32
+; CHECK-RV32-FD-NEXT:    mret
+;
+  %1 = load double, double* @h
+  %2 = load double, double* @i
+  %add = fadd double %1, %2
+  store double %add, double* @g
+  ret void
+}
+
+attributes #0 = { "interrupt"="machine" }
+attributes #1 = { "interrupt"="machine" "no-frame-pointer-elim"="true" }

llvm/trunk/test/CodeGen/RISCV/interrupt-attr-ret-error.ll

+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type!
+define i32 @isr1_user() #0 {
+  ret i32 0
+}
+
+
+attributes #0 = { "interrupt"="user" }

llvm/trunk/test/CodeGen/RISCV/interrupt-attr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-F
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-FD
+;
+; RUN: llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64
+; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-F
+; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f,+d -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD
+
+;
+; Checking for special return instructions (uret, sret, mret).
+;
+define void @foo_user() #0 {
+; CHECK-LABEL: foo_user:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    uret
+  ret void
+}
+
+define void @foo_supervisor() #1 {
+; CHECK-LABEL: foo_supervisor:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sret
+  ret void
+}
+
+define void @foo_machine() #2 {
+; CHECK-LABEL: foo_machine:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mret
+  ret void
+}
+
+;
+; Checking all Caller saved registers (arguments and temps)
+; and FP registers are all saved when the handler calls another function.
+;
+; extern int otherfoo();
+;
+; __attribute__((interrupt)) void foo_with_call() {
+;   otherfoo();
+; }
+;
+
+declare i32 @otherfoo(...)
+define void @foo_with_call() #2 {
+;
+; CHECK-RV32-LABEL: foo_with_call:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -64
+; CHECK-RV32-NEXT:    sw ra, 60(sp)
+; CHECK-RV32-NEXT:    sw t0, 56(sp)
+; CHECK-RV32-NEXT:    sw t1, 52(sp)
+; CHECK-RV32-NEXT:    sw t2, 48(sp)
+; CHECK-RV32-NEXT:    sw a0, 44(sp)
+; CHECK-RV32-NEXT:    sw a1, 40(sp)
+; CHECK-RV32-NEXT:    sw a2, 36(sp)
+; CHECK-RV32-NEXT:    sw a3, 32(sp)
+; CHECK-RV32-NEXT:    sw a4, 28(sp)
+; CHECK-RV32-NEXT:    sw a5, 24(sp)
+; CHECK-RV32-NEXT:    sw a6, 20(sp)
+; CHECK-RV32-NEXT:    sw a7, 16(sp)
+; CHECK-RV32-NEXT:    sw t3, 12(sp)
+; CHECK-RV32-NEXT:    sw t4, 8(sp)
+; CHECK-RV32-NEXT:    sw t5, 4(sp)
+; CHECK-RV32-NEXT:    sw t6, 0(sp)
+; CHECK-RV32-NEXT:    call otherfoo
+; CHECK-RV32-NEXT:    lw t6, 0(sp)
+; CHECK-RV32-NEXT:    lw t5, 4(sp)
+; CHECK-RV32-NEXT:    lw t4, 8(sp)
+; CHECK-RV32-NEXT:    lw t3, 12(sp)
+; CHECK-RV32-NEXT:    lw a7, 16(sp)
+; CHECK-RV32-NEXT:    lw a6, 20(sp)
+; CHECK-RV32-NEXT:    lw a5, 24(sp)
+; CHECK-RV32-NEXT:    lw a4, 28(sp)
+; CHECK-RV32-NEXT:    lw a3, 32(sp)
+; CHECK-RV32-NEXT:    lw a2, 36(sp)
+; CHECK-RV32-NEXT:    lw a1, 40(sp)
+; CHECK-RV32-NEXT:    lw a0, 44(sp)
+; CHECK-RV32-NEXT:    lw t2, 48(sp)
+; CHECK-RV32-NEXT:    lw t1, 52(sp)
+; CHECK-RV32-NEXT:    lw t0, 56(sp)
+; CHECK-RV32-NEXT:    lw ra, 60(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 64
+; CHECK-RV32-NEXT:    mret
+;
+; CHECK-RV32-F-LABEL: foo_with_call:
+; CHECK-RV32-F:       # %bb.0:
+; CHECK-RV32-F-NEXT:    addi sp, sp, -192
+; CHECK-RV32-F-NEXT:    sw ra, 188(sp)
+; CHECK-RV32-F-NEXT:    sw t0, 184(sp)
+; CHECK-RV32-F-NEXT:    sw t1, 180(sp)
+; CHECK-RV32-F-NEXT:    sw t2, 176(sp)
+; CHECK-RV32-F-NEXT:    sw a0, 172(sp)
+; CHECK-RV32-F-NEXT:    sw a1, 168(sp)
+; CHECK-RV32-F-NEXT:    sw a2, 164(sp)
+; CHECK-RV32-F-NEXT:    sw a3, 160(sp)
+; CHECK-RV32-F-NEXT:    sw a4, 156(sp)
+; CHECK-RV32-F-NEXT:    sw a5, 152(sp)
+; CHECK-RV32-F-NEXT:    sw a6, 148(sp)
+; CHECK-RV32-F-NEXT:    sw a7, 144(sp)
+; CHECK-RV32-F-NEXT:    sw t3, 140(sp)
+; CHECK-RV32-F-NEXT:    sw t4, 136(sp)
+; CHECK-RV32-F-NEXT:    sw t5, 132(sp)
+; CHECK-RV32-F-NEXT:    sw t6, 128(sp)
+; CHECK-RV32-F-NEXT:    fsw ft0, 124(sp)
+; CHECK-RV32-F-NEXT:    fsw ft1, 120(sp)
+; CHECK-RV32-F-NEXT:    fsw ft2, 116(sp)
+; CHECK-RV32-F-NEXT:    fsw ft3, 112(sp)
+; CHECK-RV32-F-NEXT:    fsw ft4, 108(sp)
+; CHECK-RV32-F-NEXT:    fsw ft5, 104(sp)
+; CHECK-RV32-F-NEXT:    fsw ft6, 100(sp)
+; CHECK-RV32-F-NEXT:    fsw ft7, 96(sp)
+; CHECK-RV32-F-NEXT:    fsw fa0, 92(sp)
+; CHECK-RV32-F-NEXT:    fsw fa1, 88(sp)
+; CHECK-RV32-F-NEXT:    fsw fa2, 84(sp)
+; CHECK-RV32-F-NEXT:    fsw fa3, 80(sp)
+; CHECK-RV32-F-NEXT:    fsw fa4, 76(sp)
+; CHECK-RV32-F-NEXT:    fsw fa5, 72(sp)
+; CHECK-RV32-F-NEXT:    fsw fa6, 68(sp)
+; CHECK-RV32-F-NEXT:    fsw fa7, 64(sp)
+; CHECK-RV32-F-NEXT:    fsw ft8, 60(sp)
+; CHECK-RV32-F-NEXT:    fsw ft9, 56(sp)
+; CHECK-RV32-F-NEXT:    fsw ft10, 52(sp)
+; CHECK-RV32-F-NEXT:    fsw ft11, 48(sp)
+; CHECK-RV32-F-NEXT:    fsw fs0, 44(sp)
+; CHECK-RV32-F-NEXT:    fsw fs1, 40(sp)
+; CHECK-RV32-F-NEXT:    fsw fs2, 36(sp)
+; CHECK-RV32-F-NEXT:    fsw fs3, 32(sp)
+; CHECK-RV32-F-NEXT:    fsw fs4, 28(sp)
+; CHECK-RV32-F-NEXT:    fsw fs5, 24(sp)
+; CHECK-RV32-F-NEXT:    fsw fs6, 20(sp)
+; CHECK-RV32-F-NEXT:    fsw fs7, 16(sp)
+; CHECK-RV32-F-NEXT:    fsw fs8, 12(sp)
+; CHECK-RV32-F-NEXT:    fsw fs9, 8(sp)
+; CHECK-RV32-F-NEXT:    fsw fs10, 4(sp)
+; CHECK-RV32-F-NEXT:    fsw fs11, 0(sp)
+; CHECK-RV32-F-NEXT:    call otherfoo
+; CHECK-RV32-F-NEXT:    flw fs11, 0(sp)
+; CHECK-RV32-F-NEXT:    flw fs10, 4(sp)
+; CHECK-RV32-F-NEXT:    flw fs9, 8(sp)
+; CHECK-RV32-F-NEXT:    flw fs8, 12(sp)
+; CHECK-RV32-F-NEXT:    flw fs7, 16(sp)
+; CHECK-RV32-F-NEXT:    flw fs6, 20(sp)
+; CHECK-RV32-F-NEXT:    flw fs5, 24(sp)
+; CHECK-RV32-F-NEXT:    flw fs4, 28(sp)
+; CHECK-RV32-F-NEXT:    flw fs3, 32(sp)
+; CHECK-RV32-F-NEXT:    flw fs2, 36(sp)
+; CHECK-RV32-F-NEXT:    flw fs1, 40(sp)
+; CHECK-RV32-F-NEXT:    flw fs0, 44(sp)
+; CHECK-RV32-F-NEXT:    flw ft11, 48(sp)
+; CHECK-RV32-F-NEXT:    flw ft10, 52(sp)
+; CHECK-RV32-F-NEXT:    flw ft9, 56(sp)
+; CHECK-RV32-F-NEXT:    flw ft8, 60(sp)
+; CHECK-RV32-F-NEXT:    flw fa7, 64(sp)
+; CHECK-RV32-F-NEXT:    flw fa6, 68(sp)
+; CHECK-RV32-F-NEXT:    flw fa5, 72(sp)
+; CHECK-RV32-F-NEXT:    flw fa4, 76(sp)
+; CHECK-RV32-F-NEXT:    flw fa3, 80(sp)
+; CHECK-RV32-F-NEXT:    flw fa2, 84(sp)
+; CHECK-RV32-F-NEXT:    flw fa1, 88(sp)
+; CHECK-RV32-F-NEXT:    flw fa0, 92(sp)
+; CHECK-RV32-F-NEXT:    flw ft7, 96(sp)
+; CHECK-RV32-F-NEXT:    flw ft6, 100(sp)
+; CHECK-RV32-F-NEXT:    flw ft5, 104(sp)
+; CHECK-RV32-F-NEXT:    flw ft4, 108(sp)
+; CHECK-RV32-F-NEXT:    flw ft3, 112(sp)
+; CHECK-RV32-F-NEXT:    flw ft2, 116(sp)
+; CHECK-RV32-F-NEXT:    flw ft1, 120(sp)
+; CHECK-RV32-F-NEXT:    flw ft0, 124(sp)
+; CHECK-RV32-F-NEXT:    lw t6, 128(sp)
+; CHECK-RV32-F-NEXT:    lw t5, 132(sp)
+; CHECK-RV32-F-NEXT:    lw t4, 136(sp)
+; CHECK-RV32-F-NEXT:    lw t3, 140(sp)
+; CHECK-RV32-F-NEXT:    lw a7, 144(sp)
+; CHECK-RV32-F-NEXT:    lw a6, 148(sp)
+; CHECK-RV32-F-NEXT:    lw a5, 152(sp)
+; CHECK-RV32-F-NEXT:    lw a4, 156(sp)
+; CHECK-RV32-F-NEXT:    lw a3, 160(sp)
+; CHECK-RV32-F-NEXT:    lw a2, 164(sp)
+; CHECK-RV32-F-NEXT:    lw a1, 168(sp)
+; CHECK-RV32-F-NEXT:    lw a0, 172(sp)
+; CHECK-RV32-F-NEXT:    lw t2, 176(sp)
+; CHECK-RV32-F-NEXT:    lw t1, 180(sp)
+; CHECK-RV32-F-NEXT:    lw t0, 184(sp)
+; CHECK-RV32-F-NEXT:    lw ra, 188(sp)
+; CHECK-RV32-F-NEXT:    addi sp, sp, 192
+; CHECK-RV32-F-NEXT:    mret
+;
+; CHECK-RV32-FD-LABEL: foo_with_call:
+; CHECK-RV32-FD:       # %bb.0:
+; CHECK-RV32-FD-NEXT:    addi sp, sp, -320
+; CHECK-RV32-FD-NEXT:    sw ra, 316(sp)
+; CHECK-RV32-FD-NEXT:    sw t0, 312(sp)
+; CHECK-RV32-FD-NEXT:    sw t1, 308(sp)
+; CHECK-RV32-FD-NEXT:    sw t2, 304(sp)
+; CHECK-RV32-FD-NEXT:    sw a0, 300(sp)
+; CHECK-RV32-FD-NEXT:    sw a1, 296(sp)
+; CHECK-RV32-FD-NEXT:    sw a2, 292(sp)
+; CHECK-RV32-FD-NEXT:    sw a3, 288(sp)
+; CHECK-RV32-FD-NEXT:    sw a4, 284(sp)
+; CHECK-RV32-FD-NEXT:    sw a5, 280(sp)
+; CHECK-RV32-FD-NEXT:    sw a6, 276(sp)
+; CHECK-RV32-FD-NEXT:    sw a7, 272(sp)
+; CHECK-RV32-FD-NEXT:    sw t3, 268(sp)
+; CHECK-RV32-FD-NEXT:    sw t4, 264(sp)
+; CHECK-RV32-FD-NEXT:    sw t5, 260(sp)
+; CHECK-RV32-FD-NEXT:    sw t6, 256(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft0, 248(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft1, 240(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft2, 232(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft3, 224(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft4, 216(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft5, 208(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft6, 200(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft7, 192(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa0, 184(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa1, 176(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa2, 168(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa3, 160(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa4, 152(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa5, 144(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa6, 136(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa7, 128(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft8, 120(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft9, 112(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft10, 104(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft11, 96(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs0, 88(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs1, 80(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs2, 72(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs3, 64(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs4, 56(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs5, 48(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs6, 40(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs7, 32(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs8, 24(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs9, 16(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs10, 8(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs11, 0(sp)
+; CHECK-RV32-FD-NEXT:    call otherfoo
+; CHECK-RV32-FD-NEXT:    fld fs11, 0(sp)
+; CHECK-RV32-FD-NEXT:    fld fs10, 8(sp)
+; CHECK-RV32-FD-NEXT:    fld fs9, 16(sp)
+; CHECK-RV32-FD-NEXT:    fld fs8, 24(sp)
+; CHECK-RV32-FD-NEXT:    fld fs7, 32(sp)
+; CHECK-RV32-FD-NEXT:    fld fs6, 40(sp)
+; CHECK-RV32-FD-NEXT:    fld fs5, 48(sp)
+; CHECK-RV32-FD-NEXT:    fld fs4, 56(sp)
+; CHECK-RV32-FD-NEXT:    fld fs3, 64(sp)
+; CHECK-RV32-FD-NEXT:    fld fs2, 72(sp)
+; CHECK-RV32-FD-NEXT:    fld fs1, 80(sp)
+; CHECK-RV32-FD-NEXT:    fld fs0, 88(sp)
+; CHECK-RV32-FD-NEXT:    fld ft11, 96(sp)
+; CHECK-RV32-FD-NEXT:    fld ft10, 104(sp)
+; CHECK-RV32-FD-NEXT:    fld ft9, 112(sp)
+; CHECK-RV32-FD-NEXT:    fld ft8, 120(sp)
+; CHECK-RV32-FD-NEXT:    fld fa7, 128(sp)
+; CHECK-RV32-FD-NEXT:    fld fa6, 136(sp)
+; CHECK-RV32-FD-NEXT:    fld fa5, 144(sp)
+; CHECK-RV32-FD-NEXT:    fld fa4, 152(sp)
+; CHECK-RV32-FD-NEXT:    fld fa3, 160(sp)
+; CHECK-RV32-FD-NEXT:    fld fa2, 168(sp)
+; CHECK-RV32-FD-NEXT:    fld fa1, 176(sp)
+; CHECK-RV32-FD-NEXT:    fld fa0, 184(sp)
+; CHECK-RV32-FD-NEXT:    fld ft7, 192(sp)
+; CHECK-RV32-FD-NEXT:    fld ft6, 200(sp)
+; CHECK-RV32-FD-NEXT:    fld ft5, 208(sp)
+; CHECK-RV32-FD-NEXT:    fld ft4, 216(sp)
+; CHECK-RV32-FD-NEXT:    fld ft3, 224(sp)
+; CHECK-RV32-FD-NEXT:    fld ft2, 232(sp)
+; CHECK-RV32-FD-NEXT:    fld ft1, 240(sp)
+; CHECK-RV32-FD-NEXT:    fld ft0, 248(sp)
+; CHECK-RV32-FD-NEXT:    lw t6, 256(sp)
+; CHECK-RV32-FD-NEXT:    lw t5, 260(sp)
+; CHECK-RV32-FD-NEXT:    lw t4, 264(sp)
+; CHECK-RV32-FD-NEXT:    lw t3, 268(sp)
+; CHECK-RV32-FD-NEXT:    lw a7, 272(sp)
+; CHECK-RV32-FD-NEXT:    lw a6, 276(sp)
+; CHECK-RV32-FD-NEXT:    lw a5, 280(sp)
+; CHECK-RV32-FD-NEXT:    lw a4, 284(sp)
+; CHECK-RV32-FD-NEXT:    lw a3, 288(sp)
+; CHECK-RV32-FD-NEXT:    lw a2, 292(sp)
+; CHECK-RV32-FD-NEXT:    lw a1, 296(sp)
+; CHECK-RV32-FD-NEXT:    lw a0, 300(sp)
+; CHECK-RV32-FD-NEXT:    lw t2, 304(sp)
+; CHECK-RV32-FD-NEXT:    lw t1, 308(sp)
+; CHECK-RV32-FD-NEXT:    lw t0, 312(sp)
+; CHECK-RV32-FD-NEXT:    lw ra, 316(sp)
+; CHECK-RV32-FD-NEXT:    addi sp, sp, 320
+; CHECK-RV32-FD-NEXT:    mret
+;
+; CHECK-RV64-LABEL: foo_with_call:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    addi sp, sp, -128
+; CHECK-RV64-NEXT:    sd ra, 120(sp)
+; CHECK-RV64-NEXT:    sd t0, 112(sp)
+; CHECK-RV64-NEXT:    sd t1, 104(sp)
+; CHECK-RV64-NEXT:    sd t2, 96(sp)
+; CHECK-RV64-NEXT:    sd a0, 88(sp)
+; CHECK-RV64-NEXT:    sd a1, 80(sp)
+; CHECK-RV64-NEXT:    sd a2, 72(sp)
+; CHECK-RV64-NEXT:    sd a3, 64(sp)
+; CHECK-RV64-NEXT:    sd a4, 56(sp)
+; CHECK-RV64-NEXT:    sd a5, 48(sp)
+; CHECK-RV64-NEXT:    sd a6, 40(sp)
+; CHECK-RV64-NEXT:    sd a7, 32(sp)
+; CHECK-RV64-NEXT:    sd t3, 24(sp)
+; CHECK-RV64-NEXT:    sd t4, 16(sp)
+; CHECK-RV64-NEXT:    sd t5, 8(sp)
+; CHECK-RV64-NEXT:    sd t6, 0(sp)
+; CHECK-RV64-NEXT:    call otherfoo
+; CHECK-RV64-NEXT:    ld t6, 0(sp)
+; CHECK-RV64-NEXT:    ld t5, 8(sp)
+; CHECK-RV64-NEXT:    ld t4, 16(sp)
+; CHECK-RV64-NEXT:    ld t3, 24(sp)
+; CHECK-RV64-NEXT:    ld a7, 32(sp)
+; CHECK-RV64-NEXT:    ld a6, 40(sp)
+; CHECK-RV64-NEXT:    ld a5, 48(sp)
+; CHECK-RV64-NEXT:    ld a4, 56(sp)
+; CHECK-RV64-NEXT:    ld a3, 64(sp)
+; CHECK-RV64-NEXT:    ld a2, 72(sp)
+; CHECK-RV64-NEXT:    ld a1, 80(sp)
+; CHECK-RV64-NEXT:    ld a0, 88(sp)
+; CHECK-RV64-NEXT:    ld t2, 96(sp)
+; CHECK-RV64-NEXT:    ld t1, 104(sp)
+; CHECK-RV64-NEXT:    ld t0, 112(sp)
+; CHECK-RV64-NEXT:    ld ra, 120(sp)
+; CHECK-RV64-NEXT:    addi sp, sp, 128
+; CHECK-RV64-NEXT:    mret
+;
+; CHECK-RV64-F-LABEL: foo_with_call:
+; CHECK-RV64-F:       # %bb.0:
+; CHECK-RV64-F-NEXT:    addi sp, sp, -256
+; CHECK-RV64-F-NEXT:    sd ra, 248(sp)
+; CHECK-RV64-F-NEXT:    sd t0, 240(sp)
+; CHECK-RV64-F-NEXT:    sd t1, 232(sp)
+; CHECK-RV64-F-NEXT:    sd t2, 224(sp)
+; CHECK-RV64-F-NEXT:    sd a0, 216(sp)
+; CHECK-RV64-F-NEXT:    sd a1, 208(sp)
+; CHECK-RV64-F-NEXT:    sd a2, 200(sp)
+; CHECK-RV64-F-NEXT:    sd a3, 192(sp)
+; CHECK-RV64-F-NEXT:    sd a4, 184(sp)
+; CHECK-RV64-F-NEXT:    sd a5, 176(sp)
+; CHECK-RV64-F-NEXT:    sd a6, 168(sp)
+; CHECK-RV64-F-NEXT:    sd a7, 160(sp)
+; CHECK-RV64-F-NEXT:    sd t3, 152(sp)
+; CHECK-RV64-F-NEXT:    sd t4, 144(sp)
+; CHECK-RV64-F-NEXT:    sd t5, 136(sp)
+; CHECK-RV64-F-NEXT:    sd t6, 128(sp)
+; CHECK-RV64-F-NEXT:    fsw ft0, 124(sp)
+; CHECK-RV64-F-NEXT:    fsw ft1, 120(sp)
+; CHECK-RV64-F-NEXT:    fsw ft2, 116(sp)
+; CHECK-RV64-F-NEXT:    fsw ft3, 112(sp)
+; CHECK-RV64-F-NEXT:    fsw ft4, 108(sp)
+; CHECK-RV64-F-NEXT:    fsw ft5, 104(sp)
+; CHECK-RV64-F-NEXT:    fsw ft6, 100(sp)
+; CHECK-RV64-F-NEXT:    fsw ft7, 96(sp)
+; CHECK-RV64-F-NEXT:    fsw fa0, 92(sp)
+; CHECK-RV64-F-NEXT:    fsw fa1, 88(sp)
+; CHECK-RV64-F-NEXT:    fsw fa2, 84(sp)
+; CHECK-RV64-F-NEXT:    fsw fa3, 80(sp)
+; CHECK-RV64-F-NEXT:    fsw fa4, 76(sp)
+; CHECK-RV64-F-NEXT:    fsw fa5, 72(sp)
+; CHECK-RV64-F-NEXT:    fsw fa6, 68(sp)
+; CHECK-RV64-F-NEXT:    fsw fa7, 64(sp)
+; CHECK-RV64-F-NEXT:    fsw ft8, 60(sp)
+; CHECK-RV64-F-NEXT:    fsw ft9, 56(sp)
+; CHECK-RV64-F-NEXT:    fsw ft10, 52(sp)
+; CHECK-RV64-F-NEXT:    fsw ft11, 48(sp)
+; CHECK-RV64-F-NEXT:    fsw fs0, 44(sp)
+; CHECK-RV64-F-NEXT:    fsw fs1, 40(sp)
+; CHECK-RV64-F-NEXT:    fsw fs2, 36(sp)
+; CHECK-RV64-F-NEXT:    fsw fs3, 32(sp)
+; CHECK-RV64-F-NEXT:    fsw fs4, 28(sp)
+; CHECK-RV64-F-NEXT:    fsw fs5, 24(sp)
+; CHECK-RV64-F-NEXT:    fsw fs6, 20(sp)
+; CHECK-RV64-F-NEXT:    fsw fs7, 16(sp)
+; CHECK-RV64-F-NEXT:    fsw fs8, 12(sp)
+; CHECK-RV64-F-NEXT:    fsw fs9, 8(sp)
+; CHECK-RV64-F-NEXT:    fsw fs10, 4(sp)
+; CHECK-RV64-F-NEXT:    fsw fs11, 0(sp)
+; CHECK-RV64-F-NEXT:    call otherfoo
+; CHECK-RV64-F-NEXT:    flw fs11, 0(sp)
+; CHECK-RV64-F-NEXT:    flw fs10, 4(sp)
+; CHECK-RV64-F-NEXT:    flw fs9, 8(sp)
+; CHECK-RV64-F-NEXT:    flw fs8, 12(sp)
+; CHECK-RV64-F-NEXT:    flw fs7, 16(sp)
+; CHECK-RV64-F-NEXT:    flw fs6, 20(sp)
+; CHECK-RV64-F-NEXT:    flw fs5, 24(sp)
+; CHECK-RV64-F-NEXT:    flw fs4, 28(sp)
+; CHECK-RV64-F-NEXT:    flw fs3, 32(sp)
+; CHECK-RV64-F-NEXT:    flw fs2, 36(sp)
+; CHECK-RV64-F-NEXT:    flw fs1, 40(sp)
+; CHECK-RV64-F-NEXT:    flw fs0, 44(sp)
+; CHECK-RV64-F-NEXT:    flw ft11, 48(sp)
+; CHECK-RV64-F-NEXT:    flw ft10, 52(sp)
+; CHECK-RV64-F-NEXT:    flw ft9, 56(sp)
+; CHECK-RV64-F-NEXT:    flw ft8, 60(sp)
+; CHECK-RV64-F-NEXT:    flw fa7, 64(sp)
+; CHECK-RV64-F-NEXT:    flw fa6, 68(sp)
+; CHECK-RV64-F-NEXT:    flw fa5, 72(sp)
+; CHECK-RV64-F-NEXT:    flw fa4, 76(sp)
+; CHECK-RV64-F-NEXT:    flw fa3, 80(sp)
+; CHECK-RV64-F-NEXT:    flw fa2, 84(sp)
+; CHECK-RV64-F-NEXT:    flw fa1, 88(sp)
+; CHECK-RV64-F-NEXT:    flw fa0, 92(sp)
+; CHECK-RV64-F-NEXT:    flw ft7, 96(sp)
+; CHECK-RV64-F-NEXT:    flw ft6, 100(sp)
+; CHECK-RV64-F-NEXT:    flw ft5, 104(sp)
+; CHECK-RV64-F-NEXT:    flw ft4, 108(sp)
+; CHECK-RV64-F-NEXT:    flw ft3, 112(sp)
+; CHECK-RV64-F-NEXT:    flw ft2, 116(sp)
+; CHECK-RV64-F-NEXT:    flw ft1, 120(sp)
+; CHECK-RV64-F-NEXT:    flw ft0, 124(sp)
+; CHECK-RV64-F-NEXT:    ld t6, 128(sp)
+; CHECK-RV64-F-NEXT:    ld t5, 136(sp)
+; CHECK-RV64-F-NEXT:    ld t4, 144(sp)
+; CHECK-RV64-F-NEXT:    ld t3, 152(sp)
+; CHECK-RV64-F-NEXT:    ld a7, 160(sp)
+; CHECK-RV64-F-NEXT:    ld a6, 168(sp)
+; CHECK-RV64-F-NEXT:    ld a5, 176(sp)
+; CHECK-RV64-F-NEXT:    ld a4, 184(sp)
+; CHECK-RV64-F-NEXT:    ld a3, 192(sp)
+; CHECK-RV64-F-NEXT:    ld a2, 200(sp)
+; CHECK-RV64-F-NEXT:    ld a1, 208(sp)
+; CHECK-RV64-F-NEXT:    ld a0, 216(sp)
+; CHECK-RV64-F-NEXT:    ld t2, 224(sp)
+; CHECK-RV64-F-NEXT:    ld t1, 232(sp)
+; CHECK-RV64-F-NEXT:    ld t0, 240(sp)
+; CHECK-RV64-F-NEXT:    ld ra, 248(sp)
+; CHECK-RV64-F-NEXT:    addi sp, sp, 256
+; CHECK-RV64-F-NEXT:    mret
+;
+; CHECK-RV64-FD-LABEL: foo_with_call:
+; CHECK-RV64-FD:       # %bb.0:
+; CHECK-RV64-FD-NEXT:    addi sp, sp, -384
+; CHECK-RV64-FD-NEXT:    sd ra, 376(sp)
+; CHECK-RV64-FD-NEXT:    sd t0, 368(sp)
+; CHECK-RV64-FD-NEXT:    sd t1, 360(sp)
+; CHECK-RV64-FD-NEXT:    sd t2, 352(sp)
+; CHECK-RV64-FD-NEXT:    sd a0, 344(sp)
+; CHECK-RV64-FD-NEXT:    sd a1, 336(sp)
+; CHECK-RV64-FD-NEXT:    sd a2, 328(sp)
+; CHECK-RV64-FD-NEXT:    sd a3, 320(sp)
+; CHECK-RV64-FD-NEXT:    sd a4, 312(sp)
+; CHECK-RV64-FD-NEXT:    sd a5, 304(sp)
+; CHECK-RV64-FD-NEXT:    sd a6, 296(sp)
+; CHECK-RV64-FD-NEXT:    sd a7, 288(sp)
+; CHECK-RV64-FD-NEXT:    sd t3, 280(sp)
+; CHECK-RV64-FD-NEXT:    sd t4, 272(sp)
+; CHECK-RV64-FD-NEXT:    sd t5, 264(sp)
+; CHECK-RV64-FD-NEXT:    sd t6, 256(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft0, 248(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft1, 240(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft2, 232(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft3, 224(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft4, 216(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft5, 208(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft6, 200(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft7, 192(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa0, 184(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa1, 176(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa2, 168(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa3, 160(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa4, 152(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa5, 144(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa6, 136(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa7, 128(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft8, 120(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft9, 112(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft10, 104(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft11, 96(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs0, 88(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs1, 80(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs2, 72(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs3, 64(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs4, 56(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs5, 48(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs6, 40(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs7, 32(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs8, 24(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs9, 16(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs10, 8(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs11, 0(sp)
+; CHECK-RV64-FD-NEXT:    call otherfoo
+; CHECK-RV64-FD-NEXT:    fld fs11, 0(sp)
+; CHECK-RV64-FD-NEXT:    fld fs10, 8(sp)
+; CHECK-RV64-FD-NEXT:    fld fs9, 16(sp)
+; CHECK-RV64-FD-NEXT:    fld fs8, 24(sp)
+; CHECK-RV64-FD-NEXT:    fld fs7, 32(sp)
+; CHECK-RV64-FD-NEXT:    fld fs6, 40(sp)
+; CHECK-RV64-FD-NEXT:    fld fs5, 48(sp)
+; CHECK-RV64-FD-NEXT:    fld fs4, 56(sp)
+; CHECK-RV64-FD-NEXT:    fld fs3, 64(sp)
+; CHECK-RV64-FD-NEXT:    fld fs2, 72(sp)
+; CHECK-RV64-FD-NEXT:    fld fs1, 80(sp)
+; CHECK-RV64-FD-NEXT:    fld fs0, 88(sp)
+; CHECK-RV64-FD-NEXT:    fld ft11, 96(sp)
+; CHECK-RV64-FD-NEXT:    fld ft10, 104(sp)
+; CHECK-RV64-FD-NEXT:    fld ft9, 112(sp)
+; CHECK-RV64-FD-NEXT:    fld ft8, 120(sp)
+; CHECK-RV64-FD-NEXT:    fld fa7, 128(sp)
+; CHECK-RV64-FD-NEXT:    fld fa6, 136(sp)
+; CHECK-RV64-FD-NEXT:    fld fa5, 144(sp)
+; CHECK-RV64-FD-NEXT:    fld fa4, 152(sp)
+; CHECK-RV64-FD-NEXT:    fld fa3, 160(sp)
+; CHECK-RV64-FD-NEXT:    fld fa2, 168(sp)
+; CHECK-RV64-FD-NEXT:    fld fa1, 176(sp)
+; CHECK-RV64-FD-NEXT:    fld fa0, 184(sp)
+; CHECK-RV64-FD-NEXT:    fld ft7, 192(sp)
+; CHECK-RV64-FD-NEXT:    fld ft6, 200(sp)
+; CHECK-RV64-FD-NEXT:    fld ft5, 208(sp)
+; CHECK-RV64-FD-NEXT:    fld ft4, 216(sp)
+; CHECK-RV64-FD-NEXT:    fld ft3, 224(sp)
+; CHECK-RV64-FD-NEXT:    fld ft2, 232(sp)
+; CHECK-RV64-FD-NEXT:    fld ft1, 240(sp)
+; CHECK-RV64-FD-NEXT:    fld ft0, 248(sp)
+; CHECK-RV64-FD-NEXT:    ld t6, 256(sp)
+; CHECK-RV64-FD-NEXT:    ld t5, 264(sp)
+; CHECK-RV64-FD-NEXT:    ld t4, 272(sp)
+; CHECK-RV64-FD-NEXT:    ld t3, 280(sp)
+; CHECK-RV64-FD-NEXT:    ld a7, 288(sp)
+; CHECK-RV64-FD-NEXT:    ld a6, 296(sp)
+; CHECK-RV64-FD-NEXT:    ld a5, 304(sp)
+; CHECK-RV64-FD-NEXT:    ld a4, 312(sp)
+; CHECK-RV64-FD-NEXT:    ld a3, 320(sp)
+; CHECK-RV64-FD-NEXT:    ld a2, 328(sp)
+; CHECK-RV64-FD-NEXT:    ld a1, 336(sp)
+; CHECK-RV64-FD-NEXT:    ld a0, 344(sp)
+; CHECK-RV64-FD-NEXT:    ld t2, 352(sp)
+; CHECK-RV64-FD-NEXT:    ld t1, 360(sp)
+; CHECK-RV64-FD-NEXT:    ld t0, 368(sp)
+; CHECK-RV64-FD-NEXT:    ld ra, 376(sp)
+; CHECK-RV64-FD-NEXT:    addi sp, sp, 384
+; CHECK-RV64-FD-NEXT:    mret
+  %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
+  ret void
+}
+
+;
+; Additionally check frame pointer and return address are properly saved.
+;
+define void @foo_fp_with_call() #3 {
+;
+; CHECK-RV32-LABEL: foo_fp_with_call:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -80
+; CHECK-RV32-NEXT:    sw ra, 76(sp)
+; CHECK-RV32-NEXT:    sw t0, 72(sp)
+; CHECK-RV32-NEXT:    sw t1, 68(sp)
+; CHECK-RV32-NEXT:    sw t2, 64(sp)
+; CHECK-RV32-NEXT:    sw s0, 60(sp)
+; CHECK-RV32-NEXT:    sw a0, 56(sp)
+; CHECK-RV32-NEXT:    sw a1, 52(sp)
+; CHECK-RV32-NEXT:    sw a2, 48(sp)
+; CHECK-RV32-NEXT:    sw a3, 44(sp)
+; CHECK-RV32-NEXT:    sw a4, 40(sp)
+; CHECK-RV32-NEXT:    sw a5, 36(sp)
+; CHECK-RV32-NEXT:    sw a6, 32(sp)
+; CHECK-RV32-NEXT:    sw a7, 28(sp)
+; CHECK-RV32-NEXT:    sw t3, 24(sp)
+; CHECK-RV32-NEXT:    sw t4, 20(sp)
+; CHECK-RV32-NEXT:    sw t5, 16(sp)
+; CHECK-RV32-NEXT:    sw t6, 12(sp)
+; CHECK-RV32-NEXT:    addi s0, sp, 80
+; CHECK-RV32-NEXT:    call otherfoo
+; CHECK-RV32-NEXT:    lw t6, 12(sp)
+; CHECK-RV32-NEXT:    lw t5, 16(sp)
+; CHECK-RV32-NEXT:    lw t4, 20(sp)
+; CHECK-RV32-NEXT:    lw t3, 24(sp)
+; CHECK-RV32-NEXT:    lw a7, 28(sp)
+; CHECK-RV32-NEXT:    lw a6, 32(sp)
+; CHECK-RV32-NEXT:    lw a5, 36(sp)
+; CHECK-RV32-NEXT:    lw a4, 40(sp)
+; CHECK-RV32-NEXT:    lw a3, 44(sp)
+; CHECK-RV32-NEXT:    lw a2, 48(sp)
+; CHECK-RV32-NEXT:    lw a1, 52(sp)
+; CHECK-RV32-NEXT:    lw a0, 56(sp)
+; CHECK-RV32-NEXT:    lw s0, 60(sp)
+; CHECK-RV32-NEXT:    lw t2, 64(sp)
+; CHECK-RV32-NEXT:    lw t1, 68(sp)
+; CHECK-RV32-NEXT:    lw t0, 72(sp)
+; CHECK-RV32-NEXT:    lw ra, 76(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 80
+; CHECK-RV32-NEXT:    mret
+;
+; CHECK-RV32-F-LABEL: foo_fp_with_call:
+; CHECK-RV32-F:       # %bb.0:
+; CHECK-RV32-F-NEXT:    addi sp, sp, -208
+; CHECK-RV32-F-NEXT:    sw ra, 204(sp)
+; CHECK-RV32-F-NEXT:    sw t0, 200(sp)
+; CHECK-RV32-F-NEXT:    sw t1, 196(sp)
+; CHECK-RV32-F-NEXT:    sw t2, 192(sp)
+; CHECK-RV32-F-NEXT:    sw s0, 188(sp)
+; CHECK-RV32-F-NEXT:    sw a0, 184(sp)
+; CHECK-RV32-F-NEXT:    sw a1, 180(sp)
+; CHECK-RV32-F-NEXT:    sw a2, 176(sp)
+; CHECK-RV32-F-NEXT:    sw a3, 172(sp)
+; CHECK-RV32-F-NEXT:    sw a4, 168(sp)
+; CHECK-RV32-F-NEXT:    sw a5, 164(sp)
+; CHECK-RV32-F-NEXT:    sw a6, 160(sp)
+; CHECK-RV32-F-NEXT:    sw a7, 156(sp)
+; CHECK-RV32-F-NEXT:    sw t3, 152(sp)
+; CHECK-RV32-F-NEXT:    sw t4, 148(sp)
+; CHECK-RV32-F-NEXT:    sw t5, 144(sp)
+; CHECK-RV32-F-NEXT:    sw t6, 140(sp)
+; CHECK-RV32-F-NEXT:    fsw ft0, 136(sp)
+; CHECK-RV32-F-NEXT:    fsw ft1, 132(sp)
+; CHECK-RV32-F-NEXT:    fsw ft2, 128(sp)
+; CHECK-RV32-F-NEXT:    fsw ft3, 124(sp)
+; CHECK-RV32-F-NEXT:    fsw ft4, 120(sp)
+; CHECK-RV32-F-NEXT:    fsw ft5, 116(sp)
+; CHECK-RV32-F-NEXT:    fsw ft6, 112(sp)
+; CHECK-RV32-F-NEXT:    fsw ft7, 108(sp)
+; CHECK-RV32-F-NEXT:    fsw fa0, 104(sp)
+; CHECK-RV32-F-NEXT:    fsw fa1, 100(sp)
+; CHECK-RV32-F-NEXT:    fsw fa2, 96(sp)
+; CHECK-RV32-F-NEXT:    fsw fa3, 92(sp)
+; CHECK-RV32-F-NEXT:    fsw fa4, 88(sp)
+; CHECK-RV32-F-NEXT:    fsw fa5, 84(sp)
+; CHECK-RV32-F-NEXT:    fsw fa6, 80(sp)
+; CHECK-RV32-F-NEXT:    fsw fa7, 76(sp)
+; CHECK-RV32-F-NEXT:    fsw ft8, 72(sp)
+; CHECK-RV32-F-NEXT:    fsw ft9, 68(sp)
+; CHECK-RV32-F-NEXT:    fsw ft10, 64(sp)
+; CHECK-RV32-F-NEXT:    fsw ft11, 60(sp)
+; CHECK-RV32-F-NEXT:    fsw fs0, 56(sp)
+; CHECK-RV32-F-NEXT:    fsw fs1, 52(sp)
+; CHECK-RV32-F-NEXT:    fsw fs2, 48(sp)
+; CHECK-RV32-F-NEXT:    fsw fs3, 44(sp)
+; CHECK-RV32-F-NEXT:    fsw fs4, 40(sp)
+; CHECK-RV32-F-NEXT:    fsw fs5, 36(sp)
+; CHECK-RV32-F-NEXT:    fsw fs6, 32(sp)
+; CHECK-RV32-F-NEXT:    fsw fs7, 28(sp)
+; CHECK-RV32-F-NEXT:    fsw fs8, 24(sp)
+; CHECK-RV32-F-NEXT:    fsw fs9, 20(sp)
+; CHECK-RV32-F-NEXT:    fsw fs10, 16(sp)
+; CHECK-RV32-F-NEXT:    fsw fs11, 12(sp)
+; CHECK-RV32-F-NEXT:    addi s0, sp, 208
+; CHECK-RV32-F-NEXT:    call otherfoo
+; CHECK-RV32-F-NEXT:    flw fs11, 12(sp)
+; CHECK-RV32-F-NEXT:    flw fs10, 16(sp)
+; CHECK-RV32-F-NEXT:    flw fs9, 20(sp)
+; CHECK-RV32-F-NEXT:    flw fs8, 24(sp)
+; CHECK-RV32-F-NEXT:    flw fs7, 28(sp)
+; CHECK-RV32-F-NEXT:    flw fs6, 32(sp)
+; CHECK-RV32-F-NEXT:    flw fs5, 36(sp)
+; CHECK-RV32-F-NEXT:    flw fs4, 40(sp)
+; CHECK-RV32-F-NEXT:    flw fs3, 44(sp)
+; CHECK-RV32-F-NEXT:    flw fs2, 48(sp)
+; CHECK-RV32-F-NEXT:    flw fs1, 52(sp)
+; CHECK-RV32-F-NEXT:    flw fs0, 56(sp)
+; CHECK-RV32-F-NEXT:    flw ft11, 60(sp)
+; CHECK-RV32-F-NEXT:    flw ft10, 64(sp)
+; CHECK-RV32-F-NEXT:    flw ft9, 68(sp)
+; CHECK-RV32-F-NEXT:    flw ft8, 72(sp)
+; CHECK-RV32-F-NEXT:    flw fa7, 76(sp)
+; CHECK-RV32-F-NEXT:    flw fa6, 80(sp)
+; CHECK-RV32-F-NEXT:    flw fa5, 84(sp)
+; CHECK-RV32-F-NEXT:    flw fa4, 88(sp)
+; CHECK-RV32-F-NEXT:    flw fa3, 92(sp)
+; CHECK-RV32-F-NEXT:    flw fa2, 96(sp)
+; CHECK-RV32-F-NEXT:    flw fa1, 100(sp)
+; CHECK-RV32-F-NEXT:    flw fa0, 104(sp)
+; CHECK-RV32-F-NEXT:    flw ft7, 108(sp)
+; CHECK-RV32-F-NEXT:    flw ft6, 112(sp)
+; CHECK-RV32-F-NEXT:    flw ft5, 116(sp)
+; CHECK-RV32-F-NEXT:    flw ft4, 120(sp)
+; CHECK-RV32-F-NEXT:    flw ft3, 124(sp)
+; CHECK-RV32-F-NEXT:    flw ft2, 128(sp)
+; CHECK-RV32-F-NEXT:    flw ft1, 132(sp)
+; CHECK-RV32-F-NEXT:    flw ft0, 136(sp)
+; CHECK-RV32-F-NEXT:    lw t6, 140(sp)
+; CHECK-RV32-F-NEXT:    lw t5, 144(sp)
+; CHECK-RV32-F-NEXT:    lw t4, 148(sp)
+; CHECK-RV32-F-NEXT:    lw t3, 152(sp)
+; CHECK-RV32-F-NEXT:    lw a7, 156(sp)
+; CHECK-RV32-F-NEXT:    lw a6, 160(sp)
+; CHECK-RV32-F-NEXT:    lw a5, 164(sp)
+; CHECK-RV32-F-NEXT:    lw a4, 168(sp)
+; CHECK-RV32-F-NEXT:    lw a3, 172(sp)
+; CHECK-RV32-F-NEXT:    lw a2, 176(sp)
+; CHECK-RV32-F-NEXT:    lw a1, 180(sp)
+; CHECK-RV32-F-NEXT:    lw a0, 184(sp)
+; CHECK-RV32-F-NEXT:    lw s0, 188(sp)
+; CHECK-RV32-F-NEXT:    lw t2, 192(sp)
+; CHECK-RV32-F-NEXT:    lw t1, 196(sp)
+; CHECK-RV32-F-NEXT:    lw t0, 200(sp)
+; CHECK-RV32-F-NEXT:    lw ra, 204(sp)
+; CHECK-RV32-F-NEXT:    addi sp, sp, 208
+; CHECK-RV32-F-NEXT:    mret
+;
+; CHECK-RV32-FD-LABEL: foo_fp_with_call:
+; CHECK-RV32-FD:       # %bb.0:
+; CHECK-RV32-FD-NEXT:    addi sp, sp, -336
+; CHECK-RV32-FD-NEXT:    sw ra, 332(sp)
+; CHECK-RV32-FD-NEXT:    sw t0, 328(sp)
+; CHECK-RV32-FD-NEXT:    sw t1, 324(sp)
+; CHECK-RV32-FD-NEXT:    sw t2, 320(sp)
+; CHECK-RV32-FD-NEXT:    sw s0, 316(sp)
+; CHECK-RV32-FD-NEXT:    sw a0, 312(sp)
+; CHECK-RV32-FD-NEXT:    sw a1, 308(sp)
+; CHECK-RV32-FD-NEXT:    sw a2, 304(sp)
+; CHECK-RV32-FD-NEXT:    sw a3, 300(sp)
+; CHECK-RV32-FD-NEXT:    sw a4, 296(sp)
+; CHECK-RV32-FD-NEXT:    sw a5, 292(sp)
+; CHECK-RV32-FD-NEXT:    sw a6, 288(sp)
+; CHECK-RV32-FD-NEXT:    sw a7, 284(sp)
+; CHECK-RV32-FD-NEXT:    sw t3, 280(sp)
+; CHECK-RV32-FD-NEXT:    sw t4, 276(sp)
+; CHECK-RV32-FD-NEXT:    sw t5, 272(sp)
+; CHECK-RV32-FD-NEXT:    sw t6, 268(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft0, 256(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft1, 248(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft2, 240(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft3, 232(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft4, 224(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft5, 216(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft6, 208(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft7, 200(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa0, 192(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa1, 184(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa2, 176(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa3, 168(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa4, 160(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa5, 152(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa6, 144(sp)
+; CHECK-RV32-FD-NEXT:    fsd fa7, 136(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft8, 128(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft9, 120(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft10, 112(sp)
+; CHECK-RV32-FD-NEXT:    fsd ft11, 104(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs0, 96(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs1, 88(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs2, 80(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs3, 72(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs4, 64(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs5, 56(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs6, 48(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs7, 40(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs8, 32(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs9, 24(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs10, 16(sp)
+; CHECK-RV32-FD-NEXT:    fsd fs11, 8(sp)
+; CHECK-RV32-FD-NEXT:    addi s0, sp, 336
+; CHECK-RV32-FD-NEXT:    call otherfoo
+; CHECK-RV32-FD-NEXT:    fld fs11, 8(sp)
+; CHECK-RV32-FD-NEXT:    fld fs10, 16(sp)
+; CHECK-RV32-FD-NEXT:    fld fs9, 24(sp)
+; CHECK-RV32-FD-NEXT:    fld fs8, 32(sp)
+; CHECK-RV32-FD-NEXT:    fld fs7, 40(sp)
+; CHECK-RV32-FD-NEXT:    fld fs6, 48(sp)
+; CHECK-RV32-FD-NEXT:    fld fs5, 56(sp)
+; CHECK-RV32-FD-NEXT:    fld fs4, 64(sp)
+; CHECK-RV32-FD-NEXT:    fld fs3, 72(sp)
+; CHECK-RV32-FD-NEXT:    fld fs2, 80(sp)
+; CHECK-RV32-FD-NEXT:    fld fs1, 88(sp)
+; CHECK-RV32-FD-NEXT:    fld fs0, 96(sp)
+; CHECK-RV32-FD-NEXT:    fld ft11, 104(sp)
+; CHECK-RV32-FD-NEXT:    fld ft10, 112(sp)
+; CHECK-RV32-FD-NEXT:    fld ft9, 120(sp)
+; CHECK-RV32-FD-NEXT:    fld ft8, 128(sp)
+; CHECK-RV32-FD-NEXT:    fld fa7, 136(sp)
+; CHECK-RV32-FD-NEXT:    fld fa6, 144(sp)
+; CHECK-RV32-FD-NEXT:    fld fa5, 152(sp)
+; CHECK-RV32-FD-NEXT:    fld fa4, 160(sp)
+; CHECK-RV32-FD-NEXT:    fld fa3, 168(sp)
+; CHECK-RV32-FD-NEXT:    fld fa2, 176(sp)
+; CHECK-RV32-FD-NEXT:    fld fa1, 184(sp)
+; CHECK-RV32-FD-NEXT:    fld fa0, 192(sp)
+; CHECK-RV32-FD-NEXT:    fld ft7, 200(sp)
+; CHECK-RV32-FD-NEXT:    fld ft6, 208(sp)
+; CHECK-RV32-FD-NEXT:    fld ft5, 216(sp)
+; CHECK-RV32-FD-NEXT:    fld ft4, 224(sp)
+; CHECK-RV32-FD-NEXT:    fld ft3, 232(sp)
+; CHECK-RV32-FD-NEXT:    fld ft2, 240(sp)
+; CHECK-RV32-FD-NEXT:    fld ft1, 248(sp)
+; CHECK-RV32-FD-NEXT:    fld ft0, 256(sp)
+; CHECK-RV32-FD-NEXT:    lw t6, 268(sp)
+; CHECK-RV32-FD-NEXT:    lw t5, 272(sp)
+; CHECK-RV32-FD-NEXT:    lw t4, 276(sp)
+; CHECK-RV32-FD-NEXT:    lw t3, 280(sp)
+; CHECK-RV32-FD-NEXT:    lw a7, 284(sp)
+; CHECK-RV32-FD-NEXT:    lw a6, 288(sp)
+; CHECK-RV32-FD-NEXT:    lw a5, 292(sp)
+; CHECK-RV32-FD-NEXT:    lw a4, 296(sp)
+; CHECK-RV32-FD-NEXT:    lw a3, 300(sp)
+; CHECK-RV32-FD-NEXT:    lw a2, 304(sp)
+; CHECK-RV32-FD-NEXT:    lw a1, 308(sp)
+; CHECK-RV32-FD-NEXT:    lw a0, 312(sp)
+; CHECK-RV32-FD-NEXT:    lw s0, 316(sp)
+; CHECK-RV32-FD-NEXT:    lw t2, 320(sp)
+; CHECK-RV32-FD-NEXT:    lw t1, 324(sp)
+; CHECK-RV32-FD-NEXT:    lw t0, 328(sp)
+; CHECK-RV32-FD-NEXT:    lw ra, 332(sp)
+; CHECK-RV32-FD-NEXT:    addi sp, sp, 336
+; CHECK-RV32-FD-NEXT:    mret
+;
+; CHECK-RV64-LABEL: foo_fp_with_call:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    addi sp, sp, -144
+; CHECK-RV64-NEXT:    sd ra, 136(sp)
+; CHECK-RV64-NEXT:    sd t0, 128(sp)
+; CHECK-RV64-NEXT:    sd t1, 120(sp)
+; CHECK-RV64-NEXT:    sd t2, 112(sp)
+; CHECK-RV64-NEXT:    sd s0, 104(sp)
+; CHECK-RV64-NEXT:    sd a0, 96(sp)
+; CHECK-RV64-NEXT:    sd a1, 88(sp)
+; CHECK-RV64-NEXT:    sd a2, 80(sp)
+; CHECK-RV64-NEXT:    sd a3, 72(sp)
+; CHECK-RV64-NEXT:    sd a4, 64(sp)
+; CHECK-RV64-NEXT:    sd a5, 56(sp)
+; CHECK-RV64-NEXT:    sd a6, 48(sp)
+; CHECK-RV64-NEXT:    sd a7, 40(sp)
+; CHECK-RV64-NEXT:    sd t3, 32(sp)
+; CHECK-RV64-NEXT:    sd t4, 24(sp)
+; CHECK-RV64-NEXT:    sd t5, 16(sp)
+; CHECK-RV64-NEXT:    sd t6, 8(sp)
+; CHECK-RV64-NEXT:    addi s0, sp, 144
+; CHECK-RV64-NEXT:    call otherfoo
+; CHECK-RV64-NEXT:    ld t6, 8(sp)
+; CHECK-RV64-NEXT:    ld t5, 16(sp)
+; CHECK-RV64-NEXT:    ld t4, 24(sp)
+; CHECK-RV64-NEXT:    ld t3, 32(sp)
+; CHECK-RV64-NEXT:    ld a7, 40(sp)
+; CHECK-RV64-NEXT:    ld a6, 48(sp)
+; CHECK-RV64-NEXT:    ld a5, 56(sp)
+; CHECK-RV64-NEXT:    ld a4, 64(sp)
+; CHECK-RV64-NEXT:    ld a3, 72(sp)
+; CHECK-RV64-NEXT:    ld a2, 80(sp)
+; CHECK-RV64-NEXT:    ld a1, 88(sp)
+; CHECK-RV64-NEXT:    ld a0, 96(sp)
+; CHECK-RV64-NEXT:    ld s0, 104(sp)
+; CHECK-RV64-NEXT:    ld t2, 112(sp)
+; CHECK-RV64-NEXT:    ld t1, 120(sp)
+; CHECK-RV64-NEXT:    ld t0, 128(sp)
+; CHECK-RV64-NEXT:    ld ra, 136(sp)
+; CHECK-RV64-NEXT:    addi sp, sp, 144
+; CHECK-RV64-NEXT:    mret
+;
+; CHECK-RV64-F-LABEL: foo_fp_with_call:
+; CHECK-RV64-F:       # %bb.0:
+; CHECK-RV64-F-NEXT:    addi sp, sp, -272
+; CHECK-RV64-F-NEXT:    sd ra, 264(sp)
+; CHECK-RV64-F-NEXT:    sd t0, 256(sp)
+; CHECK-RV64-F-NEXT:    sd t1, 248(sp)
+; CHECK-RV64-F-NEXT:    sd t2, 240(sp)
+; CHECK-RV64-F-NEXT:    sd s0, 232(sp)
+; CHECK-RV64-F-NEXT:    sd a0, 224(sp)
+; CHECK-RV64-F-NEXT:    sd a1, 216(sp)
+; CHECK-RV64-F-NEXT:    sd a2, 208(sp)
+; CHECK-RV64-F-NEXT:    sd a3, 200(sp)
+; CHECK-RV64-F-NEXT:    sd a4, 192(sp)
+; CHECK-RV64-F-NEXT:    sd a5, 184(sp)
+; CHECK-RV64-F-NEXT:    sd a6, 176(sp)
+; CHECK-RV64-F-NEXT:    sd a7, 168(sp)
+; CHECK-RV64-F-NEXT:    sd t3, 160(sp)
+; CHECK-RV64-F-NEXT:    sd t4, 152(sp)
+; CHECK-RV64-F-NEXT:    sd t5, 144(sp)
+; CHECK-RV64-F-NEXT:    sd t6, 136(sp)
+; CHECK-RV64-F-NEXT:    fsw ft0, 132(sp)
+; CHECK-RV64-F-NEXT:    fsw ft1, 128(sp)
+; CHECK-RV64-F-NEXT:    fsw ft2, 124(sp)
+; CHECK-RV64-F-NEXT:    fsw ft3, 120(sp)
+; CHECK-RV64-F-NEXT:    fsw ft4, 116(sp)
+; CHECK-RV64-F-NEXT:    fsw ft5, 112(sp)
+; CHECK-RV64-F-NEXT:    fsw ft6, 108(sp)
+; CHECK-RV64-F-NEXT:    fsw ft7, 104(sp)
+; CHECK-RV64-F-NEXT:    fsw fa0, 100(sp)
+; CHECK-RV64-F-NEXT:    fsw fa1, 96(sp)
+; CHECK-RV64-F-NEXT:    fsw fa2, 92(sp)
+; CHECK-RV64-F-NEXT:    fsw fa3, 88(sp)
+; CHECK-RV64-F-NEXT:    fsw fa4, 84(sp)
+; CHECK-RV64-F-NEXT:    fsw fa5, 80(sp)
+; CHECK-RV64-F-NEXT:    fsw fa6, 76(sp)
+; CHECK-RV64-F-NEXT:    fsw fa7, 72(sp)
+; CHECK-RV64-F-NEXT:    fsw ft8, 68(sp)
+; CHECK-RV64-F-NEXT:    fsw ft9, 64(sp)
+; CHECK-RV64-F-NEXT:    fsw ft10, 60(sp)
+; CHECK-RV64-F-NEXT:    fsw ft11, 56(sp)
+; CHECK-RV64-F-NEXT:    fsw fs0, 52(sp)
+; CHECK-RV64-F-NEXT:    fsw fs1, 48(sp)
+; CHECK-RV64-F-NEXT:    fsw fs2, 44(sp)
+; CHECK-RV64-F-NEXT:    fsw fs3, 40(sp)
+; CHECK-RV64-F-NEXT:    fsw fs4, 36(sp)
+; CHECK-RV64-F-NEXT:    fsw fs5, 32(sp)
+; CHECK-RV64-F-NEXT:    fsw fs6, 28(sp)
+; CHECK-RV64-F-NEXT:    fsw fs7, 24(sp)
+; CHECK-RV64-F-NEXT:    fsw fs8, 20(sp)
+; CHECK-RV64-F-NEXT:    fsw fs9, 16(sp)
+; CHECK-RV64-F-NEXT:    fsw fs10, 12(sp)
+; CHECK-RV64-F-NEXT:    fsw fs11, 8(sp)
+; CHECK-RV64-F-NEXT:    addi s0, sp, 272
+; CHECK-RV64-F-NEXT:    call otherfoo
+; CHECK-RV64-F-NEXT:    flw fs11, 8(sp)
+; CHECK-RV64-F-NEXT:    flw fs10, 12(sp)
+; CHECK-RV64-F-NEXT:    flw fs9, 16(sp)
+; CHECK-RV64-F-NEXT:    flw fs8, 20(sp)
+; CHECK-RV64-F-NEXT:    flw fs7, 24(sp)
+; CHECK-RV64-F-NEXT:    flw fs6, 28(sp)
+; CHECK-RV64-F-NEXT:    flw fs5, 32(sp)
+; CHECK-RV64-F-NEXT:    flw fs4, 36(sp)
+; CHECK-RV64-F-NEXT:    flw fs3, 40(sp)
+; CHECK-RV64-F-NEXT:    flw fs2, 44(sp)
+; CHECK-RV64-F-NEXT:    flw fs1, 48(sp)
+; CHECK-RV64-F-NEXT:    flw fs0, 52(sp)
+; CHECK-RV64-F-NEXT:    flw ft11, 56(sp)
+; CHECK-RV64-F-NEXT:    flw ft10, 60(sp)
+; CHECK-RV64-F-NEXT:    flw ft9, 64(sp)
+; CHECK-RV64-F-NEXT:    flw ft8, 68(sp)
+; CHECK-RV64-F-NEXT:    flw fa7, 72(sp)
+; CHECK-RV64-F-NEXT:    flw fa6, 76(sp)
+; CHECK-RV64-F-NEXT:    flw fa5, 80(sp)
+; CHECK-RV64-F-NEXT:    flw fa4, 84(sp)
+; CHECK-RV64-F-NEXT:    flw fa3, 88(sp)
+; CHECK-RV64-F-NEXT:    flw fa2, 92(sp)
+; CHECK-RV64-F-NEXT:    flw fa1, 96(sp)
+; CHECK-RV64-F-NEXT:    flw fa0, 100(sp)
+; CHECK-RV64-F-NEXT:    flw ft7, 104(sp)
+; CHECK-RV64-F-NEXT:    flw ft6, 108(sp)
+; CHECK-RV64-F-NEXT:    flw ft5, 112(sp)
+; CHECK-RV64-F-NEXT:    flw ft4, 116(sp)
+; CHECK-RV64-F-NEXT:    flw ft3, 120(sp)
+; CHECK-RV64-F-NEXT:    flw ft2, 124(sp)
+; CHECK-RV64-F-NEXT:    flw ft1, 128(sp)
+; CHECK-RV64-F-NEXT:    flw ft0, 132(sp)
+; CHECK-RV64-F-NEXT:    ld t6, 136(sp)
+; CHECK-RV64-F-NEXT:    ld t5, 144(sp)
+; CHECK-RV64-F-NEXT:    ld t4, 152(sp)
+; CHECK-RV64-F-NEXT:    ld t3, 160(sp)
+; CHECK-RV64-F-NEXT:    ld a7, 168(sp)
+; CHECK-RV64-F-NEXT:    ld a6, 176(sp)
+; CHECK-RV64-F-NEXT:    ld a5, 184(sp)
+; CHECK-RV64-F-NEXT:    ld a4, 192(sp)
+; CHECK-RV64-F-NEXT:    ld a3, 200(sp)
+; CHECK-RV64-F-NEXT:    ld a2, 208(sp)
+; CHECK-RV64-F-NEXT:    ld a1, 216(sp)
+; CHECK-RV64-F-NEXT:    ld a0, 224(sp)
+; CHECK-RV64-F-NEXT:    ld s0, 232(sp)
+; CHECK-RV64-F-NEXT:    ld t2, 240(sp)
+; CHECK-RV64-F-NEXT:    ld t1, 248(sp)
+; CHECK-RV64-F-NEXT:    ld t0, 256(sp)
+; CHECK-RV64-F-NEXT:    ld ra, 264(sp)
+; CHECK-RV64-F-NEXT:    addi sp, sp, 272
+; CHECK-RV64-F-NEXT:    mret
+;
+; CHECK-RV64-FD-LABEL: foo_fp_with_call:
+; CHECK-RV64-FD:       # %bb.0:
+; CHECK-RV64-FD-NEXT:    addi sp, sp, -400
+; CHECK-RV64-FD-NEXT:    sd ra, 392(sp)
+; CHECK-RV64-FD-NEXT:    sd t0, 384(sp)
+; CHECK-RV64-FD-NEXT:    sd t1, 376(sp)
+; CHECK-RV64-FD-NEXT:    sd t2, 368(sp)
+; CHECK-RV64-FD-NEXT:    sd s0, 360(sp)
+; CHECK-RV64-FD-NEXT:    sd a0, 352(sp)
+; CHECK-RV64-FD-NEXT:    sd a1, 344(sp)
+; CHECK-RV64-FD-NEXT:    sd a2, 336(sp)
+; CHECK-RV64-FD-NEXT:    sd a3, 328(sp)
+; CHECK-RV64-FD-NEXT:    sd a4, 320(sp)
+; CHECK-RV64-FD-NEXT:    sd a5, 312(sp)
+; CHECK-RV64-FD-NEXT:    sd a6, 304(sp)
+; CHECK-RV64-FD-NEXT:    sd a7, 296(sp)
+; CHECK-RV64-FD-NEXT:    sd t3, 288(sp)
+; CHECK-RV64-FD-NEXT:    sd t4, 280(sp)
+; CHECK-RV64-FD-NEXT:    sd t5, 272(sp)
+; CHECK-RV64-FD-NEXT:    sd t6, 264(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft0, 256(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft1, 248(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft2, 240(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft3, 232(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft4, 224(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft5, 216(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft6, 208(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft7, 200(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa0, 192(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa1, 184(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa2, 176(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa3, 168(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa4, 160(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa5, 152(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa6, 144(sp)
+; CHECK-RV64-FD-NEXT:    fsd fa7, 136(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft8, 128(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft9, 120(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft10, 112(sp)
+; CHECK-RV64-FD-NEXT:    fsd ft11, 104(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs0, 96(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs1, 88(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs2, 80(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs3, 72(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs4, 64(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs5, 56(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs6, 48(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs7, 40(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs8, 32(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs9, 24(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs10, 16(sp)
+; CHECK-RV64-FD-NEXT:    fsd fs11, 8(sp)
+; CHECK-RV64-FD-NEXT:    addi s0, sp, 400
+; CHECK-RV64-FD-NEXT:    call otherfoo
+; CHECK-RV64-FD-NEXT:    fld fs11, 8(sp)
+; CHECK-RV64-FD-NEXT:    fld fs10, 16(sp)
+; CHECK-RV64-FD-NEXT:    fld fs9, 24(sp)
+; CHECK-RV64-FD-NEXT:    fld fs8, 32(sp)
+; CHECK-RV64-FD-NEXT:    fld fs7, 40(sp)
+; CHECK-RV64-FD-NEXT:    fld fs6, 48(sp)
+; CHECK-RV64-FD-NEXT:    fld fs5, 56(sp)
+; CHECK-RV64-FD-NEXT:    fld fs4, 64(sp)
+; CHECK-RV64-FD-NEXT:    fld fs3, 72(sp)
+; CHECK-RV64-FD-NEXT:    fld fs2, 80(sp)
+; CHECK-RV64-FD-NEXT:    fld fs1, 88(sp)
+; CHECK-RV64-FD-NEXT:    fld fs0, 96(sp)
+; CHECK-RV64-FD-NEXT:    fld ft11, 104(sp)
+; CHECK-RV64-FD-NEXT:    fld ft10, 112(sp)
+; CHECK-RV64-FD-NEXT:    fld ft9, 120(sp)
+; CHECK-RV64-FD-NEXT:    fld ft8, 128(sp)
+; CHECK-RV64-FD-NEXT:    fld fa7, 136(sp)
+; CHECK-RV64-FD-NEXT:    fld fa6, 144(sp)
+; CHECK-RV64-FD-NEXT:    fld fa5, 152(sp)
+; CHECK-RV64-FD-NEXT:    fld fa4, 160(sp)
+; CHECK-RV64-FD-NEXT:    fld fa3, 168(sp)
+; CHECK-RV64-FD-NEXT:    fld fa2, 176(sp)
+; CHECK-RV64-FD-NEXT:    fld fa1, 184(sp)
+; CHECK-RV64-FD-NEXT:    fld fa0, 192(sp)
+; CHECK-RV64-FD-NEXT:    fld ft7, 200(sp)
+; CHECK-RV64-FD-NEXT:    fld ft6, 208(sp)
+; CHECK-RV64-FD-NEXT:    fld ft5, 216(sp)
+; CHECK-RV64-FD-NEXT:    fld ft4, 224(sp)
+; CHECK-RV64-FD-NEXT:    fld ft3, 232(sp)
+; CHECK-RV64-FD-NEXT:    fld ft2, 240(sp)
+; CHECK-RV64-FD-NEXT:    fld ft1, 248(sp)
+; CHECK-RV64-FD-NEXT:    fld ft0, 256(sp)
+; CHECK-RV64-FD-NEXT:    ld t6, 264(sp)
+; CHECK-RV64-FD-NEXT:    ld t5, 272(sp)
+; CHECK-RV64-FD-NEXT:    ld t4, 280(sp)
+; CHECK-RV64-FD-NEXT:    ld t3, 288(sp)
+; CHECK-RV64-FD-NEXT:    ld a7, 296(sp)
+; CHECK-RV64-FD-NEXT:    ld a6, 304(sp)
+; CHECK-RV64-FD-NEXT:    ld a5, 312(sp)
+; CHECK-RV64-FD-NEXT:    ld a4, 320(sp)
+; CHECK-RV64-FD-NEXT:    ld a3, 328(sp)
+; CHECK-RV64-FD-NEXT:    ld a2, 336(sp)
+; CHECK-RV64-FD-NEXT:    ld a1, 344(sp)
+; CHECK-RV64-FD-NEXT:    ld a0, 352(sp)
+; CHECK-RV64-FD-NEXT:    ld s0, 360(sp)
+; CHECK-RV64-FD-NEXT:    ld t2, 368(sp)
+; CHECK-RV64-FD-NEXT:    ld t1, 376(sp)
+; CHECK-RV64-FD-NEXT:    ld t0, 384(sp)
+; CHECK-RV64-FD-NEXT:    ld ra, 392(sp)
+; CHECK-RV64-FD-NEXT:    addi sp, sp, 400
+; CHECK-RV64-FD-NEXT:    mret
+  %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
+  ret void
+}
+
+attributes #0 = { "interrupt"="user" }
+attributes #1 = { "interrupt"="supervisor" }
+attributes #2 = { "interrupt"="machine" }
+attributes #3 = { "interrupt"="machine" "no-frame-pointer-elim"="true" }