[mips] Sign extend i32 return values on MIPS64

[smaksimovic]

Summary

Override getTypeForExtReturn so that functions returning an i32 typed value have it sign extended on MIPS64.
Also provide patterns to get rid of unneeded sign extensions for arithmetic instructions which implicitly sign extend their results.

[atanasyan]

LGTM

[smaksimovic]

Forgot to mark this explicitly as still being WIP, since we are missing sign extensions at some places.

test/CodeGen/Mips/llvm-ir/or.ll

111

For example here.
What is happening is that the already extended arguments which are operands to the 32 bit OR enable the operation to be transformed to a 64 bit OR through series of combines done at SimplifyBinOpWithSameOpcodeHands in DAGCombiner.cpp.
This in turn renders the sign_extend node introduced as a parent to the 64 bit OR unneeded so it gets removed, which leads to SLL instruction not being generated.

Likewise for the xor.ll test.

[smaksimovic]

Added target hooks to replace the sign_extend with the sign_extend_inreg node which will get pattern matched with the SLL64_64 thus providing the needed sign extension.
The second target hook is introduced to keep the sign_extend_inreg node from being combined away.

[efriedma]

include/llvm/CodeGen/TargetLowering.h

2140

Is this required for correctness? If it is, then the MIPS target is lying to DAGCombine somehow, and this fix is just papering over the bug. Otherwise, I can't see how keeping around a redundant SIGN_EXTEND_INREG would make the generated code more efficient.

[efriedma]

test/CodeGen/Mips/llvm-ir/or.ll

111

The sign extension here is redundant, I think: if x and y both have N sign bits, x | y also has N sign bits.

[smaksimovic]

include/llvm/CodeGen/TargetLowering.h

2140

The sole purpose of that function, and keeping the SIGN_EXTEND_INREG node alive, is so that it could be later matched with this pattern:

def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
              (SLL64_64 GPR64:$src)>;

As an example, SelectionDAG for the or_i32 function which resides in the or.ll test file:

t0: ch = EntryToken
          t2: i64,ch = CopyFromReg t0, Register:i64 %0
        t4: i64 = AssertSext t2, ValueType:ch:i32
      t5: i32 = truncate t4
          t7: i64,ch = CopyFromReg t0, Register:i64 %1
        t8: i64 = AssertSext t7, ValueType:ch:i32
      t9: i32 = truncate t8
    t10: i32 = or t5, t9
  t11: i64 = sign_extend t10
t13: ch,glue = CopyToReg t0, Register:i64 $v0_64, t11
t14: ch = MipsISD::Ret t13, Register:i64 $v0_64, t13:1

gets eventually transformed to this (including the sign_extend_inreg node incorporated by this patch):

t0: ch = EntryToken
        t2: i64,ch = CopyFromReg t0, Register:i64 %0
      t4: i64 = AssertSext t2, ValueType:ch:i32
        t7: i64,ch = CopyFromReg t0, Register:i64 %1
      t8: i64 = AssertSext t7, ValueType:ch:i32
    t15: i64 = or t4, t8
  t17: i64 = sign_extend_inreg t15, ValueType:ch:i32
t13: ch,glue = CopyToReg t0, Register:i64 $v0_64, t17
t14: ch = MipsISD::Ret t13, Register:i64 $v0_64, t13:1

In place of sign_extend_inreg node would be the sign_extend node, which would be removed the same way the sign_extend_inreg would.
Hence the keepSextInRegNode function to keep it until it can be pattern matched and replaced with the target dependent machine node.
I completely agree that its existence is indeed questionable, looking at the code above by itself.
However I have not found a better way to go about this change.

[efriedma]

include/llvm/CodeGen/TargetLowering.h

2140

I don't understand: why do you want to generate a redundant "sll" instruction?

[smaksimovic]

include/llvm/CodeGen/TargetLowering.h

2140

Its purpose in this case is to sign extend the return value of a function, specifically i32 on MIPS64. At the moment that is not the case, even if the i32 return value is marked with the signext attribute.
On MIPS, only the arithmetic instructions implicitly sign extend their results so we need to keep the sll instruction which does the extend for other operations prior to returning.

[efriedma]

include/llvm/CodeGen/TargetLowering.h

2140

I don't mean "why do you want to generate an sll instruction in general"; I follow that part. I mean, "why do you want to generate a redundant sll instruction in your example"? "i64 = or t4, t8" is already appropriately sign-extended.

[smaksimovic]

include/llvm/CodeGen/TargetLowering.h

2140

Ah, I see, there was a misunderstanding on my part.
I was under the impression, given the statement above regarding the arithmetic instructions and such, that I needed to sign extend the non-arithmetic ones unconditionally. Even in the example above the arguments to the operation were implicitly sign extended by the caller thus there is no need to additionally sign extend the result, as you noted. I'll revert this patch to the previous version.

[smaksimovic]

Revert patch back to the previous version.

[atanasyan]

Is the patch in WIP state now?

[smaksimovic]

Not anymore, I'd like to have it reviewed.
I rolled it back to the version similar to the one you reviewed initially.

[atanasyan]

LGTM

include/llvm/CodeGen/TargetLowering.h

public:
   virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
     return false;
   }
 
   virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
     return false;
   }
 
+  /// Return true if the target is to keep the SIGN_EXTEND from being combined
+  /// in certain conditions.
+  virtual bool keepSextNode(SDNode* N, SelectionDAG &DAG, const SDLoc &DL,
+                            const SDValue &Op, unsigned DestBits) const {
+    return false;
+  }
+  /// Return true if the target is to keep the SIGN_EXTEND_INREG from being
+  /// combined in certain conditions.
+  virtual bool keepSextInRegNode(EVT VT) const {
+    return false;
+  }
+
   /// Return true if the target supplies and combines to a paired load
   /// two loaded values of type LoadedType next to each other in memory.
   /// RequiredAlignment gives the minimal alignment constraints that must be met
   /// to be able to select this paired load.
   ///
   /// This information is *not* used to generate actual paired loads, but it is
   /// used to generate a sequence of loads that is easier to combine into a
   /// paired load.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N0.getOpcode() == ISD::TRUNCATE) {
     // eliminate the trunc/sext pair.
     SDValue Op = N0.getOperand(0);
     unsigned OpBits   = Op.getScalarValueSizeInBits();
     unsigned MidBits  = N0.getScalarValueSizeInBits();
     unsigned DestBits = VT.getScalarSizeInBits();
     unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
 
     if (OpBits == DestBits) {
+      if (TLI.keepSextNode(N, DAG, DL, Op, DestBits))
+        return SDValue(N, 0);
       // Op is i32, Mid is i8, and Dest is i32.  If Op has more than 24 sign
       // bits, it is already ready.
       if (NumSignBits > DestBits-MidBits)
         return Op;
     } else if (OpBits < DestBits) {
       // Op is i32, Mid is i8, and Dest is i64.  If Op has more than 24 sign
       // bits, just sext from i32.
       if (NumSignBits > OpBits-MidBits)
SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   if (N0.isUndef())
     return DAG.getUNDEF(VT);
 
   // fold (sext_in_reg c1) -> c1
   if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
     return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
 
   // If the input is already sign extended, just drop the extension.
-  if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
+  if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) {
+    if (TLI.keepSextInRegNode(VT))
+      return SDValue(N, 0);
+    else
       return N0;
+  }
 
   // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
   if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
       EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
     return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
                        N0.getOperand(0), N1);
 
   // fold (sext_in_reg (sext x)) -> (sext x)

lib/Target/Mips/Mips64InstrInfo.td

 def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>;
 
 // Atomic store patterns.
 def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>;
 def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>;
 def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>;
 def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>;
 
+// Patterns used for matching away redundant sign extensions.
+// MIPS32 arithmetic instructions sign extend their result implicitly.
+def : MipsPat<(i64 (sext (i32 (add GPR32:$src, immSExt16:$imm16)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (ADDiu GPR32:$src, immSExt16:$imm16), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (add GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (ADDu GPR32:$src, GPR32:$src2), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (SUBu GPR32:$src, GPR32:$src2), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (MUL GPR32:$src, GPR32:$src2), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (PseudoMFHI ACC64:$src), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (MipsMFLO ACC64:$src)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (PseudoMFLO ACC64:$src), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (SLLV GPR32:$src, GPR32:$src2), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (SRLV GPR32:$src, GPR32:$src2), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
+def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (SRAV GPR32:$src, GPR32:$src2), sub_32)>;
+
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
 let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<"move $dst, $src",
                       (OR64 GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
         GPR_64;
   def : MipsInstAlias<"move $dst, $src",

lib/Target/Mips/Mips64r6InstrInfo.td

def : MipsPat<(select i32:$cond, immz, i64:$f),
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
               (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
               ISA_MIPS64R6;
 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
               (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
               ISA_MIPS64R6;
 
+// Patterns used for matching away redundant sign extensions.
+// MIPS32 arithmetic instructions sign extend their result implicitly.
+def : MipsPat<(i64 (sext (i32 (sdiv GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (DIV GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
+def : MipsPat<(i64 (sext (i32 (udiv GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (DIVU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
+def : MipsPat<(i64 (sext (i32 (srem GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (MOD GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
+def : MipsPat<(i64 (sext (i32 (urem GPR32:$src, GPR32:$src2)))),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
+              (MODU GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6;
+
 // Pseudo instructions
 
 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
                             NoIndirectJumpGuards] in {
   def TAILCALL64R6REG : TailCallRegR6<JALR64, ZERO_64, GPR64Opnd>, ISA_MIPS64R6;
   def PseudoIndirectBranch64R6 : PseudoIndirectBranchBaseR6<JALR64, ZERO_64,
                                                             GPR64Opnd>,
                                  ISA_MIPS64R6;

lib/Target/Mips/MipsISelLowering.h

public:
     /// or null if the target does not support "fast" ISel.
     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
                              const TargetLibraryInfo *libInfo) const override;
 
     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
       return MVT::i32;
     }
 
+    EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
+                            ISD::NodeType) const override;
+    
+    bool keepSextNode(SDNode* N, SelectionDAG &DAG, const SDLoc &DL,
+                      const SDValue &Op, unsigned DestBits) const override;
+    
+    bool keepSextInRegNode(EVT VT) const override;
+
     bool isCheapToSpeculateCttz() const override;
     bool isCheapToSpeculateCtlz() const override;
 
     /// Return the register type for a given MVT, ensuring vectors are treated
     /// as a series of gpr sized integers.
     MVT getRegisterTypeForCallingConv(LLVMContext &Context,
                                       EVT VT) const override;
 

lib/Target/Mips/MipsISelLowering.cpp

static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
   if (I == E)
     return std::make_pair(true, false);
 
   // Parse the numeric characters.
   return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
                         true);
 }
 
+EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
+                                            ISD::NodeType) const {
+  bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
+  EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32);
+  return VT.bitsLT(MinVT) ? MinVT : VT;
+}
+
+bool MipsTargetLowering::keepSextNode(SDNode* N, SelectionDAG &DAG,
+                                      const SDLoc &DL, const SDValue &Op,
+                                      unsigned DestBits) const {
+  if (DestBits != 64 || ABI.IsO32())
+    return false;
+  SDValue InRegNode = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, Op,
+                                  DAG.getValueType(MVT::i32));
+  DAG.ReplaceAllUsesWith(N, &InRegNode);
+  return true;
+}
+    
+bool MipsTargetLowering::keepSextInRegNode(EVT VT) const {
+  return VT == MVT::i64;
+}
+
 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
   const TargetRegisterInfo *TRI =
       Subtarget.getRegisterInfo();
   const TargetRegisterClass *RC;
   StringRef Prefix;
   unsigned long long Reg;
 

test/CodeGen/Mips/delay-slot-kill.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
-; We have to XFAIL this temporarily because of the reversion of r229675.
-; XFAIL: *
 
 ; Currently, the following IR assembly generates a KILL instruction between
 ; the bitwise-and instruction and the return instruction. We verify that the
 ; delay slot filler ignores such KILL instructions by filling the slot of the
 ; return instruction properly.
 define signext i32 @f1(i32 signext %a, i32 signext %b) {
 entry:
-  ; CHECK:          jr      $ra
-  ; CHECK-NEXT:     and     $2, $4, $5
+  ; CHECK:          and     $1, $4, $5
+  ; CHECK-NEXT:     jr      $ra
+  ; CHECK-NEXT:     sll     $2, $1, 0
 
   %r = and i32 %a, %b
   ret i32 %r
 }

test/CodeGen/Mips/llvm-ir/not.ll

 }
 
 define signext i32 @not_i32(i32 signext %a) {
 entry:
 ; ALL-LABEL: not_i32:
 
   ; GP32:         not     $2, $4
 
-  ; GP64:         not     $2, $4
+  ; GP64:         not     $1, $4
+  ; GP64:         sll     $2, $1, 0
 
   ; MM:           not16   $2, $4
 
   %r = xor i32 %a, -1
   ret i32 %r
 }
 
 define signext i64 @not_i64(i64 signext %a) {

 define signext i32 @nor_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: nor_i32:
 
   ; GP32:         nor     $2, $5, $4
 
   ; GP64:         or      $[[T0:[0-9]+]], $5, $4
   ; GP64:         sll     $[[T1:[0-9]+]], $[[T0]], 0
-  ; GP64:         not     $2, $[[T1]]
+  ; GP64:         not     $[[T2:[0-9]+]], $[[T1]]
+  ; GP64:         sll     $2, $[[T2]], 0
 
   ; MM32:         nor     $2, $5, $4
 
   %or = or i32 %b, %a
   %r = xor i32 %or, -1
   ret i32 %r
 }
 

test/CodeGen/Mips/llvm-ir/or.ll

 ; GP32:       # %bb.0: # %entry
 ; GP32-NEXT:    jr $ra
 ; GP32-NEXT:    or $2, $4, $5
 ;
 ; GP64-LABEL: or_i32:
 ; GP64:       # %bb.0: # %entry
 ; GP64-NEXT:    or $1, $4, $5
 ; GP64-NEXT:    jr $ra
 ; GP64-NEXT:    sll $2, $1, 0
 ;
 ; MM32-LABEL: or_i32:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    or16 $4, $5
 ; MM32-NEXT:    move $2, $4
 ; MM32-NEXT:    jrc $ra
 ;
 ; MM32R6-LABEL: or_i32:

 define signext i32 @or_i32_4(i32 signext %b) {
 ; GP32-LABEL: or_i32_4:
 ; GP32:       # %bb.0: # %entry
 ; GP32-NEXT:    jr $ra
 ; GP32-NEXT:    ori $2, $4, 4
 ;
 ; GP64-LABEL: or_i32_4:
 ; GP64:       # %bb.0: # %entry
+; GP64-NEXT:    ori $1, $4, 4
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    ori $2, $4, 4
+; GP64-NEXT:    sll $2, $1, 0
 ;
 ; MM32-LABEL: or_i32_4:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    jr $ra
 ; MM32-NEXT:    ori $2, $4, 4
 ;
 ; MM32R6-LABEL: or_i32_4:
 ; MM32R6:       # %bb.0: # %entry

 define signext i32 @or_i32_31(i32 signext %b) {
 ; GP32-LABEL: or_i32_31:
 ; GP32:       # %bb.0: # %entry
 ; GP32-NEXT:    jr $ra
 ; GP32-NEXT:    ori $2, $4, 31
 ;
 ; GP64-LABEL: or_i32_31:
 ; GP64:       # %bb.0: # %entry
+; GP64-NEXT:    ori $1, $4, 31
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    ori $2, $4, 31
+; GP64-NEXT:    sll $2, $1, 0
 ;
 ; MM32-LABEL: or_i32_31:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    jr $ra
 ; MM32-NEXT:    ori $2, $4, 31
 ;
 ; MM32R6-LABEL: or_i32_31:
 ; MM32R6:       # %bb.0: # %entry

 define signext i32 @or_i32_255(i32 signext %b) {
 ; GP32-LABEL: or_i32_255:
 ; GP32:       # %bb.0: # %entry
 ; GP32-NEXT:    jr $ra
 ; GP32-NEXT:    ori $2, $4, 255
 ;
 ; GP64-LABEL: or_i32_255:
 ; GP64:       # %bb.0: # %entry
+; GP64-NEXT:    ori $1, $4, 255
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    ori $2, $4, 255
+; GP64-NEXT:    sll $2, $1, 0
 ;
 ; MM32-LABEL: or_i32_255:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    jr $ra
 ; MM32-NEXT:    ori $2, $4, 255
 ;
 ; MM32R6-LABEL: or_i32_255:
 ; MM32R6:       # %bb.0: # %entry

 define signext i32 @or_i32_32768(i32 signext %b) {
 ; GP32-LABEL: or_i32_32768:
 ; GP32:       # %bb.0: # %entry
 ; GP32-NEXT:    jr $ra
 ; GP32-NEXT:    ori $2, $4, 32768
 ;
 ; GP64-LABEL: or_i32_32768:
 ; GP64:       # %bb.0: # %entry
+; GP64-NEXT:    ori $1, $4, 32768
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    ori $2, $4, 32768
+; GP64-NEXT:    sll $2, $1, 0
 ;
 ; MM32-LABEL: or_i32_32768:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    jr $ra
 ; MM32-NEXT:    ori $2, $4, 32768
 ;
 ; MM32R6-LABEL: or_i32_32768:
 ; MM32R6:       # %bb.0: # %entry

 define signext i32 @or_i32_65(i32 signext %b) {
 ; GP32-LABEL: or_i32_65:
 ; GP32:       # %bb.0: # %entry
 ; GP32-NEXT:    jr $ra
 ; GP32-NEXT:    ori $2, $4, 65
 ;
 ; GP64-LABEL: or_i32_65:
 ; GP64:       # %bb.0: # %entry
+; GP64-NEXT:    ori $1, $4, 65
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    ori $2, $4, 65
+; GP64-NEXT:    sll $2, $1, 0
 ;
 ; MM32-LABEL: or_i32_65:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    jr $ra
 ; MM32-NEXT:    ori $2, $4, 65
 ;
 ; MM32R6-LABEL: or_i32_65:
 ; MM32R6:       # %bb.0: # %entry

 define signext i32 @or_i32_256(i32 signext %b) {
 ; GP32-LABEL: or_i32_256:
 ; GP32:       # %bb.0: # %entry
 ; GP32-NEXT:    jr $ra
 ; GP32-NEXT:    ori $2, $4, 256
 ;
 ; GP64-LABEL: or_i32_256:
 ; GP64:       # %bb.0: # %entry
+; GP64-NEXT:    ori $1, $4, 256
 ; GP64-NEXT:    jr $ra
-; GP64-NEXT:    ori $2, $4, 256
+; GP64-NEXT:    sll $2, $1, 0
 ;
 ; MM32-LABEL: or_i32_256:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    jr $ra
 ; MM32-NEXT:    ori $2, $4, 256
 ;
 ; MM32R6-LABEL: or_i32_256:
 ; MM32R6:       # %bb.0: # %entry

test/CodeGen/Mips/llvm-ir/select-int.ll

entry:
 
   ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
   ; M2:     bnez    $[[T0]], [[BB0:\$BB[0-9_]+]]
   ; M3:     bnez    $[[T0]], [[BB0:\.LBB[0-9_]+]]
   ; M2-M3:  nop
   ; M2-M3:  move    $5, $6
   ; M2-M3:  [[BB0]]:
   ; M2-M3:  jr      $ra
-  ; M2-M3:  move    $2, $5
+  ; M3:     sll     $2, $5, 0
 
   ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV:   movn    $6, $5, $[[T0]]
-  ; CMOV:   move    $2, $6
+  ; CMOV-64:sll     $2, $6, 0
 
   ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
   ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
-  ; SEL:    or      $2, $[[T2]], $[[T1]]
+  ; SEL:    or      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; SEL-64: sll     $2, $[[T3]], 0
 
   ; MM32R3:     andi16  $[[T0:[0-9]+]], $4, 1
   ; MM32R3:     movn    $[[T1:[0-9]+]], $5, $[[T0]]  # <MCInst #{{[0-9]+}} MOVN_I_MM
   ; MM32R3:     move    $2, $[[T1]]
 
   ; MMR6:       andi16  $[[T0:[0-9]+]], $4, 1
   ; MMR6:       seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; MMR6:       selnez  $[[T2:[0-9]+]], $5, $[[T0]]

test/CodeGen/Mips/llvm-ir/xor.ll

 ;
 ; MIPS32R6-LABEL: xor_i32_4:
 ; MIPS32R6:       # %bb.0: # %entry
 ; MIPS32R6-NEXT:    jr $ra
 ; MIPS32R6-NEXT:    xori $2, $4, 4
 ;
 ; MIPS64-LABEL: xor_i32_4:
 ; MIPS64:       # %bb.0: # %entry
+; MIPS64-NEXT:    xori $1, $4, 4
 ; MIPS64-NEXT:    jr $ra
-; MIPS64-NEXT:    xori $2, $4, 4
+; MIPS64-NEXT:    sll $2, $1, 0
 ;
 ; MIPS64R2-LABEL: xor_i32_4:
 ; MIPS64R2:       # %bb.0: # %entry
+; MIPS64R2-NEXT:    xori $1, $4, 4
 ; MIPS64R2-NEXT:    jr $ra
-; MIPS64R2-NEXT:    xori $2, $4, 4
+; MIPS64R2-NEXT:    sll $2, $1, 0
 ;
 ; MIPS64R6-LABEL: xor_i32_4:
 ; MIPS64R6:       # %bb.0: # %entry
+; MIPS64R6-NEXT:    xori $1, $4, 4
 ; MIPS64R6-NEXT:    jr $ra
-; MIPS64R6-NEXT:    xori $2, $4, 4
+; MIPS64R6-NEXT:    sll $2, $1, 0
 ;
 ; MM32R3-LABEL: xor_i32_4:
 ; MM32R3:       # %bb.0: # %entry
 ; MM32R3-NEXT:    jr $ra
 ; MM32R3-NEXT:    xori $2, $4, 4
 ;
 ; MM32R6-LABEL: xor_i32_4:
 ; MM32R6:       # %bb.0: # %entry

test/CodeGen/Mips/shrink-wrapping.ll

 ; SHRINK-WRAP-64-STATIC:       # %bb.0: # %entry
 ; SHRINK-WRAP-64-STATIC-NEXT:    beqz $4, .LBB0_2
 ; SHRINK-WRAP-64-STATIC-NEXT:    nop
 ; SHRINK-WRAP-64-STATIC-NEXT:  # %bb.1: # %if.end
 ; SHRINK-WRAP-64-STATIC-NEXT:    daddiu $sp, $sp, -16
 ; SHRINK-WRAP-64-STATIC-NEXT:    .cfi_def_cfa_offset 16
 ; SHRINK-WRAP-64-STATIC-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; SHRINK-WRAP-64-STATIC-NEXT:    .cfi_offset 31, -8
-; SHRINK-WRAP-64-STATIC-NEXT:    addiu $1, $4, 1
 ; SHRINK-WRAP-64-STATIC-NEXT:    jal f
-; SHRINK-WRAP-64-STATIC-NEXT:    sll $4, $1, 0
+; SHRINK-WRAP-64-STATIC-NEXT:    addiu $4, $4, 1
 ; SHRINK-WRAP-64-STATIC-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
 ; SHRINK-WRAP-64-STATIC-NEXT:    daddiu $sp, $sp, 16
 ; SHRINK-WRAP-64-STATIC-NEXT:  .LBB0_2: # %return
 ; SHRINK-WRAP-64-STATIC-NEXT:    jr $ra
 ; SHRINK-WRAP-64-STATIC-NEXT:    addiu $2, $zero, 0
 ;
 ; NO-SHRINK-WRAP-64-STATIC-LABEL: foo:
 ; NO-SHRINK-WRAP-64-STATIC:       # %bb.0: # %entry
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    daddiu $sp, $sp, -16
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    .cfi_def_cfa_offset 16
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    .cfi_offset 31, -8
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    beqz $4, .LBB0_2
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    nop
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:  # %bb.1: # %if.end
-; NO-SHRINK-WRAP-64-STATIC-NEXT:    addiu $1, $4, 1
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    jal f
-; NO-SHRINK-WRAP-64-STATIC-NEXT:    sll $4, $1, 0
+; NO-SHRINK-WRAP-64-STATIC-NEXT:    addiu $4, $4, 1
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:  .LBB0_2: # %return
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    addiu $2, $zero, 0
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    jr $ra
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    daddiu $sp, $sp, 16
 ;
 ; SHRINK-WRAP-64-PIC-LABEL: foo:
 ; SHRINK-WRAP-64-PIC:       # %bb.0: # %entry
 ; SHRINK-WRAP-64-PIC-NEXT:    lui $1, %hi(%neg(%gp_rel(foo)))
 ; SHRINK-WRAP-64-PIC-NEXT:    beqz $4, .LBB0_2
 ; SHRINK-WRAP-64-PIC-NEXT:    daddu $2, $1, $25
 ; SHRINK-WRAP-64-PIC-NEXT:  # %bb.1: # %if.end
 ; SHRINK-WRAP-64-PIC-NEXT:    daddiu $sp, $sp, -16
 ; SHRINK-WRAP-64-PIC-NEXT:    .cfi_def_cfa_offset 16
 ; SHRINK-WRAP-64-PIC-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; SHRINK-WRAP-64-PIC-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
 ; SHRINK-WRAP-64-PIC-NEXT:    .cfi_offset 31, -8
 ; SHRINK-WRAP-64-PIC-NEXT:    .cfi_offset 28, -16
 ; SHRINK-WRAP-64-PIC-NEXT:    daddiu $gp, $2, %lo(%neg(%gp_rel(foo)))
-; SHRINK-WRAP-64-PIC-NEXT:    addiu $1, $4, 1
 ; SHRINK-WRAP-64-PIC-NEXT:    ld $25, %call16(f)($gp)
 ; SHRINK-WRAP-64-PIC-NEXT:    jalr $25
-; SHRINK-WRAP-64-PIC-NEXT:    sll $4, $1, 0
+; SHRINK-WRAP-64-PIC-NEXT:    addiu $4, $4, 1
 ; SHRINK-WRAP-64-PIC-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
 ; SHRINK-WRAP-64-PIC-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
 ; SHRINK-WRAP-64-PIC-NEXT:    daddiu $sp, $sp, 16
 ; SHRINK-WRAP-64-PIC-NEXT:  .LBB0_2: # %return
 ; SHRINK-WRAP-64-PIC-NEXT:    jr $ra
 ; SHRINK-WRAP-64-PIC-NEXT:    addiu $2, $zero, 0
 ;
 ; NO-SHRINK-WRAP-64-PIC-LABEL: foo:
 ; NO-SHRINK-WRAP-64-PIC:       # %bb.0: # %entry
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    daddiu $sp, $sp, -16
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    .cfi_def_cfa_offset 16
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    .cfi_offset 31, -8
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    .cfi_offset 28, -16
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    lui $1, %hi(%neg(%gp_rel(foo)))
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    beqz $4, .LBB0_2
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    daddu $2, $1, $25
 ; NO-SHRINK-WRAP-64-PIC-NEXT:  # %bb.1: # %if.end
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    daddiu $gp, $2, %lo(%neg(%gp_rel(foo)))
-; NO-SHRINK-WRAP-64-PIC-NEXT:    addiu $1, $4, 1
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    ld $25, %call16(f)($gp)
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    jalr $25
-; NO-SHRINK-WRAP-64-PIC-NEXT:    sll $4, $1, 0
+; NO-SHRINK-WRAP-64-PIC-NEXT:    addiu $4, $4, 1
 ; NO-SHRINK-WRAP-64-PIC-NEXT:  .LBB0_2: # %return
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    addiu $2, $zero, 0
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    ld $gp, 0($sp) # 8-byte Folded Reload
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    jr $ra
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    daddiu $sp, $sp, 16
 entry:
   %cmp = icmp eq i32 %a, 0