[AArch64][SVE] Implement copying for Z registers

[huntergr]

Summary

Implements copying for scalable vector registers using the "orr"
instruction.

Part of the initial SVE codegen series, rfc will be posted soon. Note: this patch is currently just to support the scalable vector codegen rfc, and does not need a full review yet.

[huntergr]

Superseded by D66302

lib/Target/AArch64/AArch64InstrInfo.cpp

void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (SrcReg == AArch64::NZCV) {
     assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
     BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg)
         .addImm(AArch64SysReg::NZCV)
         .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
     return;
   }
 
+  if (AArch64::ZPRRegClass.contains(DestReg) &&
+      AArch64::ZPRRegClass.contains(SrcReg)) {
+    assert(Subtarget.hasSVE() && "Unexpected SVE register.");
+    BuildMI(MBB, I, DL, get(AArch64::ORR_ZZZ), DestReg)
+      .addReg(SrcReg)
+      .addReg(SrcReg, getKillRegState(KillSrc));
+    return;
+  }
+
   llvm_unreachable("unimplemented reg-to-reg copy");
 }
 
 void AArch64InstrInfo::storeRegToStackSlot(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
     bool isKill, int FI, const TargetRegisterClass *RC,
     const TargetRegisterInfo *TRI) const {
   DebugLoc DL;