Current implementation of c.cond.fmt instructions only accept default cc0 register. This patch enables the instruction to accept other fcc registers. The aliases with default fcc0 registers are also defined.
Details
Details
Diff Detail
Diff Detail
Event Timeline
| lib/Target/Mips/MipsInstrFPU.td | ||
|---|---|---|
| 235 | Given that CC is always FCCRegsOpnd do we really need it to be an argument? I think we could just use it directly. | |
| 264 | You need to update ISA_MIPS* adverbs. Support for multiple $fcc registers was added in MIPS-IV and MIPS32. Prior to that only the form without $fcc registers was permitted. | |
| 273 | Nit: space after comma | |
| lib/Target/Mips/MipsInstrFPU.td | ||
|---|---|---|
| 235 | This was introduced to enable alias definitions that use FCC0 as a default value. | |
| 264 | That would mean that we need two separated definitions for c.cond.fmt instructions, one for Mips-IV and Mips32 that allows $fcc registers and one for prior architectures that doesn't. Is that right? | |
| lib/Target/Mips/MipsInstrFPU.td | ||
|---|---|---|
| 235 | I mean the argument for the class not the operand. Your definition will look like this: class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, InstrItinClass itin> :
InstSE<(outs), (ins FCCRegOpnd:$cc, RC:$fs, RC:$ft),
!strconcat("c.", CondStr, ".", Typestr, "\t $cc, $fs, $ft"),
[], itin, FrmFR>; | |
| 264 | You should only need the definitions you have now but with corrected adverbs. It's possible to have an InstAlias enabled even when the Instruction it aliases is disabled. | |
Comment Actions
Changed instruction definition to use FCCRegsOpnd in base class. Changed predicates for instruction and aliases.
Comment Actions
LGTM with a whitespace nit. Could you align the start of the operands to match the neighbouring instructions in each of the test files?
It's not necessary for this commit but we ought to start checking that the encodings are correct soon. Most instructions only test that the parser accepts the syntax at the moment
Comment Actions
This patch fixes the failing tests that caused the initial patch to be reverted. Instruction formats for assembler and code gen versions of conditional instructions have been separated, so at the moment fcc0-fcc7 registers are allowed for assembler while on code gen it will be still fixed to fcc0.
Comment Actions
A bug in the previous version of the patch has been fixed. Disassembler tests are added, and corresponding cases from xfailed tests removed.
Given that CC is always FCCRegsOpnd do we really need it to be an argument? I think we could just use it directly.