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Differential D4776

Add fcc registers to c.cond.fmt instruction definition.
Needs ReviewPublic

Authored by vmedic on Aug 4 2014, 6:40 AM.

Details

Reviewers
sstankovic
zoran.jovanovic
dsanders
Summary

Current implementation of c.cond.fmt instructions only accept default cc0 register. This patch enables the instruction to accept other fcc registers. The aliases with default fcc0 registers are also defined.

Diff Detail

Event Timeline

vmedic updated this revision to Diff 12157.Aug 4 2014, 6:40 AM
vmedic retitled this revision from to Add fcc registers to c.cond.fmt instruction definition..
vmedic updated this object.
vmedic edited the test plan for this revision. (Show Details)
vmedic added reviewers: dsanders, zoran.jovanovic.
vmedic changed the visibility from "Public (No Login Required)" to "Custom Policy".
vmedic changed the visibility from "Custom Policy" to "Public (No Login Required)".Aug 6 2014, 3:05 AM
dsanders added inline comments.Aug 11 2014, 2:42 AM
lib/Target/Mips/MipsInstrFPU.td
235

Given that CC is always FCCRegsOpnd do we really need it to be an argument? I think we could just use it directly.

264

You need to update ISA_MIPS* adverbs. Support for multiple $fcc registers was added in MIPS-IV and MIPS32. Prior to that only the form without $fcc registers was permitted.

273

Nit: space after comma

vmedic added inline comments.Aug 11 2014, 3:13 AM
lib/Target/Mips/MipsInstrFPU.td
235

This was introduced to enable alias definitions that use FCC0 as a default value.

264

That would mean that we need two separated definitions for c.cond.fmt instructions, one for Mips-IV and Mips32 that allows $fcc registers and one for prior architectures that doesn't. Is that right?

dsanders added inline comments.Aug 11 2014, 3:59 AM
lib/Target/Mips/MipsInstrFPU.td
235

I mean the argument for the class not the operand. Your definition will look like this:

class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, InstrItinClass itin>  :
   InstSE<(outs), (ins FCCRegOpnd:$cc, RC:$fs, RC:$ft),
          !strconcat("c.", CondStr, ".", Typestr, "\t $cc, $fs, $ft"),
          [], itin, FrmFR>;
264

You should only need the definitions you have now but with corrected adverbs. It's possible to have an InstAlias enabled even when the Instruction it aliases is disabled.

vmedic updated this revision to Diff 12447.Aug 13 2014, 7:20 AM

Changed instruction definition to use FCCRegsOpnd in base class. Changed predicates for instruction and aliases.

dsanders accepted this revision.Aug 13 2014, 12:52 PM
dsanders edited edge metadata.

LGTM with a whitespace nit. Could you align the start of the operands to match the neighbouring instructions in each of the test files?

It's not necessary for this commit but we ought to start checking that the encodings are correct soon. Most instructions only test that the parser accepts the syntax at the moment

This revision is now accepted and ready to land.Aug 13 2014, 12:52 PM
vmedic updated this revision to Diff 14445.Oct 6 2014, 4:33 AM
vmedic added a reviewer: sstankovic.

This patch fixes the failing tests that caused the initial patch to be reverted. Instruction formats for assembler and code gen versions of conditional instructions have been separated, so at the moment fcc0-fcc7 registers are allowed for assembler while on code gen it will be still fixed to fcc0.

vmedic planned changes to this revision.Jan 26 2015, 9:20 AM

Revision reverted, changes required.

vmedic updated this revision to Diff 18893.Jan 28 2015, 8:39 AM
vmedic added a subscriber: Unknown Object (MLST).

A bug in the previous version of the patch has been fixed. Disassembler tests are added, and corresponding cases from xfailed tests removed.

This revision is now accepted and ready to land.Jan 28 2015, 8:39 AM
vmedic requested a review of this revision.Feb 4 2015, 6:08 AM
vmedic edited edge metadata.
dsanders resigned from this revision.Jul 18 2019, 7:01 PM
Herald added subscribers: atanasyan, sdardis. · View Herald TranscriptJul 18 2019, 7:01 PM

Revision Contents

PathSize
lib/
Target/
Mips/
69 lines
24 lines
test/
MC/
Disassembler/
Mips/
mips32/
28 lines
28 lines
mips32r2/
28 lines
28 lines
28 lines
mips4/
28 lines
29 lines
28 lines
mips64/
28 lines
28 lines
28 lines
mips64r2/
28 lines
28 lines
28 lines
Mips/
mips32/
28 lines
28 lines
mips32r2/
58 lines
28 lines
mips4/
28 lines
28 lines
mips5/
28 lines
28 lines
mips64/
28 lines
28 lines
mips64r2/
28 lines
28 lines

Diff 18893

lib/Target/Mips/MipsInstrFPU.td

Context not available.
defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
AdditionalRequires<[IsFP64bit]>; AdditionalRequires<[IsFP64bit]>;
class C_COND_FT_CC<string CondStr, string Typestr,
RegisterOperand RC, InstrItinClass itin> :
InstSE<(outs), (ins FCCRegsOpnd:$cc, RC:$fs, RC:$ft),
!strconcat("c.", CondStr, ".", Typestr, "\t $cc, $fs, $ft"),
[], itin, FrmFR>;
dsandersUnsubmitted
Not Done
ReplyInline Actions

Nit: space after comma

dsanders: Nit: space after comma
multiclass C_COND_M_CC<string TypeStr, RegisterOperand RC, bits<5> fmt,
InstrItinClass itin> {
def C_F_#NAME : C_COND_FT_CC<"f", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 0>;
def C_UN_#NAME : C_COND_FT_CC<"un", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 1>;
def C_EQ_#NAME : C_COND_FT_CC<"eq", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 2>;
def C_UEQ_#NAME : C_COND_FT_CC<"ueq", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 3>;
def C_OLT_#NAME : C_COND_FT_CC<"olt", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 4>;
def C_ULT_#NAME : C_COND_FT_CC<"ult", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 5>;
def C_OLE_#NAME : C_COND_FT_CC<"ole", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 6>;
def C_ULE_#NAME : C_COND_FT_CC<"ule", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 7>;
def C_SF_#NAME : C_COND_FT_CC<"sf", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 8>;
def C_NGLE_#NAME : C_COND_FT_CC<"ngle", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 9>;
def C_SEQ_#NAME : C_COND_FT_CC<"seq", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 10>;
def C_NGL_#NAME : C_COND_FT_CC<"ngl", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 11>;
def C_LT_#NAME : C_COND_FT_CC<"lt", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 12>;
def C_NGE_#NAME : C_COND_FT_CC<"nge", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 13>;
def C_LE_#NAME : C_COND_FT_CC<"le", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 14>;
def C_NGT_#NAME : C_COND_FT_CC<"ngt", TypeStr, RC, itin>, C_COND_FM_CC<fmt, 15>;
}
defm S_CC : C_COND_M_CC<"s", FGR32Opnd, 16, II_C_CC_S>, INSN_MIPS4_32_NOT_32R6_64R6;
defm D32_CC : C_COND_M_CC<"d", AFGR64Opnd, 17, II_C_CC_D>, INSN_MIPS4_32_NOT_32R6_64R6,
AdditionalRequires<[NotFP64bit]>;
let DecoderNamespace = "Mips64" in
defm D64_CC : C_COND_M_CC<"d", FGR64Opnd, 17, II_C_CC_D>, INSN_MIPS4_32_NOT_32R6_64R6,
AdditionalRequires<[IsFP64bit]>;
class CCInstAlias<string CondStr, string TypeStr, dag Result>:
MipsInstAlias<!strconcat("c.", CondStr, ".", TypeStr, "\t $fs, $ft"),
Result>, INSN_MIPS4_32_NOT_32R6_64R6;
multiclass CCondInstAlias<string CondStr,
Instruction CondS, Instruction CondD32,
Instruction CondD64> {
def : CCInstAlias<CondStr, "s",
(CondS FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft )>;
def : CCInstAlias<CondStr, "d" ,
(CondD32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft )>,
AdditionalRequires<[NotFP64bit]>;
def : CCInstAlias<CondStr, "d",
(CondD64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft )>,
AdditionalRequires<[IsFP64bit]>;
}
defm : CCondInstAlias<"f", C_F_S_CC, C_F_D32_CC, C_F_D64_CC>;
defm : CCondInstAlias<"un", C_UN_S_CC, C_UN_D32_CC, C_UN_D64_CC>;
defm : CCondInstAlias<"eq", C_EQ_S_CC, C_EQ_D32_CC, C_EQ_D64_CC>;
defm : CCondInstAlias<"ueq", C_UEQ_S_CC, C_UEQ_D32_CC, C_UEQ_D64_CC>;
defm : CCondInstAlias<"olt", C_OLT_S_CC, C_OLT_D32_CC, C_OLT_D64_CC>;
defm : CCondInstAlias<"ult", C_ULT_S_CC, C_ULT_D32_CC, C_ULT_D64_CC>;
defm : CCondInstAlias<"ole", C_OLE_S_CC, C_OLE_D32_CC, C_OLE_D64_CC>;
defm : CCondInstAlias<"ule", C_ULE_S_CC, C_ULE_D32_CC, C_ULE_D64_CC>;
defm : CCondInstAlias<"sf", C_SF_S_CC, C_SF_D32_CC, C_SF_D64_CC>;
defm : CCondInstAlias<"ngle", C_NGLE_S_CC, C_NGLE_D32_CC, C_NGLE_D64_CC>;
defm : CCondInstAlias<"seq", C_SEQ_S_CC, C_SEQ_D32_CC, C_SEQ_D64_CC>;
defm : CCondInstAlias<"ngl", C_NGL_S_CC, C_NGL_D32_CC, C_NGL_D64_CC>;
defm : CCondInstAlias<"lt", C_LT_S_CC, C_LT_D32_CC, C_LT_D64_CC>;
defm : CCondInstAlias<"nge", C_NGE_S_CC, C_NGE_D32_CC, C_NGE_D64_CC>;
defm : CCondInstAlias<"le", C_LE_S_CC, C_LE_D32_CC, C_LE_D64_CC>;
defm : CCondInstAlias<"ngt", C_NGT_S_CC, C_NGT_D32_CC, C_NGT_D64_CC>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating Point Instructions // Floating Point Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.

lib/Target/Mips/MipsInstrFormats.td

Context not available.
let Inst{15-0} = offset; let Inst{15-0} = offset;
} }
class CEQS_FM<bits<5> fmt> : StdArch { class CEQS_FM_CC<bits<5> fmt> : StdArch {
bits<5> fs; bits<5> fs;
bits<5> ft; bits<5> ft;
bits<4> cond; bits<4> cond;
bits<3> cc;
bits<32> Inst; bits<32> Inst;
Context not available.
let Inst{25-21} = fmt; let Inst{25-21} = fmt;
let Inst{20-16} = ft; let Inst{20-16} = ft;
let Inst{15-11} = fs; let Inst{15-11} = fs;
let Inst{10-8} = 0; // cc let Inst{10-8} = cc;
let Inst{7-4} = 0x3; let Inst{7-4} = 0x3;
let Inst{3-0} = cond; let Inst{3-0} = cond;
} }
class CEQS_FM<bits<5> fmt> : StdArch {
bits<5> fs;
bits<5> ft;
bits<4> cond;
bits<32> Inst;
let Inst{31-26} = 0x11;
let Inst{25-21} = fmt;
let Inst{20-16} = ft;
let Inst{15-11} = fs;
let Inst{10-4} = 0x3;
let Inst{3-0} = cond;
}
class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
let cond = c; let cond = c;
} }
class C_COND_FM_CC<bits<5> fmt, bits<4> c> : CEQS_FM_CC<fmt> {
let cond = c;
}
class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch { class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
bits<5> fd; bits<5> fd;
bits<5> fs; bits<5> fs;
Context not available.

test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt

Context not available.
0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7 0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7
0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14
0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14
0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17
0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20
0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7
0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2
0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4
0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2
0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14
0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16
0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8
0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23
0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6
0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13
0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30
0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20
0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28
0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7
0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8
0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25
0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24
0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18
0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30
0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16
0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10
0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24
0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4
0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14 0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14
0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18 0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18
0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14 0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14
Context not available.

test/MC/Disassembler/Mips/mips32/valid-mips32.txt

Context not available.
0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
0x46 0x2e 0x71 0x32 # CHECK: c.eq.d $fcc1, $f14, $f14
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x34 0x54 0x30 # CHECK: c.f.d $fcc4, $f10, $f20
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x22 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f2
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x22 0x43 0x3c # CHECK: c.lt.d $fcc3, $f8, $f2
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xa5 0x3d # CHECK: c.nge.d $fcc5, $f20, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x26 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f6
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3e 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f30
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x94 0x34 # CHECK: c.olt.d $fcc4, $f18, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x28 0xf4 0x3a # CHECK: c.seq.d $fcc4, $f30, $f8
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x38 0x64 0x33 # CHECK: c.ueq.d $fcc4, $f12, $f24
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xc7 0x37 # CHECK: c.ule.d $fcc7, $f24, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x30 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f16
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xb6 0x31 # CHECK: c.un.d $fcc6, $f22, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
Context not available.

test/MC/Disassembler/Mips/mips32/valid-xfail-mips32.txt

  • This file was deleted.
# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble | FileCheck %s
# XFAIL: *
0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4

test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt

Context not available.
0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7 0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14 0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7 0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14
0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17
0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20
0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7
0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2
0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4
0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2
0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14
0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16
0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8
0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23
0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6
0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13
0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30
0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20
0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28
0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7
0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8
0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25
0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24
0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18
0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30
0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16
0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10
0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24
0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4
0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14 0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7 0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7 0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
Context not available.

test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt

Context not available.
0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
0x46 0x2e 0x71 0x32 # CHECK: c.eq.d $fcc1, $f14, $f14
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x34 0x54 0x30 # CHECK: c.f.d $fcc4, $f10, $f20
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x22 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f2
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x22 0x43 0x3c # CHECK: c.lt.d $fcc3, $f8, $f2
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xa5 0x3d # CHECK: c.nge.d $fcc5, $f20, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x26 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f6
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3e 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f30
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x94 0x34 # CHECK: c.olt.d $fcc4, $f18, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x28 0xf4 0x3a # CHECK: c.seq.d $fcc4, $f30, $f8
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x38 0x64 0x33 # CHECK: c.ueq.d $fcc4, $f12, $f24
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xc7 0x37 # CHECK: c.ule.d $fcc7, $f24, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x30 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f16
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xb6 0x31 # CHECK: c.un.d $fcc6, $f22, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7
0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
Context not available.

test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt

# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r2 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r2 | FileCheck %s
# XFAIL: * # XFAIL: *
0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8 0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10 0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10

test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt

Context not available.
0x39 0x00 0x30 0x46 # CHECK: c.ngle.d $f0, $f16 0x39 0x00 0x30 0x46 # CHECK: c.ngle.d $f0, $f16
0x38 0xf0 0x20 0x46 # CHECK: c.sf.d $f30, $f0 0x38 0xf0 0x20 0x46 # CHECK: c.sf.d $f30, $f0
0x38 0x70 0x16 0x46 # CHECK: c.sf.s $f14, $f22 0x38 0x70 0x16 0x46 # CHECK: c.sf.s $f14, $f22
0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14
0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17
0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20
0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7
0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2
0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4
0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2
0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14
0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16
0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8
0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23
0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6
0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13
0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30
0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20
0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28
0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7
0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8
0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25
0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24
0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18
0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30
0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16
0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10
0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24
0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4
0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3 0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3
0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13 0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13
0xce 0xc2 0x20 0x46 # CHECK: ceil.w.d $f11, $f24 0xce 0xc2 0x20 0x46 # CHECK: ceil.w.d $f11, $f24
Context not available.

test/MC/Disassembler/Mips/mips4/valid-mips4.txt

Context not available.
0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16
0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0
0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22
0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24 0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24
0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20 0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20
Context not available.

test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt

# RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips4 | FileCheck %s # RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips4 | FileCheck %s
# XFAIL: * # XFAIL: *
0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18

test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt

Context not available.
0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7 0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14 0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7 0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14
0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17
0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20
0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7
0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2
0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4
0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2
0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14
0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16
0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8
0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23
0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6
0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13
0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30
0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20
0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28
0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7
0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8
0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25
0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24
0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18
0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30
0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16
0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10
0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24
0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4
0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14 0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7 0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7
0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3 0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3
Context not available.

test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt

# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble | FileCheck %s
# XFAIL: * # XFAIL: *
0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8 0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
0x46 0xcd 0xde 0x40 # CHECK: add.ps $f25, $f27, $f13 0x46 0xcd 0xde 0x40 # CHECK: add.ps $f25, $f27, $f13
0x4d 0x9e 0x93 0x1e # CHECK: alnv.ps $f12, $f18, $f30, $8 0x4d 0x9e 0x93 0x1e # CHECK: alnv.ps $f12, $f18, $f30, $8

test/MC/Disassembler/Mips/mips64/valid-mips64.txt

Context not available.
0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14
0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14
Context not available.

test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt

Context not available.
0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7 0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7
0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14 0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14
0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7 0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7
0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14
0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17
0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20
0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7
0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2
0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4
0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2
0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14
0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16
0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8
0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23
0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6
0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13
0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30
0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20
0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28
0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7
0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8
0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25
0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24
0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18
0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30
0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16
0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10
0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24
0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4
0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3 0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3
0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13 0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13
0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14 0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14
Context not available.

test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt

Context not available.
0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7
0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14
0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3
0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14
Context not available.

test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt

# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r2 | FileCheck %s # RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r2 | FileCheck %s
# XFAIL: * # XFAIL: *
0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8 0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8
0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12
0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10 0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10

test/MC/Mips/mips32/valid-xfail.s

Context not available.
# XFAIL: * # XFAIL: *
.set noat .set noat
c.eq.d $fcc1,$f15,$f15
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.s $fcc3,$f11,$f8
c.ngl.s $fcc2,$f31,$f23
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
rorv $13,$a3,$s5 rorv $13,$a3,$s5
Context not available.

test/MC/Mips/mips32/valid.s

Context not available.
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
c.eq.d $fcc1,$f15,$f15
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.s $fcc3,$f11,$f8
c.ngl.s $fcc2,$f31,$f23
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
Context not available.

test/MC/Mips/mips32r2/valid-xfail.s

Context not available.
bmnz.v $w15,$w2,$w28 bmnz.v $w15,$w2,$w28
bmz.v $w13,$w11,$w21 bmz.v $w13,$w11,$w21
bsel.v $w28,$w7,$w0 bsel.v $w28,$w7,$w0
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4 c.ult.ps $fcc7,$f14,$f0
c.ule.ps $fcc6,$f17,$f3
c.ueq.ps $fcc1,$f5,$f29
c.sf.ps $fcc6,$f4,$f6
c.seq.ps $fcc6,$f31,$f14
c.olt.ps $fcc3,$f7,$f16
c.ole.ps $fcc7,$f21,$f8
c.ngt.ps $fcc5,$f30,$f6
c.ngle.ps $fcc7,$f12,$f20
c.ngl.ps $f21,$f30
c.nge.ps $f1,$f26
c.lt.ps $f19,$f5
c.le.ps $fcc1,$f7,$f20
c.f.ps $fcc6,$f11,$f11
c.eq.ps $fcc5,$f0,$f9
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
cfcmsa $s6,$19 cfcmsa $s6,$19
Context not available.

test/MC/Mips/mips32r2/valid.s

Context not available.
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
c.eq.d $fcc1,$f15,$f15
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.s $fcc3,$f11,$f8
c.ngl.s $fcc2,$f31,$f23
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
Context not available.

test/MC/Mips/mips4/valid-xfail.s

Context not available.
# XFAIL: * # XFAIL: *
.set noat .set noat
c.eq.d $fcc1,$f15,$f15
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.s $fcc3,$f11,$f8
c.ngl.s $fcc2,$f31,$f23
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
madd.d $f18,$f19,$f26,$f20 madd.d $f18,$f19,$f26,$f20
madd.s $f1,$f31,$f19,$f25 madd.s $f1,$f31,$f19,$f25
msub.d $f10,$f1,$f31,$f18 msub.d $f10,$f1,$f31,$f18
Context not available.

test/MC/Mips/mips4/valid.s

Context not available.
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
c.eq.d $fcc1,$f15,$f15
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.s $fcc3,$f11,$f8
c.ngl.s $fcc2,$f31,$f23
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
Context not available.

test/MC/Mips/mips5/valid-xfail.s

Context not available.
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25 cvt.s.pu $f14,$f25
Context not available.

test/MC/Mips/mips5/valid.s

Context not available.
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
c.eq.d $fcc1,$f15,$f15
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.s $fcc3,$f11,$f8
c.ngl.s $fcc2,$f31,$f23
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
Context not available.

test/MC/Mips/mips64/valid-xfail.s

Context not available.
alnv.ob $v31,$v23,$v30,$at alnv.ob $v31,$v23,$v30,$at
alnv.ob $v8,$v17,$v30,$a1 alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25 cvt.s.pu $f14,$f25
Context not available.

test/MC/Mips/mips64/valid.s

Context not available.
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
c.eq.d $fcc1,$f15,$f15
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.s $fcc3,$f11,$f8
c.ngl.s $fcc2,$f31,$f23
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
Context not available.

test/MC/Mips/mips64r2/valid-xfail.s

Context not available.
bmnz.v $w15,$w2,$w28 bmnz.v $w15,$w2,$w28
bmz.v $w13,$w11,$w21 bmz.v $w13,$w11,$w21
bsel.v $w28,$w7,$w0 bsel.v $w28,$w7,$w0
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cmp.eq.ph $s7,$14 cmp.eq.ph $s7,$14
cmp.le.ph $8,$14 cmp.le.ph $8,$14
Context not available.

test/MC/Mips/mips64r2/valid.s

Context not available.
c.ngle.d $f0,$f16 c.ngle.d $f0,$f16
c.sf.d $f30,$f0 c.sf.d $f30,$f0
c.sf.s $f14,$f22 c.sf.s $f14,$f22
c.eq.d $fcc1,$f15,$f15
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.s $fcc3,$f11,$f8
c.ngl.s $fcc2,$f31,$f23
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
Context not available.
test/MC/Disassembler/Mips/mips32/valid-mips32.txt