[Power9] Enable extload of constant values to f128

[lei]

Summary

Enable` extload` of constant values to f128

[nemanjai]

LGTM.

lib/Target/PowerPC/PPCISelLowering.cpp

800

Nit: please add a comment // No extending loads to f128 on PPC.

[lei]

This patch has a dependency on: https://reviews.llvm.org/D47552

lib/Target/PowerPC/PPCISelLowering.cpp

800

okay.

[lei]

merged into D47552

lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasP9Vector()) {
 
       if (EnableQuadPrecision) {
         addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
         setOperationAction(ISD::FADD, MVT::f128, Legal);
         setOperationAction(ISD::FSUB, MVT::f128, Legal);
         setOperationAction(ISD::FDIV, MVT::f128, Legal);
         setOperationAction(ISD::FMUL, MVT::f128, Legal);
         setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
-        setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
-        setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
+        for (MVT VT : MVT::fp_valuetypes())
+          setLoadExtAction(ISD::EXTLOAD, MVT::f128, VT, Expand);
         setOperationAction(ISD::FMA, MVT::f128, Legal);
         setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
         setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
         setTruncStoreAction(MVT::f128, MVT::f64, Expand);
         setTruncStoreAction(MVT::f128, MVT::f32, Expand);
       }
 
     }

test/CodeGen/PowerPC/f128-passByValue.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -enable-ppc-quad-precision -ppc-asm-full-reg-names \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s
 
+; Function Attrs: norecurse nounwind readnone
+define fp128 @loadConstant() {
+; CHECK-LABEL: loadConstant:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-NEXT:    lxvx vs34, 0, r3
+; CHECK-NEXT:    blr
+entry:
+  ret fp128 0xL00000000000000004001400000000000
+}
+
+; Function Attrs: norecurse nounwind readnone
+define fp128 @loadConstant2(fp128 %a, fp128 %b) {
+; CHECK-LABEL: loadConstant2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xsaddqp v2, v2, v3
+; CHECK-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-NEXT:    lxvx vs51, 0, r3
+; CHECK-NEXT:    xsaddqp v2, v2, v19
+; CHECK-NEXT:    blr
+entry:
+  %add = fadd fp128 %a, %b
+  %add1 = fadd fp128 %add, 0xL00000000000000004001400000000000
+  ret fp128 %add1
+}
+
 ; Test passing float128 by value.
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @fp128Param(fp128 %a) {
 ; CHECK-LABEL: fp128Param:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvqpswz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, vs34
 ; CHECK-NEXT:    extsw r3, r3