[llvm-mca] Add the RetireStage.

[mattd]

Summary

This class maintains the same logic as the original RetireControlUnit.

This is just an intermediate patch to make the RCU a Stage. Future patches will remove the dependency on the DispatchStage, and then more properly populate the pre/execute/post Stage interface.

[andreadb]

A couple of minor nits. Otherwise it LGTM too.

tools/llvm-mca/Backend.cpp

41 ↗

(On Diff #148152)

Backend.cpp should not be modified by this patch. Please get rid of this line diff.

tools/llvm-mca/DispatchStage.h

11–12 ↗

(On Diff #148152)

Can you improve the description? The old description is no longer valid.

tools/llvm-mca/RetireStage.h

88 ↗

(On Diff #148152)

This comment can be removed as it doesn't add much.

[andreadb]

On a second thought,
wouldn't it be better if we still keep the RetireControlUnit abstraction?
We can have that the RetireStage acts as a proxy for the RetireControlUnit.

Basically, the logic in RetireStage::cycleEvent() and onInstructionExecuted() should be implemented by the "stage".
While, the actual RetireControlUnit functionality should live in its own class. I think it logically helps to distinguish between the actual pipeline process from the implementation of the RCU. It also allows the Stage to not be bound to a specific implementation of the RCU.

[mattd]

I like Andrea's suggestion, and that we still maintain the RCU as a separate component.

This patch maintains that separation, but places ownership in the Backend. Additionally, the RegisterFile (renamed to RF instead of RAT) is also another simulated hardware component that is owned by the Backend. Any other MCA component that requires the use of such hardware abstraction will be passed pointers to those items during construction. The Owner pointer in the RetireStage (sorry) will hopefully disappear once we move the eventing (notification) logic from solely being owned by the Backend, into the the Stages.

This patch moves the notifyInstructionRetired and cycleEvent from the RCU into the RetireStage.

[andreadb]

In D47244#1111881, @mattd wrote:

I like Andrea's suggestion, and that we still maintain the RCU as a separate component.

This patch maintains that separation, but places ownership in the Backend. Additionally, the RegisterFile (renamed to RF instead of RAT) is also another simulated hardware component that is owned by the Backend. Any other MCA component that requires the use of such hardware abstraction will be passed pointers to those items during construction.

Nice patch. Thanks!

The Owner pointer in the RetireStage (sorry) will hopefully disappear once we move the eventing (notification) logic from solely being owned by the Backend, into the the Stages.

No problem. One step at the time :-).

This patch moves the notifyInstructionRetired and cycleEvent from the RCU into the RetireStage.

LGTM modulo a few nits (see comments below).

Thanks
-Andrea

tools/llvm-mca/DispatchStage.cpp

33 ↗

(On Diff #148532)

s/checkRF/checkPRF

tools/llvm-mca/DispatchStage.h

62–63 ↗

(On Diff #148532)

These should be references.
Also, could you please rename RF --> PRF (as in physical register file)?

92–93 ↗

(On Diff #148532)

Pass the RCU and PRF by reference to the constructor of DispatchStage.

tools/llvm-mca/RetireStage.h

31–32 ↗

(On Diff #148532)

Make these references.
Please rename RF into PRF.

tools/llvm-mca/Scheduler.h

405 ↗

(On Diff #148532)

Make this a reference.

[mattd]

• Renamed RegisterFile references from RF to PRF.
• I think it's simplest to make RCU and PRF complete objects instead of pointers or unique_ptrs.
• For now RCU and PRF are owned by the pipeline abstraction: Backend.
• RCU and PRF are now passed as references to Backend components that need them.

[andreadb]

LGTM. Thanks!

llvm/trunk/tools/llvm-mca/Backend.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_BACKEND_H
 #define LLVM_TOOLS_LLVM_MCA_BACKEND_H
 
 #include "DispatchStage.h"
 #include "FetchStage.h"
 #include "InstrBuilder.h"
+#include "RegisterFile.h"
+#include "RetireControlUnit.h"
+#include "RetireStage.h"
 #include "Scheduler.h"
 
 namespace mca {
 
 class HWEventListener;
 class HWInstructionEvent;
 class HWStallEvent;
 

 /// The Backend entry point is method 'run()' which executes cycles in a loop
 /// until there are new instructions to dispatch, and not every instruction
 /// has been retired.
 ///
 /// Internally, the Backend collects statistical information in the form of
 /// histograms. For example, it tracks how the dispatch group size changes
 /// over time.
 class Backend {
-  /// This is the initial stage of the pipeline.
+  // The following are the simulated hardware components of the backend.
+  RetireControlUnit RCU;
+  RegisterFile PRF;
+
   /// TODO: Eventually this will become a list of unique Stage* that this
   /// backend pipeline executes.
   std::unique_ptr<FetchStage> Fetch;
   std::unique_ptr<Scheduler> HWS;
   std::unique_ptr<DispatchStage> Dispatch;
+  std::unique_ptr<RetireStage> Retire;
+
   std::set<HWEventListener *> Listeners;
   unsigned Cycles;
 
   void runCycle(unsigned Cycle);
 
 public:
   Backend(const llvm::MCSubtargetInfo &Subtarget,
           const llvm::MCRegisterInfo &MRI,
           std::unique_ptr<FetchStage> InitialStage, unsigned DispatchWidth = 0,
           unsigned RegisterFileSize = 0, unsigned LoadQueueSize = 0,
           unsigned StoreQueueSize = 0, bool AssumeNoAlias = false)
-      : Fetch(std::move(InitialStage)),
-        HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(),
+      : RCU(Subtarget.getSchedModel()),
+        PRF(Subtarget.getSchedModel(), MRI, RegisterFileSize),
+        Fetch(std::move(InitialStage)),
+        HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(), RCU,
                                          LoadQueueSize, StoreQueueSize,
                                          AssumeNoAlias)),
         Dispatch(llvm::make_unique<DispatchStage>(
-            this, Subtarget, MRI, RegisterFileSize, DispatchWidth, HWS.get())),
-        Cycles(0) {
-    HWS->setDispatchStage(Dispatch.get());
-  }
+            this, Subtarget, MRI, RegisterFileSize, DispatchWidth, RCU, PRF,
+            HWS.get())),
+        Retire(llvm::make_unique<RetireStage>(this, RCU, PRF)), Cycles(0) {}
 
   void run();
   void addEventListener(HWEventListener *Listener);
   void notifyCycleBegin(unsigned Cycle);
   void notifyInstructionEvent(const HWInstructionEvent &Event);
   void notifyStallEvent(const HWStallEvent &Event);
   void notifyResourceAvailable(const ResourceRef &RR);
   void notifyReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
   void notifyCycleEnd(unsigned Cycle);
 };
 } // namespace mca
 
 #endif

llvm/trunk/tools/llvm-mca/Backend.cpp

 void Backend::run() {
   while (Fetch->isReady() || !Dispatch->isReady())
     runCycle(Cycles++);
 }
 
 void Backend::runCycle(unsigned Cycle) {
   notifyCycleBegin(Cycle);
 
+  // Update the stages before we do any processing for this cycle.
   InstRef IR;
+  Retire->preExecute(IR);
   Dispatch->preExecute(IR);
+
+  // This will execute scheduled instructions.
   HWS->cycleEvent(); // TODO: This will eventually be stage-ified.
 
+  // Fetch instructions and dispatch them to the hardware.
   while (Fetch->execute(IR)) {
     if (!Dispatch->execute(IR))
       break;
     Fetch->postExecute(IR);
   }
 
   notifyCycleEnd(Cycle);
 }

llvm/trunk/tools/llvm-mca/CMakeLists.txt

add_llvm_tool(llvm-mca
   InstructionTables.cpp
   LSUnit.cpp
   llvm-mca.cpp
   RegisterFile.cpp
   RegisterFileStatistics.cpp
   ResourcePressureView.cpp
   RetireControlUnit.cpp
   RetireControlUnitStatistics.cpp
+  RetireStage.cpp
   Scheduler.cpp
   SchedulerStatistics.cpp
   Stage.cpp
   Support.cpp
   SummaryView.cpp
   TimelineView.cpp
   View.cpp
   )

llvm/trunk/tools/llvm-mca/DispatchStage.h

 // The DispatchStage will still have to wait for a number of cycles (depending
 // on the DispatchWidth and the number of micro opcodes) before it can serve
 // other instructions.
 class DispatchStage : public Stage {
   unsigned DispatchWidth;
   unsigned AvailableEntries;
   unsigned CarryOver;
   Scheduler *SC;
-  std::unique_ptr<RegisterFile> RAT;
-  std::unique_ptr<RetireControlUnit> RCU;
   Backend *Owner;
   const llvm::MCSubtargetInfo &STI;
+  RetireControlUnit &RCU;
+  RegisterFile &PRF;
 
-  bool checkRAT(const InstRef &IR);
   bool checkRCU(const InstRef &IR);
+  bool checkPRF(const InstRef &IR);
   bool checkScheduler(const InstRef &IR);
   void dispatch(InstRef IR);
-  bool isRCUEmpty() const { return RCU->isEmpty(); }
+  bool isRCUEmpty() const { return RCU.isEmpty(); }
   void updateRAWDependencies(ReadState &RS, const llvm::MCSubtargetInfo &STI);
 
   void notifyInstructionDispatched(const InstRef &IR,
                                    llvm::ArrayRef<unsigned> UsedPhysRegs);
 
   bool isAvailable(unsigned NumEntries) const {
     return NumEntries <= AvailableEntries || AvailableEntries == DispatchWidth;
   }
 
   bool canDispatch(const InstRef &IR) {
     assert(isAvailable(IR.getInstruction()->getDesc().NumMicroOps));
-    return checkRCU(IR) && checkRAT(IR) && checkScheduler(IR);
+    return checkRCU(IR) && checkPRF(IR) && checkScheduler(IR);
   }
 
   void collectWrites(llvm::SmallVectorImpl<WriteState *> &Vec,
                      unsigned RegID) const {
-    return RAT->collectWrites(Vec, RegID);
+    return PRF.collectWrites(Vec, RegID);
   }
 
 public:
   DispatchStage(Backend *B, const llvm::MCSubtargetInfo &Subtarget,
                 const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
-                unsigned MaxDispatchWidth, Scheduler *Sched)
+                unsigned MaxDispatchWidth, RetireControlUnit &R,
+                RegisterFile &F, Scheduler *Sched)
       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
-        CarryOver(0U), SC(Sched),
-        RAT(llvm::make_unique<RegisterFile>(Subtarget.getSchedModel(), MRI,
-                                            RegisterFileSize)),
-        RCU(llvm::make_unique<RetireControlUnit>(Subtarget.getSchedModel(),
-                                                 this)),
-        Owner(B), STI(Subtarget) {}
+        CarryOver(0U), SC(Sched), Owner(B), STI(Subtarget), RCU(R), PRF(F) {}
 
   virtual bool isReady() const override final { return isRCUEmpty(); }
   virtual void preExecute(const InstRef &IR) override final;
   virtual bool execute(InstRef &IR) override final;
-  void notifyInstructionRetired(const InstRef &IR);
   void notifyDispatchStall(const InstRef &IR, unsigned EventType);
 
-  void onInstructionExecuted(unsigned TokenID) {
-    RCU->onInstructionExecuted(TokenID);
-  }
-
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 } // namespace mca
 
 #endif

llvm/trunk/tools/llvm-mca/DispatchStage.cpp

 namespace mca {
 
 void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
                                                 ArrayRef<unsigned> UsedRegs) {
   LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: " << IR << '\n');
   Owner->notifyInstructionEvent(HWInstructionDispatchedEvent(IR, UsedRegs));
 }
 
-void DispatchStage::notifyInstructionRetired(const InstRef &IR) {
-  LLVM_DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
-  SmallVector<unsigned, 4> FreedRegs(RAT->getNumRegisterFiles());
-  const InstrDesc &Desc = IR.getInstruction()->getDesc();
-
-  for (const std::unique_ptr<WriteState> &WS : IR.getInstruction()->getDefs())
-    RAT->removeRegisterWrite(*WS.get(), FreedRegs, !Desc.isZeroLatency());
-  Owner->notifyInstructionEvent(HWInstructionRetiredEvent(IR, FreedRegs));
-}
-
-bool DispatchStage::checkRAT(const InstRef &IR) {
+bool DispatchStage::checkPRF(const InstRef &IR) {
   SmallVector<unsigned, 4> RegDefs;
   for (const std::unique_ptr<WriteState> &RegDef :
        IR.getInstruction()->getDefs())
     RegDefs.emplace_back(RegDef->getRegisterID());
 
-  unsigned RegisterMask = RAT->isAvailable(RegDefs);
+  const unsigned RegisterMask = PRF.isAvailable(RegDefs);
   // A mask with all zeroes means: register files are available.
   if (RegisterMask) {
     Owner->notifyStallEvent(HWStallEvent(HWStallEvent::RegisterFileStall, IR));
     return false;
   }
 
   return true;
 }
 
 bool DispatchStage::checkRCU(const InstRef &IR) {
   const unsigned NumMicroOps = IR.getInstruction()->getDesc().NumMicroOps;
-  if (RCU->isAvailable(NumMicroOps))
+  if (RCU.isAvailable(NumMicroOps))
     return true;
   Owner->notifyStallEvent(
       HWStallEvent(HWStallEvent::RetireControlUnitStall, IR));
   return false;
 }
 
 bool DispatchStage::checkScheduler(const InstRef &IR) {
   return SC->canBeDispatched(IR);
void DispatchStage::dispatch(InstRef IR) {
   // An example of dependency-breaking instruction on X86 is a zero-idiom XOR.
   if (!Desc.isZeroLatency())
     for (std::unique_ptr<ReadState> &RS : IS.getUses())
       updateRAWDependencies(*RS, STI);
 
   // By default, a dependency-breaking zero-latency instruction is expected to
   // be optimized at register renaming stage. That means, no physical register
   // is allocated to the instruction.
-  SmallVector<unsigned, 4> RegisterFiles(RAT->getNumRegisterFiles());
+  SmallVector<unsigned, 4> RegisterFiles(PRF.getNumRegisterFiles());
   for (std::unique_ptr<WriteState> &WS : IS.getDefs())
-    RAT->addRegisterWrite(*WS, RegisterFiles, !Desc.isZeroLatency());
+    PRF.addRegisterWrite(*WS, RegisterFiles, !Desc.isZeroLatency());
 
   // Reserve slots in the RCU, and notify the instruction that it has been
   // dispatched to the schedulers for execution.
-  IS.dispatch(RCU->reserveSlot(IR, NumMicroOps));
+  IS.dispatch(RCU.reserveSlot(IR, NumMicroOps));
 
   // Notify listeners of the "instruction dispatched" event.
   notifyInstructionDispatched(IR, RegisterFiles);
 
   // Now move the instruction into the scheduler's queue.
   // The scheduler is responsible for checking if this is a zero-latency
   // instruction that doesn't consume pipeline/scheduler resources.
   SC->scheduleInstruction(IR);
 }
 
 void DispatchStage::preExecute(const InstRef &IR) {
-  RCU->cycleEvent();
   AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
   CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
 }
 
 bool DispatchStage::execute(InstRef &IR) {
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   if (!isAvailable(Desc.NumMicroOps) || !canDispatch(IR))
     return false;
   dispatch(IR);
   return true;
 }
 
 #ifndef NDEBUG
 void DispatchStage::dump() const {
-  RAT->dump();
-  RCU->dump();
+  PRF.dump();
+  RCU.dump();
 }
 #endif
 } // namespace mca

llvm/trunk/tools/llvm-mca/RetireControlUnit.h

 //===---------------------- RetireControlUnit.h -----------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements the logic for retiring instructions.
+/// This file simulates the hardware responsible for retiring instructions.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H
 #define LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H
 
 #include "Instruction.h"
 #include "llvm/MC/MCSchedule.h"
struct RetireControlUnit {
   };
 
 private:
   unsigned NextAvailableSlotIdx;
   unsigned CurrentInstructionSlotIdx;
   unsigned AvailableSlots;
   unsigned MaxRetirePerCycle; // 0 means no limit.
   std::vector<RUToken> Queue;
-  DispatchStage *Owner;
 
 public:
-  RetireControlUnit(const llvm::MCSchedModel &SM, DispatchStage *DU);
+  RetireControlUnit(const llvm::MCSchedModel &SM);
 
   bool isFull() const { return !AvailableSlots; }
   bool isEmpty() const { return AvailableSlots == Queue.size(); }
   bool isAvailable(unsigned Quantity = 1) const {
-    // Some instructions may declare a number of uOps which exceedes the size
+    // Some instructions may declare a number of uOps which exceeds the size
     // of the reorder buffer. To avoid problems, cap the amount of slots to
     // the size of the reorder buffer.
     Quantity = std::min(Quantity, static_cast<unsigned>(Queue.size()));
     return AvailableSlots >= Quantity;
   }
 
+  unsigned getMaxRetirePerCycle() const { return MaxRetirePerCycle; }
+
   // Reserves a number of slots, and returns a new token.
   unsigned reserveSlot(const InstRef &IS, unsigned NumMicroOps);
 
-  /// Retires instructions in program order.
-  void cycleEvent();
+  // Return the current token from the RCU's circular token queue.
+  const RUToken &peekCurrentToken() const;
+
+  // Advance the pointer to the next token in the circular token queue.
+  void consumeCurrentToken();
 
+  // Update the RCU token to represent the executed state.
   void onInstructionExecuted(unsigned TokenID);
 
 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 } // namespace mca
 
 #endif // LLVM_TOOLS_LLVM_MCA_RETIRE_CONTROL_UNIT_H

llvm/trunk/tools/llvm-mca/RetireControlUnit.cpp

 //===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file implements methods declared by the RetireControlUnit interface.
+/// This file simulates the hardware responsible for retiring instructions.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "RetireControlUnit.h"
 #include "DispatchStage.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace mca {
 
-RetireControlUnit::RetireControlUnit(const llvm::MCSchedModel &SM,
-                                     DispatchStage *DS)
+RetireControlUnit::RetireControlUnit(const llvm::MCSchedModel &SM)
     : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
-      AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0), Owner(DS) {
+      AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0) {
   // Check if the scheduling model provides extra information about the machine
   // processor. If so, then use that information to set the reorder buffer size
   // and the maximum number of instructions retired per cycle.
   if (SM.hasExtraProcessorInfo()) {
     const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
     if (EPI.ReorderBufferSize)
       AvailableSlots = EPI.ReorderBufferSize;
     MaxRetirePerCycle = EPI.MaxRetirePerCycle;
unsigned RetireControlUnit::reserveSlot(const InstRef &IR,
   unsigned TokenID = NextAvailableSlotIdx;
   Queue[NextAvailableSlotIdx] = {IR, NormalizedQuantity, false};
   NextAvailableSlotIdx += NormalizedQuantity;
   NextAvailableSlotIdx %= Queue.size();
   AvailableSlots -= NormalizedQuantity;
   return TokenID;
 }
 
-void RetireControlUnit::cycleEvent() {
-  if (isEmpty())
-    return;
-
-  unsigned NumRetired = 0;
-  while (!isEmpty()) {
-    if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
-      break;
-    RUToken &Current = Queue[CurrentInstructionSlotIdx];
-    assert(Current.NumSlots && "Reserved zero slots?");
-    assert(Current.IR.isValid() && "Invalid RUToken in the RCU queue.");
-    if (!Current.Executed)
-      break;
-    Owner->notifyInstructionRetired(Current.IR);
-    CurrentInstructionSlotIdx += Current.NumSlots;
-    CurrentInstructionSlotIdx %= Queue.size();
-    AvailableSlots += Current.NumSlots;
-    NumRetired++;
-  }
+const RetireControlUnit::RUToken &RetireControlUnit::peekCurrentToken() const {
+  return Queue[CurrentInstructionSlotIdx];
+}
+
+void RetireControlUnit::consumeCurrentToken() {
+  const RetireControlUnit::RUToken &Current = peekCurrentToken();
+
+  // Update the slot index to be the next item in the circular queue.
 }
 
 void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
   assert(Queue.size() > TokenID);
   assert(Queue[TokenID].Executed == false && Queue[TokenID].IR.isValid());
   Queue[TokenID].Executed = true;
 }
 
 #ifndef NDEBUG
 void RetireControlUnit::dump() const {
   dbgs() << "Retire Unit: { Total Slots=" << Queue.size()
          << ", Available Slots=" << AvailableSlots << " }\n";
 }
 #endif
 
 } // namespace mca

llvm/trunk/tools/llvm-mca/RetireStage.h

+//===---------------------- RetireStage.h -----------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file defines the retire stage of an instruction pipeline.
+/// The RetireStage represents the process logic that interacts with the
+/// simulated RetireControlUnit hardware.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
+#define LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H
+
+#include "RegisterFile.h"
+#include "RetireControlUnit.h"
+#include "Stage.h"
+
+namespace mca {
+
+class Backend;
+
+class RetireStage : public Stage {
+  // Owner will go away when we move listeners/eventing to the stages.
+  Backend *Owner;
+  RetireControlUnit &RCU;
+  RegisterFile &PRF;
+
+public:
+  RetireStage(Backend *B, RetireControlUnit &R, RegisterFile &F)
+      : Stage(), Owner(B), RCU(R), PRF(F) {}
+  RetireStage(const RetireStage &Other) = delete;
+  RetireStage &operator=(const RetireStage &Other) = delete;
+
+  virtual void preExecute(const InstRef &IR) override final;
+  virtual bool execute(InstRef &IR) override final { return true; }
+  void notifyInstructionRetired(const InstRef &IR);
+  void onInstructionExecuted(unsigned TokenID);
+};
+
+} // namespace mca
+
+#endif // LLVM_TOOLS_LLVM_MCA_RETIRE_STAGE_H

llvm/trunk/tools/llvm-mca/RetireStage.cpp

+//===---------------------- RetireStage.cpp ---------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file defines the retire stage of an instruction pipeline.
+/// The RetireStage represents the process logic that interacts with the
+/// simulated RetireControlUnit hardware.
+///
+//===----------------------------------------------------------------------===//
+
+#include "RetireStage.h"
+#include "Backend.h"
+#include "HWEventListener.h"
+#include "llvm/Support/Debug.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "llvm-mca"
+
+namespace mca {
+
+void RetireStage::preExecute(const InstRef &IR) {
+  if (RCU.isEmpty())
+    return;
+
+  const unsigned MaxRetirePerCycle = RCU.getMaxRetirePerCycle();
+  unsigned NumRetired = 0;
+  while (!RCU.isEmpty()) {
+    if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
+      break;
+    const RetireControlUnit::RUToken &Current = RCU.peekCurrentToken();
+    if (!Current.Executed)
+      break;
+    RCU.consumeCurrentToken();
+    notifyInstructionRetired(Current.IR);
+    NumRetired++;
+  }
+}
+
+void RetireStage::notifyInstructionRetired(const InstRef &IR) {
+  LLVM_DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
+  SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles());
+  const InstrDesc &Desc = IR.getInstruction()->getDesc();
+
+  for (const std::unique_ptr<WriteState> &WS : IR.getInstruction()->getDefs())
+    PRF.removeRegisterWrite(*WS.get(), FreedRegs, !Desc.isZeroLatency());
+  Owner->notifyInstructionEvent(HWInstructionRetiredEvent(IR, FreedRegs));
+}
+
+} // namespace mca

llvm/trunk/tools/llvm-mca/Scheduler.h

 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
 #define LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
 
 #include "Instruction.h"
 #include "LSUnit.h"
+#include "RetireControlUnit.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <map>
 
 namespace mca {
 
 class Backend;
-class DispatchStage;
 
 /// Used to notify the internal state of a processor resource.
 ///
 /// A processor resource is available if it is not reserved, and there are
 /// available slots in the buffer.  A processor resource is unavailable if it
 /// is either reserved, or the associated buffer is full. A processor resource
 /// with a buffer size of -1 is always available if it is not reserved.
 ///

 /// that the first instructions in the set are also the oldest.
 ///
 /// An Instruction is moved from the ReadyQueue the `IssuedQueue` when it is
 /// issued to a (one or more) pipeline(s). This event also causes an instruction
 /// state transition (i.e. from state IS_READY, to state IS_EXECUTING).
 /// An Instruction leaves the IssuedQueue when it reaches the write-back stage.
 class Scheduler {
   const llvm::MCSchedModel &SM;
+  RetireControlUnit &RCU;
 
   // Hardware resources that are managed by this scheduler.
   std::unique_ptr<ResourceManager> Resources;
   std::unique_ptr<LSUnit> LSU;
 
   // The Backend gets notified when instructions are ready/issued/executed.
   Backend *const Owner;
 
-  // The dispatch unit gets notified when instructions are executed.
-  DispatchStage *DS;
-
   using QueueEntryTy = std::pair<unsigned, Instruction *>;
   std::map<unsigned, Instruction *> WaitQueue;
   std::map<unsigned, Instruction *> ReadyQueue;
   std::map<unsigned, Instruction *> IssuedQueue;
 
   void
   notifyInstructionIssued(const InstRef &IR,
                           llvm::ArrayRef<std::pair<ResourceRef, double>> Used);
class Scheduler {
   void issueInstructionImpl(
       InstRef &IR,
       llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Pipes);
 
   void updatePendingQueue(llvm::SmallVectorImpl<InstRef> &Ready);
   void updateIssuedQueue(llvm::SmallVectorImpl<InstRef> &Executed);
 
 public:
-  Scheduler(Backend *B, const llvm::MCSchedModel &Model, unsigned LoadQueueSize,
-            unsigned StoreQueueSize, bool AssumeNoAlias)
-      : SM(Model), Resources(llvm::make_unique<ResourceManager>(SM)),
+  Scheduler(Backend *B, const llvm::MCSchedModel &Model, RetireControlUnit &R,
+            unsigned LoadQueueSize, unsigned StoreQueueSize, bool AssumeNoAlias)
+      : SM(Model), RCU(R), Resources(llvm::make_unique<ResourceManager>(SM)),
         LSU(llvm::make_unique<LSUnit>(LoadQueueSize, StoreQueueSize,
                                       AssumeNoAlias)),
         Owner(B) {}
 
-  void setDispatchStage(DispatchStage *DispStage) { DS = DispStage; }
-
   /// Check if the instruction in 'IR' can be dispatched.
   ///
   /// The DispatchStage is responsible for querying the Scheduler before
   /// dispatching new instructions. Queries are performed through method
   /// `Scheduler::canBeDispatched`. If scheduling resources are available,
   /// and the instruction can be dispatched, then this method returns true.
   /// Otherwise, a generic HWStallEvent is notified to the listeners.
   bool canBeDispatched(const InstRef &IR) const;

llvm/trunk/tools/llvm-mca/Scheduler.cpp

void Scheduler::notifyInstructionIssued(
   Owner->notifyInstructionEvent(HWInstructionIssuedEvent(IR, Used));
 }
 
 void Scheduler::notifyInstructionExecuted(const InstRef &IR) {
   LSU->onInstructionExecuted(IR);
   LLVM_DEBUG(dbgs() << "[E] Instruction Executed: " << IR << '\n');
   Owner->notifyInstructionEvent(
       HWInstructionEvent(HWInstructionEvent::Executed, IR));
-  DS->onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
+  RCU.onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
 }
 
 void Scheduler::notifyInstructionReady(const InstRef &IR) {
   LLVM_DEBUG(dbgs() << "[E] Instruction Ready: " << IR << '\n');
   Owner->notifyInstructionEvent(
       HWInstructionEvent(HWInstructionEvent::Ready, IR));
 }