AMDGPU: Stop special casing constant indexes of extract_vector_elt

[arsenm]

Summary

The same result folds out of the dynamic expansion logic if the
index is constant.

[rampitec]

LGTM

[arsenm]

r331906

lib/Target/AMDGPU/SIISelLowering.cpp

SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
 
   // Make sure we do any optimizations that will make it easier to fold
   // source modifiers before obscuring it with bit operations.
 
   // XXX - Why doesn't this get called when vector_shuffle is expanded?
   if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
     return Combined;
 
-  if (const ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
-    SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
-
-    if (CIdx->getZExtValue() == 1) {
-      Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result,
-                           DAG.getConstant(16, SL, MVT::i32));
-    } else {
-      assert(CIdx->getZExtValue() == 0);
-    }
-
-    if (ResultVT.bitsLT(MVT::i32))
-      Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Result);
-    return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
-  }
-
   SDValue Four = DAG.getConstant(4, SL, MVT::i32);
 
   // Convert vector index to bit-index (* 16)
   SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, Four);
 
   SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
   SDValue Elt = DAG.getNode(ISD::SRL, SL, MVT::i32, BC, ScaledIdx);