This is an archive of the discontinued LLVM Phabricator instance.

Differential D46171

AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL
ClosedPublic

Authored by tstellar on Apr 26 2018, 9:09 PM.

Details

Reviewers
arsenm
nhaehnle
Commits
rG46bbbc33c02f: AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL
rL334665: AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL

Diff Detail

Event Timeline

tstellar created this revision.Apr 26 2018, 9:09 PM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptApr 26 2018, 9:09 PM
Harbormaster completed remote builds in B17484: Diff 144273.Apr 26 2018, 9:09 PM
arsenm added inline comments.May 3 2018, 3:06 AM
test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir
4

I think you can drop the IR

tstellar updated this revision to Diff 146993.May 15 2018, 9:49 PM

Rebase patch.

Harbormaster completed remote builds in B18158: Diff 146993.May 15 2018, 9:49 PM
tstellar added inline comments.May 15 2018, 9:50 PM
test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir
4

The Machine IR needs the %global0 reference.

arsenm accepted this revision.Jun 7 2018, 12:32 AM

LGTM

This revision is now accepted and ready to land.Jun 7 2018, 12:32 AM
Closed by commit rL334665: AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL (authored by tstellar). · Explain WhyJun 13 2018, 3:35 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
4 lines
2 lines
10 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
37 lines
37 lines

Diff 144273

lib/Target/AMDGPU/AMDGPUGISel.td

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
// even supported yet. // even supported yet.
defm : GISelVOP2DefaultPat < defm : GISelVOP2DefaultPat <
int_amdgcn_cvt_pkrtz, V_CVT_PKRTZ_F16_F32_e32, v2f16, f32>; int_amdgcn_cvt_pkrtz, V_CVT_PKRTZ_F16_F32_e32, v2f16, f32>;
def gi_vop3mods0 : def gi_vop3mods0 :
GIComplexOperandMatcher<s32, "selectVOP3Mods0">, GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
GIComplexPatternEquiv<VOP3Mods0>; GIComplexPatternEquiv<VOP3Mods0>;
def gi_vop3mods :
GIComplexOperandMatcher<s32, "selectVOP3Mods">,
GIComplexPatternEquiv<VOP3Mods>;

lib/Target/AMDGPU/AMDGPUInstructionSelector.h

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Linesprivate:
void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
SmallVectorImpl<GEPInfo> &AddrInfo) const; SmallVectorImpl<GEPInfo> &AddrInfo) const;
bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const; bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
bool selectG_LOAD(MachineInstr &I) const; bool selectG_LOAD(MachineInstr &I) const;
bool selectG_STORE(MachineInstr &I) const; bool selectG_STORE(MachineInstr &I) const;
InstructionSelector::ComplexRendererFns InstructionSelector::ComplexRendererFns
selectVOP3Mods0(MachineOperand &Root) const; selectVOP3Mods0(MachineOperand &Root) const;
InstructionSelector::ComplexRendererFns
selectVOP3Mods(MachineOperand &Root) const;
const SIInstrInfo &TII; const SIInstrInfo &TII;
const SIRegisterInfo &TRI; const SIRegisterInfo &TRI;
const AMDGPURegisterBankInfo &RBI; const AMDGPURegisterBankInfo &RBI;
const AMDGPUTargetMachine &TM; const AMDGPUTargetMachine &TM;
const SISubtarget &STI; const SISubtarget &STI;
bool EnableLateStructurizeCFG; bool EnableLateStructurizeCFG;
#define GET_GLOBALISEL_PREDICATES_DECL #define GET_GLOBALISEL_PREDICATES_DECL
Show All 13 Lines

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 588 Lines • ▼ Show 20 Lines if (!isPreISelGenericOpcode(I.getOpcode())) {
if (I.isCopy()) if (I.isCopy())
return selectCOPY(I); return selectCOPY(I);
return true; return true;
} }
switch (I.getOpcode()) { switch (I.getOpcode()) {
default: default:
break; break;
case TargetOpcode::G_FMUL:
case TargetOpcode::G_FADD:
case TargetOpcode::G_FPTOUI: case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_OR: case TargetOpcode::G_OR:
return selectImpl(I, CoverageInfo); return selectImpl(I, CoverageInfo);
case TargetOpcode::G_ADD: case TargetOpcode::G_ADD:
return selectG_ADD(I); return selectG_ADD(I);
case TargetOpcode::G_BITCAST: case TargetOpcode::G_BITCAST:
return selectCOPY(I); return selectCOPY(I);
case TargetOpcode::G_CONSTANT: case TargetOpcode::G_CONSTANT:
Show All 19 Lines
AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const { AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
return {{ return {{
[=](MachineInstrBuilder &MIB) { MIB.add(Root); }, [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
}}; }};
} }
InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const {
return {{
[=](MachineInstrBuilder &MIB) { MIB.add(Root); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods
}};
}

test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir

  • This file was added.
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
--- |
define amdgpu_kernel void @fadd(i32 addrspace(1)* %global0) {ret void}
arsenmUnsubmitted
Not Done
ReplyInline Actions

I think you can drop the IR

arsenm: I think you can drop the IR
tstellarAuthorUnsubmitted
Not Done
ReplyInline Actions

The Machine IR needs the %global0 reference.

tstellar: The Machine IR needs the %global0 reference.
...
---
name: fadd
legalized: true
regBankSelected: true
# GCN-LABEL: name: fadd
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
%3:vgpr(s64) = COPY $vgpr3_vgpr4
; fadd vs
; GCN: V_ADD_F32_e64
%4:vgpr(s32) = G_FADD %1, %0
; fadd sv
; GCN: V_ADD_F32_e64
%5:vgpr(s32) = G_FADD %0, %1
; fadd vv
; GCN: V_ADD_F32_e64
%6:vgpr(s32) = G_FADD %1, %2
G_STORE %4, %3 :: (store 4 into %ir.global0)
G_STORE %5, %3 :: (store 4 into %ir.global0)
G_STORE %6, %3 :: (store 4 into %ir.global0)
...
---

test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir

  • This file was added.
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
--- |
define amdgpu_kernel void @fmul(i32 addrspace(1)* %global0) {ret void}
...
---
name: fmul
legalized: true
regBankSelected: true
# GCN-LABEL: name: fmul
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
%3:vgpr(s64) = COPY $vgpr3_vgpr4
; fmul vs
; GCN: V_MUL_F32_e64
%4:vgpr(s32) = G_FMUL %1, %0
; fmul sv
; GCN: V_MUL_F32_e64
%5:vgpr(s32) = G_FMUL %0, %1
; fmul vv
; GCN: V_MUL_F32_e64
%6:vgpr(s32) = G_FMUL %1, %2
G_STORE %4, %3 :: (store 4 into %ir.global0)
G_STORE %5, %3 :: (store 4 into %ir.global0)
G_STORE %6, %3 :: (store 4 into %ir.global0)
...
---